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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S102_KEIL/] [init/] [Startup.s] - Blame information for rev 581

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;/*****************************************************************************/
;/* STARTUP.S: Startup file for Luminary Micro LM3Sxxx                        */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>>                          */ 
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools.                   */
;/* Copyright (c) 2005-2006 Keil Software. All rights reserved.               */
;/* This software may only be used under the terms of a valid, current,       */
;/* end user licence from KEIL for a compatible version of KEIL software      */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
 
 
;/*
; *  The STARTUP.S code is executed after CPU Reset. 
; */
 
 
;// <h> Stack Configuration
;//   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;// </h>
 
Stack_Size      EQU     51
 
                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size
 
 
;// <h> Heap Configuration
;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;// </h>
 
Heap_Size       EQU     0x00000000
 
                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem        SPACE   Heap_Size
 
 
; System Control Register Addresses
SYSCTL_BASE     EQU     0x400FE000      ; System Control Base Address
PBORCTL_OFS     EQU     0x0030          ; Power-On & Brown-Out Reset Control
LDOPC_OFS       EQU     0x0034          ; LDO Power
SRCR0_OFS       EQU     0x0040          ; Software Reset Control 0
SRCR1_OFS       EQU     0x0044          ; Software Reset Control 1
SRCR2_OFS       EQU     0x0048          ; Software Reset Control 2
RCC_OFS         EQU     0x0060          ; Run-Mode Clock Control
RCGC0_OFS       EQU     0x0100          ; Run-Mode Clock Gating Control 0
RCGC1_OFS       EQU     0x0104          ; Run-Mode Clock Gating Control 1
RCGC2_OFS       EQU     0x0108          ; Run-Mode Clock Gating Control 2
SCGC0_OFS       EQU     0x0110          ; Sleep-Mode Clock Gating Control 0
SCGC1_OFS       EQU     0x0114          ; Sleep-Mode Clock Gating Control 1
SCGC2_OFS       EQU     0x0118          ; Sleep-Mode Clock Gating Control 2
DCGC0_OFS       EQU     0x0120          ; Deep-Sleep-Mode Clock Gating Control 0
DCGC1_OFS       EQU     0x0124          ; Deep-Sleep-Mode Clock Gating Control 1
DCGC2_OFS       EQU     0x0128          ; Deep-Sleep-Mode Clock Gating Control 2
 
 
                PRESERVE8
 
 
; Area Definition and Entry Point
;  Startup Code must be linked first at Address 0.
 
                AREA    RESET, CODE, READONLY
                THUMB
 
                                IMPORT  xPortPendSVHandler
                                IMPORT  xPortSysTickHandler
                                IMPORT  vUART_ISR
                                IMPORT  vPortSVCHandler
 
; Vector Table
                                EXPORT __Vectors
__Vectors       DCD     Stack_Mem + Stack_Size  ; Top of Stack
                DCD     Reset_Handler                   ; Reset Handler
                DCD     NmiSR                           ; NMI Handler
                DCD     DefaultISR                      ; Hard Fault Handler
                DCD     DefaultISR                      ; MPU Fault Handler
                DCD     DefaultISR                      ; Bus Fault Handler
                DCD     DefaultISR                      ; Usage Fault Handler
                DCD     0                       ; Reserved
                DCD     0                       ; Reserved
                DCD     0                       ; Reserved
                DCD     0                       ; Reserved
                DCD     vPortSVCHandler         ; SVCall Handler
                DCD     DefaultISR                      ; Debug Monitor Handler
                DCD     0                       ; Reserved
                DCD     xPortPendSVHandler      ; PendSV Handler
                DCD     xPortSysTickHandler     ; SysTick Handler
                DCD     DefaultISR              ; GPIO Port A Handler
                DCD     DefaultISR              ; GPIO Port B Handler
                DCD     DefaultISR              ; GPIO Port C Handler
                DCD     DefaultISR              ; GPIO Port D Handler
                DCD     DefaultISR              ; GPIO Port E Handler
                DCD     vUART_ISR                       ; UART0 Rx/Tx Handler
                DCD     DefaultISR              ; UART1 Rx/Tx Handler
                DCD     DefaultISR              ; SSI Rx/Tx Handler
                DCD     DefaultISR              ; I2C Master/Slave Handler
                DCD     DefaultISR         ; PWM Fault Handler
                DCD     DefaultISR         ; PWM Generator 0 Handler
                DCD     DefaultISR         ; PWM Generator 1 Handler
                DCD     DefaultISR         ; PWM Generator 2 Handler
                DCD     DefaultISR         ; Quadrature Encoder Handler
                DCD     DefaultISR         ; ADC Sequence 0 Handler
                DCD     DefaultISR         ; ADC Sequence 1 Handler
                DCD     DefaultISR         ; ADC Sequence 2 Handler
                DCD     DefaultISR         ; ADC Sequence 3 Handler
                DCD     DefaultISR         ; Watchdog Timer Handler
                DCD     DefaultISR         ; Timer 0 Subtimer A Handler
                DCD     DefaultISR         ; Timer 0 Subtimer B Handler
                DCD     DefaultISR         ; Timer 1 Subtimer A Handler
                DCD     DefaultISR         ; Timer 1 Subtimer B Handler
                DCD     DefaultISR         ; Timer 2 Subtimer A Handler
                DCD     DefaultISR         ; Timer 2 Subtimer B Handler
                DCD     DefaultISR         ; Analog Comparator 0 Handler
                DCD     DefaultISR         ; Analog Comparator 1 Handler
                DCD     DefaultISR         ; Analog Comparator 2 Handler
                DCD     DefaultISR         ; System Control Handler
                DCD     DefaultISR         ; Flash Control Handler
 
; Dummy Handlers are implemented as infinite loops which can be modified.
 
NmiSR                   B       NmiSR
FaultISR                B               FaultISR
                                EXPORT FaultISR
DefaultISR              B       DefaultISR
 
 
; Reset Handler
 
                EXPORT  Reset_Handler
Reset_Handler
 
; Enable Clock Gating for Peripherals
;                LDR     R0, =SYSCTL_BASE        ; System Control Base Address
;                MVN     R1, #0                  ; Value 0xFFFFFFFF
;                STR     R1, [R0,#RCGC0_OFS]     ; Run-Mode Clock Gating Ctrl 0
;                STR     R1, [R0,#RCGC1_OFS]     ; Run-Mode Clock Gating Ctrl 1
;                STR     R1, [R0,#RCGC2_OFS]     ; Run-Mode Clock Gating Ctrl 2
 
; Enter the C code
 
                IMPORT  __main
                LDR     R0, =__main
                BX      R0
 
 
; User Initial Stack & Heap
                AREA    |.text|, CODE, READONLY
 
                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap
 
                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + Stack_Size)
                LDR     R2, = (Heap_Mem +  Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR
 
                ALIGN
 
 
                END

Line No.	Rev	Author	Line
1	581	jeremybenn	`;/*****************************************************************************/`
2			`;/* STARTUP.S: Startup file for Luminary Micro LM3Sxxx */`
3			`;/*****************************************************************************/`
4			`;/* <<< Use Configuration Wizard in Context Menu >>> */`
5			`;/*****************************************************************************/`
6			`;/* This file is part of the uVision/ARM development tools. */`
7			`;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */`
8			`;/* This software may only be used under the terms of a valid, current, */`
9			`;/* end user licence from KEIL for a compatible version of KEIL software */`
10			`;/* development tools. Nothing else gives you the right to use this software. */`
11			`;/*****************************************************************************/`
12
13
14			`;/*`
15			`; * The STARTUP.S code is executed after CPU Reset.`
16			`; */`
17
18
19			`;// <h> Stack Configuration`
20			`;// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>`
21			`;// </h>`
22
23			`Stack_Size EQU 51`
24
25			`AREA STACK, NOINIT, READWRITE, ALIGN=3`
26			`Stack_Mem SPACE Stack_Size`
27
28
29			`;// <h> Heap Configuration`
30			`;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>`
31			`;// </h>`
32
33			`Heap_Size EQU 0x00000000`
34
35			`AREA HEAP, NOINIT, READWRITE, ALIGN=3`
36			`Heap_Mem SPACE Heap_Size`
37
38
39			`; System Control Register Addresses`
40			`SYSCTL_BASE EQU 0x400FE000 ; System Control Base Address`
41			`PBORCTL_OFS EQU 0x0030 ; Power-On & Brown-Out Reset Control`
42			`LDOPC_OFS EQU 0x0034 ; LDO Power`
43			`SRCR0_OFS EQU 0x0040 ; Software Reset Control 0`
44			`SRCR1_OFS EQU 0x0044 ; Software Reset Control 1`
45			`SRCR2_OFS EQU 0x0048 ; Software Reset Control 2`
46			`RCC_OFS EQU 0x0060 ; Run-Mode Clock Control`
47			`RCGC0_OFS EQU 0x0100 ; Run-Mode Clock Gating Control 0`
48			`RCGC1_OFS EQU 0x0104 ; Run-Mode Clock Gating Control 1`
49			`RCGC2_OFS EQU 0x0108 ; Run-Mode Clock Gating Control 2`
50			`SCGC0_OFS EQU 0x0110 ; Sleep-Mode Clock Gating Control 0`
51			`SCGC1_OFS EQU 0x0114 ; Sleep-Mode Clock Gating Control 1`
52			`SCGC2_OFS EQU 0x0118 ; Sleep-Mode Clock Gating Control 2`
53			`DCGC0_OFS EQU 0x0120 ; Deep-Sleep-Mode Clock Gating Control 0`
54			`DCGC1_OFS EQU 0x0124 ; Deep-Sleep-Mode Clock Gating Control 1`
55			`DCGC2_OFS EQU 0x0128 ; Deep-Sleep-Mode Clock Gating Control 2`
56
57
58			`PRESERVE8`
59
60
61			`; Area Definition and Entry Point`
62			`; Startup Code must be linked first at Address 0.`
63
64			`AREA RESET, CODE, READONLY`
65			`THUMB`
66
67			`IMPORT xPortPendSVHandler`
68			`IMPORT xPortSysTickHandler`
69			`IMPORT vUART_ISR`
70			`IMPORT vPortSVCHandler`
71
72			`; Vector Table`
73			`EXPORT __Vectors`
74			`__Vectors DCD Stack_Mem + Stack_Size ; Top of Stack`
75			`DCD Reset_Handler ; Reset Handler`
76			`DCD NmiSR ; NMI Handler`
77			`DCD DefaultISR ; Hard Fault Handler`
78			`DCD DefaultISR ; MPU Fault Handler`
79			`DCD DefaultISR ; Bus Fault Handler`
80			`DCD DefaultISR ; Usage Fault Handler`
81			`DCD 0 ; Reserved`
82			`DCD 0 ; Reserved`
83			`DCD 0 ; Reserved`
84			`DCD 0 ; Reserved`
85			`DCD vPortSVCHandler ; SVCall Handler`
86			`DCD DefaultISR ; Debug Monitor Handler`
87			`DCD 0 ; Reserved`
88			`DCD xPortPendSVHandler ; PendSV Handler`
89			`DCD xPortSysTickHandler ; SysTick Handler`
90			`DCD DefaultISR ; GPIO Port A Handler`
91			`DCD DefaultISR ; GPIO Port B Handler`
92			`DCD DefaultISR ; GPIO Port C Handler`
93			`DCD DefaultISR ; GPIO Port D Handler`
94			`DCD DefaultISR ; GPIO Port E Handler`
95			`DCD vUART_ISR ; UART0 Rx/Tx Handler`
96			`DCD DefaultISR ; UART1 Rx/Tx Handler`
97			`DCD DefaultISR ; SSI Rx/Tx Handler`
98			`DCD DefaultISR ; I2C Master/Slave Handler`
99			`DCD DefaultISR ; PWM Fault Handler`
100			`DCD DefaultISR ; PWM Generator 0 Handler`
101			`DCD DefaultISR ; PWM Generator 1 Handler`
102			`DCD DefaultISR ; PWM Generator 2 Handler`
103			`DCD DefaultISR ; Quadrature Encoder Handler`
104			`DCD DefaultISR ; ADC Sequence 0 Handler`
105			`DCD DefaultISR ; ADC Sequence 1 Handler`
106			`DCD DefaultISR ; ADC Sequence 2 Handler`
107			`DCD DefaultISR ; ADC Sequence 3 Handler`
108			`DCD DefaultISR ; Watchdog Timer Handler`
109			`DCD DefaultISR ; Timer 0 Subtimer A Handler`
110			`DCD DefaultISR ; Timer 0 Subtimer B Handler`
111			`DCD DefaultISR ; Timer 1 Subtimer A Handler`
112			`DCD DefaultISR ; Timer 1 Subtimer B Handler`
113			`DCD DefaultISR ; Timer 2 Subtimer A Handler`
114			`DCD DefaultISR ; Timer 2 Subtimer B Handler`
115			`DCD DefaultISR ; Analog Comparator 0 Handler`
116			`DCD DefaultISR ; Analog Comparator 1 Handler`
117			`DCD DefaultISR ; Analog Comparator 2 Handler`
118			`DCD DefaultISR ; System Control Handler`
119			`DCD DefaultISR ; Flash Control Handler`
120
121			`; Dummy Handlers are implemented as infinite loops which can be modified.`
122
123			`NmiSR B NmiSR`
124			`FaultISR B FaultISR`
125			`EXPORT FaultISR`
126			`DefaultISR B DefaultISR`
127
128
129			`; Reset Handler`
130
131			`EXPORT Reset_Handler`
132			`Reset_Handler`
133
134			`; Enable Clock Gating for Peripherals`
135			`; LDR R0, =SYSCTL_BASE ; System Control Base Address`
136			`; MVN R1, #0 ; Value 0xFFFFFFFF`
137			`; STR R1, [R0,#RCGC0_OFS] ; Run-Mode Clock Gating Ctrl 0`
138			`; STR R1, [R0,#RCGC1_OFS] ; Run-Mode Clock Gating Ctrl 1`
139			`; STR R1, [R0,#RCGC2_OFS] ; Run-Mode Clock Gating Ctrl 2`
140
141			`; Enter the C code`
142
143			`IMPORT __main`
144			`LDR R0, =__main`
145			`BX R0`
146
147
148			`; User Initial Stack & Heap`
149			`AREA \|.text\|, CODE, READONLY`
150
151			`IMPORT __use_two_region_memory`
152			`EXPORT __user_initial_stackheap`
153			`__user_initial_stackheap`
154
155			`LDR R0, = Heap_Mem`
156			`LDR R1, =(Stack_Mem + Stack_Size)`
157			`LDR R2, = (Heap_Mem + Heap_Size)`
158			`LDR R3, = Stack_Mem`
159			`BX LR`
160
161			`ALIGN`
162
163
164			`END`

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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S102_KEIL/] [init/] [Startup.s] - Blame information for rev 581