URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S102_Rowley/] [hw_include/] [pdc.c] - Blame information for rev 637

Go to most recent revision | Details | Compare with Previous | View Log


//*****************************************************************************
//
// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris
//         development board.
//
// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
//
// Software License Agreement
//
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's Stellaris Family of microcontroller products.
//
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws.  All rights are reserved.  Any use in violation
// of the foregoing restrictions may subject the user to criminal sanctions
// under applicable laws, as well as to civil liability for the breach of the
// terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 523 of the Stellaris Driver Library.
//
//*****************************************************************************
 
//*****************************************************************************
//
//! \addtogroup utilities_api
//! @{
//
//*****************************************************************************
 
#include "hw_memmap.h"
#include "hw_types.h"
#include "gpio.h"
#include "ssi.h"
#include "sysctl.h"
#include "pdc.h"
 
//*****************************************************************************
//
//! Initializes the connection to the PDC.
//!
//! This function will enable clocking to the SSI and GPIO A modules, configure
//! the GPIO pins to be used for an SSI interface, and it will configure the
//! SSI as a 1Mb master device, operating in MOTO mode.  It will also enable
//! the SSI module, and will enable the chip select for the PDC on the
//! Stellaris development board.
//!
//! This function is contained in <tt>utils/pdc.c</tt>, with
//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.
//!
//! \return None.
//
//*****************************************************************************
void
PDCInit(void)
{
    //
    // Enable the peripherals used to drive the PDC.
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
 
    //
    // Configure the appropriate pins to be SSI instead of GPIO.
    //
    GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX,
                   GPIO_DIR_MODE_HW);
    GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);
    GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,
                     GPIO_PIN_TYPE_STD_WPU);
 
    //
    // Configure the SSI port.
    //
    SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
    SSIEnable(SSI_BASE);
 
    //
    // Reset the PDC SSI state machine.  The chip select needs to be held low
    // for 100ns; the procedure call overhead more than accounts for this time.
    //
    GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);
    GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);
}
 
//*****************************************************************************
//
//! Write a PDC register.
//!
//! \param ucAddr specifies the PDC register to write.
//! \param ucData specifies the data to write.
//!
//! This function will perform the SSI transfers required to write a register
//! in the PDC on the Stellaris development board.
//!
//! This function is contained in <tt>utils/pdc.c</tt>, with
//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.
//!
//! \return None.
//
//*****************************************************************************
void
PDCWrite(unsigned char ucAddr, unsigned char ucData)
{
    unsigned long ulTemp;
 
    //
    // Send address and write command.
    //
    SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR);
 
    //
    // Write the data.
    //
    SSIDataPut(SSI_BASE, ucData);
 
    //
    // Flush data read during address write.
    //
    SSIDataGet(SSI_BASE, &ulTemp);
 
    //
    // Flush data read during data write.
    //
    SSIDataGet(SSI_BASE, &ulTemp);
}
 

Line No.	Rev	Author	Line
1	581	jeremybenn	`//*****************************************************************************`
2			`//`
3			`// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris`
4			`// development board.`
5			`//`
6			`// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.`
7			`//`
8			`// Software License Agreement`
9			`//`
10			`// Luminary Micro, Inc. (LMI) is supplying this software for use solely and`
11			`// exclusively on LMI's Stellaris Family of microcontroller products.`
12			`//`
13			`// The software is owned by LMI and/or its suppliers, and is protected under`
14			`// applicable copyright laws. All rights are reserved. Any use in violation`
15			`// of the foregoing restrictions may subject the user to criminal sanctions`
16			`// under applicable laws, as well as to civil liability for the breach of the`
17			`// terms and conditions of this license.`
18			`//`
19			`// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED`
20			`// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF`
21			`// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.`
22			`// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR`
23			`// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.`
24			`//`
25			`// This is part of revision 523 of the Stellaris Driver Library.`
26			`//`
27			`//*****************************************************************************`
28
29			`//*****************************************************************************`
30			`//`
31			`//! \addtogroup utilities_api`
32			`//! @{`
33			`//`
34			`//*****************************************************************************`
35
36			`#include "hw_memmap.h"`
37			`#include "hw_types.h"`
38			`#include "gpio.h"`
39			`#include "ssi.h"`
40			`#include "sysctl.h"`
41			`#include "pdc.h"`
42
43			`//*****************************************************************************`
44			`//`
45			`//! Initializes the connection to the PDC.`
46			`//!`
47			`//! This function will enable clocking to the SSI and GPIO A modules, configure`
48			`//! the GPIO pins to be used for an SSI interface, and it will configure the`
49			`//! SSI as a 1Mb master device, operating in MOTO mode. It will also enable`
50			`//! the SSI module, and will enable the chip select for the PDC on the`
51			`//! Stellaris development board.`
52			`//!`
53			`//! This function is contained in <tt>utils/pdc.c</tt>, with`
54			`//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.`
55			`//!`
56			`//! \return None.`
57			`//`
58			`//*****************************************************************************`
59			`void`
60			`PDCInit(void)`
61			`{`
62			`//`
63			`// Enable the peripherals used to drive the PDC.`
64			`//`
65			`SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);`
66			`SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);`
67
68			`//`
69			`// Configure the appropriate pins to be SSI instead of GPIO.`
70			`//`
71			`GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK \| SSI_TX \| SSI_RX,`
72			`GPIO_DIR_MODE_HW);`
73			`GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);`
74			`GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,`
75			`GPIO_PIN_TYPE_STD_WPU);`
76
77			`//`
78			`// Configure the SSI port.`
79			`//`
80			`SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);`
81			`SSIEnable(SSI_BASE);`
82
83			`//`
84			`// Reset the PDC SSI state machine. The chip select needs to be held low`
85			`// for 100ns; the procedure call overhead more than accounts for this time.`
86			`//`
87			`GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);`
88			`GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);`
89			`}`
90
91			`//*****************************************************************************`
92			`//`
93			`//! Write a PDC register.`
94			`//!`
95			`//! \param ucAddr specifies the PDC register to write.`
96			`//! \param ucData specifies the data to write.`
97			`//!`
98			`//! This function will perform the SSI transfers required to write a register`
99			`//! in the PDC on the Stellaris development board.`
100			`//!`
101			`//! This function is contained in <tt>utils/pdc.c</tt>, with`
102			`//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.`
103			`//!`
104			`//! \return None.`
105			`//`
106			`//*****************************************************************************`
107			`void`
108			`PDCWrite(unsigned char ucAddr, unsigned char ucData)`
109			`{`
110			`unsigned long ulTemp;`
111
112			`//`
113			`// Send address and write command.`
114			`//`
115			`SSIDataPut(SSI_BASE, (ucAddr & 0x0F) \| PDC_WR);`
116
117			`//`
118			`// Write the data.`
119			`//`
120			`SSIDataPut(SSI_BASE, ucData);`
121
122			`//`
123			`// Flush data read during address write.`
124			`//`
125			`SSIDataGet(SSI_BASE, &ulTemp);`
126
127			`//`
128			`// Flush data read during data write.`
129			`//`
130			`SSIDataGet(SSI_BASE, &ulTemp);`
131			`}`
132

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S102_Rowley/] [hw_include/] [pdc.c] - Blame information for rev 637