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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S316_IAR/] [hw_include/] [hw_sysctl.h] - Blame information for rev 581

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1 581 jeremybenn 
//*****************************************************************************
2 
//
3 
// hw_sysctl.h - Macros used when accessing the system control hardware.
4 
//
5 
// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
6 
//
7 
// Software License Agreement
8 
//
9 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10 
// exclusively on LMI's Stellaris Family of microcontroller products.
11 
//
12 
// The software is owned by LMI and/or its suppliers, and is protected under
13 
// applicable copyright laws.  All rights are reserved.  Any use in violation
14 
// of the foregoing restrictions may subject the user to criminal sanctions
15 
// under applicable laws, as well as to civil liability for the breach of the
16 
// terms and conditions of this license.
17 
//
18 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19 
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20 
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21 
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
22 
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23 
//
24 
// This is part of revision 635 of the Stellaris Driver Library.
25 
//
26 
//*****************************************************************************
27 
 
28 
#ifndef __HW_SYSCTL_H__
29 
#define __HW_SYSCTL_H__
30 
 
31 
//*****************************************************************************
32 
//
33 
// The following define the offsets of the system control registers.
34 
//
35 
//*****************************************************************************
36 
#define SYSCTL_DID0             0x400fe000  // Device identification register 0
37 
#define SYSCTL_DID1             0x400fe004  // Device identification register 1
38 
#define SYSCTL_DC0              0x400fe008  // Device capabilities register 0
39 
#define SYSCTL_DC1              0x400fe010  // Device capabilities register 1
40 
#define SYSCTL_DC2              0x400fe014  // Device capabilities register 2
41 
#define SYSCTL_DC3              0x400fe018  // Device capabilities register 3
42 
#define SYSCTL_DC4              0x400fe01C  // Device capabilities register 4
43 
#define SYSCTL_PBORCTL          0x400fe030  // POR/BOR reset control register
44 
#define SYSCTL_LDOPCTL          0x400fe034  // LDO power control register
45 
#define SYSCTL_SRCR0            0x400fe040  // Software reset control reg 0
46 
#define SYSCTL_SRCR1            0x400fe044  // Software reset control reg 1
47 
#define SYSCTL_SRCR2            0x400fe048  // Software reset control reg 2
48 
#define SYSCTL_RIS              0x400fe050  // Raw interrupt status register
49 
#define SYSCTL_IMC              0x400fe054  // Interrupt mask/control register
50 
#define SYSCTL_MISC             0x400fe058  // Interrupt status register
51 
#define SYSCTL_RESC             0x400fe05c  // Reset cause register
52 
#define SYSCTL_RCC              0x400fe060  // Run-mode clock config register
53 
#define SYSCTL_PLLCFG           0x400fe064  // PLL configuration register
54 
#define SYSCTL_RCGC0            0x400fe100  // Run-mode clock gating register 0
55 
#define SYSCTL_RCGC1            0x400fe104  // Run-mode clock gating register 1
56 
#define SYSCTL_RCGC2            0x400fe108  // Run-mode clock gating register 2
57 
#define SYSCTL_SCGC0            0x400fe110  // Sleep-mode clock gating reg 0
58 
#define SYSCTL_SCGC1            0x400fe114  // Sleep-mode clock gating reg 1
59 
#define SYSCTL_SCGC2            0x400fe118  // Sleep-mode clock gating reg 2
60 
#define SYSCTL_DCGC0            0x400fe120  // Deep Sleep-mode clock gate reg 0
61 
#define SYSCTL_DCGC1            0x400fe124  // Deep Sleep-mode clock gate reg 1
62 
#define SYSCTL_DCGC2            0x400fe128  // Deep Sleep-mode clock gate reg 2
63 
#define SYSCTL_CLKVCLR          0x400fe150  // Clock verifcation clear register
64 
#define SYSCTL_LDOARST          0x400fe160  // LDO reset control register
65 
 
66 
//*****************************************************************************
67 
//
68 
// The following define the bit fields in the SYSCTL_DID0 register.
69 
//
70 
//*****************************************************************************
71 
#define SYSCTL_DID0_VER_MASK    0x70000000  // DID0 version mask
72 
#define SYSCTL_DID0_VER_0       0x00000000  // DID0 version 0
73 
#define SYSCTL_DID0_MAJ_MASK    0x0000FF00  // Major revision mask
74 
#define SYSCTL_DID0_MAJ_A       0x00000000  // Major revision A
75 
#define SYSCTL_DID0_MAJ_B       0x00000100  // Major revision B
76 
#define SYSCTL_DID0_MIN_MASK    0x000000FF  // Minor revision mask
77 
#define SYSCTL_DID0_MIN_0       0x00000000  // Minor revision 0
78 
#define SYSCTL_DID0_MIN_1       0x00000001  // Minor revision 1
79 
 
80 
//*****************************************************************************
81 
//
82 
// The following define the bit fields in the SYSCTL_DID1 register.
83 
//
84 
//*****************************************************************************
85 
#define SYSCTL_DID1_VER_MASK    0xF0000000  // Register version mask
86 
#define SYSCTL_DID1_FAM_MASK    0x0F000000  // Family mask
87 
#define SYSCTL_DID1_FAM_S       0x00000000  // Stellaris family
88 
#define SYSCTL_DID1_PRTNO_MASK  0x00FF0000  // Part number mask
89 
#define SYSCTL_DID1_PRTNO_101   0x00010000  // LM3S101
90 
#define SYSCTL_DID1_PRTNO_102   0x00020000  // LM3S102
91 
#define SYSCTL_DID1_PRTNO_301   0x00110000  // LM3S301
92 
#define SYSCTL_DID1_PRTNO_310   0x00120000  // LM3S310
93 
#define SYSCTL_DID1_PRTNO_315   0x00130000  // LM3S315
94 
#define SYSCTL_DID1_PRTNO_316   0x00140000  // LM3S316
95 
#define SYSCTL_DID1_TEMP_MASK   0x000000E0  // Temperature range mask
96 
#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temp range (0..70C)
97 
#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temp range (-40..85C)
98 
#define SYSCTL_DID1_PKG_MASK    0x00000018  // Package mask
99 
#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // 28-pin SOIC
100 
#define SYSCTL_DID1_PKG_48QFP   0x00000008  // 48-pin QFP
101 
#define SYSCTL_DID1_ROHS        0x00000004  // Part is RoHS compliant
102 
#define SYSCTL_DID1_QUAL_MASK   0x00000003  // Qualification status mask
103 
#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering sample (unqualified)
104 
#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot production (unqualified)
105 
#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully qualified
106 
#define SYSCTL_DID1_PRTNO_SHIFT 16
107 
 
108 
//*****************************************************************************
109 
//
110 
// The following define the bit fields in the SYSCTL_DC0 register.
111 
//
112 
//*****************************************************************************
113 
#define SYSCTL_DC0_SRAMSZ_MASK  0xFFFF0000  // SRAM size mask
114 
#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2kB of SRAM
115 
#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4kB of SRAM
116 
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF  // Flash size mask
117 
#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8kB of flash
118 
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16kB of flash
119 
 
120 
//*****************************************************************************
121 
//
122 
// The following define the bit fields in the SYSCTL_DC1 register.
123 
//
124 
//*****************************************************************************
125 
#define SYSCTL_DC1_PWM          0x00100000  // PWM module present
126 
#define SYSCTL_DC1_ADC          0x00010000  // ADC module present
127 
#define SYSCTL_DC1_SYSDIV_MASK  0x0000F000  // Minimum system divider mask
128 
#define SYSCTL_DC1_ADCSPD_MASK  0x00000F00  // ADC speed mask
129 
#define SYSCTL_DC1_ADCSPD_250K  0x00000100  // 250Ksps ADC
130 
#define SYSCTL_DC1_ADCSPD_125K  0x00000000  // 125Ksps ADC
131 
#define SYSCTL_DC1_MPU          0x00000080  // Cortex M3 MPU present
132 
#define SYSCTL_DC1_TEMP         0x00000020  // Temperature sensor present
133 
#define SYSCTL_DC1_PLL          0x00000010  // PLL present
134 
#define SYSCTL_DC1_WDOG         0x00000008  // Watchdog present
135 
#define SYSCTL_DC1_SWO          0x00000004  // Serial wire output present
136 
#define SYSCTL_DC1_SWD          0x00000002  // Serial wire debug present
137 
#define SYSCTL_DC1_JTAG         0x00000001  // JTAG debug present
138 
 
139 
//*****************************************************************************
140 
//
141 
// The following define the bit fields in the SYSCTL_DC2 register.
142 
//
143 
//*****************************************************************************
144 
#define SYSCTL_DC2_COMP2        0x04000000  // Analog comparator 2 present
145 
#define SYSCTL_DC2_COMP1        0x02000000  // Analog comparator 1 present
146 
#define SYSCTL_DC2_COMP0        0x01000000  // Analog comparator 0 present
147 
#define SYSCTL_DC2_TIMER2       0x00040000  // Timer 2 present
148 
#define SYSCTL_DC2_TIMER1       0x00020000  // Timer 1 present
149 
#define SYSCTL_DC2_TIMER0       0x00010000  // Timer 0 present
150 
#define SYSCTL_DC2_I2C          0x00001000  // I2C present
151 
#define SYSCTL_DC2_SSI          0x00000010  // SSI present
152 
#define SYSCTL_DC2_UART1        0x00000002  // UART 1 present
153 
#define SYSCTL_DC2_UART0        0x00000001  // UART 0 present
154 
 
155 
//*****************************************************************************
156 
//
157 
// The following define the bit fields in the SYSCTL_DC3 register.
158 
//
159 
//*****************************************************************************
160 
#define SYSCTL_DC3_32KHZ        0x80000000  // 32kHz pin present
161 
#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 pin present
162 
#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 pin present
163 
#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 pin present
164 
#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 pin present
165 
#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 pin present
166 
#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 pin present
167 
#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 pin present
168 
#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 pin present
169 
#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 pin present
170 
#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 pin present
171 
#define SYSCTL_DC3_C2O          0x00004000  // C2o pin present
172 
#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ pin present
173 
#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- pin present
174 
#define SYSCTL_DC3_C1O          0x00000800  // C1o pin present
175 
#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ pin present
176 
#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- pin present
177 
#define SYSCTL_DC3_C0O          0x00000100  // C0o pin present
178 
#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ pin present
179 
#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- pin present
180 
#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 pin present
181 
#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 pin present
182 
#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 pin present
183 
#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 pin present
184 
#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 pin present
185 
#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 pin present
186 
 
187 
//*****************************************************************************
188 
//
189 
// The following define the bit fields in the SYSCTL_DC4 register.
190 
//
191 
//*****************************************************************************
192 
#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO port E present
193 
#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO port D present
194 
#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO port C present
195 
#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO port B present
196 
#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO port A present
197 
 
198 
//*****************************************************************************
199 
//
200 
// The following define the bit fields in the SYSCTL_PBORCTL register.
201 
//
202 
//*****************************************************************************
203 
#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC  // BOR wait timer
204 
#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR interrupt or reset
205 
#define SYSCTL_PBORCTL_BORWT    0x00000001  // BOR wait and check for noise
206 
#define SYSCTL_PBORCTL_BOR_SH   2
207 
 
208 
//*****************************************************************************
209 
//
210 
// The following define the bit fields in the SYSCTL_LDOPCTL register.
211 
//
212 
//*****************************************************************************
213 
#define SYSCTL_LDOPCTL_MASK     0x0000003F  // Voltage adjust mask
214 
#define SYSCTL_LDOPCTL_2_25V    0x00000005  // LDO output of 2.25V
215 
#define SYSCTL_LDOPCTL_2_30V    0x00000004  // LDO output of 2.30V
216 
#define SYSCTL_LDOPCTL_2_35V    0x00000003  // LDO output of 2.35V
217 
#define SYSCTL_LDOPCTL_2_40V    0x00000002  // LDO output of 2.40V
218 
#define SYSCTL_LDOPCTL_2_45V    0x00000001  // LDO output of 2.45V
219 
#define SYSCTL_LDOPCTL_2_50V    0x00000000  // LDO output of 2.50V
220 
#define SYSCTL_LDOPCTL_2_55V    0x0000001F  // LDO output of 2.55V
221 
#define SYSCTL_LDOPCTL_2_60V    0x0000001E  // LDO output of 2.60V
222 
#define SYSCTL_LDOPCTL_2_65V    0x0000001D  // LDO output of 2.65V
223 
#define SYSCTL_LDOPCTL_2_70V    0x0000001C  // LDO output of 2.70V
224 
#define SYSCTL_LDOPCTL_2_75V    0x0000001B  // LDO output of 2.75V
225 
 
226 
//*****************************************************************************
227 
//
228 
// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,
229 
// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
230 
//
231 
//*****************************************************************************
232 
#define SYSCTL_SET0_PWM         0x00100000  // PWM module
233 
#define SYSCTL_SET0_ADC         0x00010000  // ADC module
234 
#define SYSCTL_SET0_WDOG        0x00000008  // Watchdog module
235 
 
236 
//*****************************************************************************
237 
//
238 
// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,
239 
// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
240 
//
241 
//*****************************************************************************
242 
#define SYSCTL_SET1_COMP2       0x04000000  // Analog comparator module 2
243 
#define SYSCTL_SET1_COMP1       0x02000000  // Analog comparator module 1
244 
#define SYSCTL_SET1_COMP0       0x01000000  // Analog comparator module 0
245 
#define SYSCTL_SET1_TIMER2      0x00040000  // Timer module 2
246 
#define SYSCTL_SET1_TIMER1      0x00020000  // Timer module 1
247 
#define SYSCTL_SET1_TIMER0      0x00010000  // Timer module 0
248 
#define SYSCTL_SET1_I2C         0x00001000  // I2C module
249 
#define SYSCTL_SET1_SSI         0x00000010  // SSI module
250 
#define SYSCTL_SET1_UART1       0x00000002  // UART module 1
251 
#define SYSCTL_SET1_UART0       0x00000001  // UART module 0
252 
 
253 
//*****************************************************************************
254 
//
255 
// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,
256 
// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
257 
//
258 
//*****************************************************************************
259 
#define SYSCTL_SET2_GPIOE       0x00000010  // GPIO E module
260 
#define SYSCTL_SET2_GPIOD       0x00000008  // GPIO D module
261 
#define SYSCTL_SET2_GPIOC       0x00000004  // GPIO C module
262 
#define SYSCTL_SET2_GPIOB       0x00000002  // GPIO B module
263 
#define SYSCTL_SET2_GPIOA       0x00000001  // GIPO A module
264 
 
265 
//*****************************************************************************
266 
//
267 
// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and
268 
// SYSCTL_IMS registers.
269 
//
270 
//*****************************************************************************
271 
#define SYSCTL_INT_PLL_LOCK     0x00000040  // PLL lock interrupt
272 
#define SYSCTL_INT_CUR_LIMIT    0x00000020  // Current limit interrupt
273 
#define SYSCTL_INT_IOSC_FAIL    0x00000010  // Internal oscillator failure int
274 
#define SYSCTL_INT_MOSC_FAIL    0x00000008  // Main oscillator failure int
275 
#define SYSCTL_INT_POR          0x00000004  // Power on reset interrupt
276 
#define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt
277 
#define SYSCTL_INT_PLL_FAIL     0x00000001  // PLL failure interrupt
278 
 
279 
//*****************************************************************************
280 
//
281 
// The following define the bit fields in the SYSCTL_RESC register.
282 
//
283 
//*****************************************************************************
284 
#define SYSCTL_RESC_LDO         0x00000020  // LDO power OK lost reset
285 
#define SYSCTL_RESC_SW          0x00000010  // Software reset
286 
#define SYSCTL_RESC_WDOG        0x00000008  // Watchdog reset
287 
#define SYSCTL_RESC_BOR         0x00000004  // Brown-out reset
288 
#define SYSCTL_RESC_POR         0x00000002  // Power on reset
289 
#define SYSCTL_RESC_EXT         0x00000001  // External reset
290 
 
291 
//*****************************************************************************
292 
//
293 
// The following define the bit fields in the SYSCTL_RCC register.
294 
//
295 
//*****************************************************************************
296 
#define SYSCTL_RCC_ACG          0x08000000  // Automatic clock gating
297 
#define SYSCTL_RCC_SYSDIV_MASK  0x07800000  // System clock divider
298 
#define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2
299 
#define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3
300 
#define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4
301 
#define SYSCTL_RCC_SYSDIV_5     0x02000000  // System clock /5
302 
#define SYSCTL_RCC_SYSDIV_6     0x02800000  // System clock /6
303 
#define SYSCTL_RCC_SYSDIV_7     0x03000000  // System clock /7
304 
#define SYSCTL_RCC_SYSDIV_8     0x03800000  // System clock /8
305 
#define SYSCTL_RCC_SYSDIV_9     0x04000000  // System clock /9
306 
#define SYSCTL_RCC_SYSDIV_10    0x04800000  // System clock /10
307 
#define SYSCTL_RCC_SYSDIV_11    0x05000000  // System clock /11
308 
#define SYSCTL_RCC_SYSDIV_12    0x05800000  // System clock /12
309 
#define SYSCTL_RCC_SYSDIV_13    0x06000000  // System clock /13
310 
#define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14
311 
#define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15
312 
#define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16
313 
#define SYSCTL_RCC_USE_SYSDIV   0x00400000  // Use sytem clock divider
314 
#define SYSCTL_RCC_USE_PWMDIV   0x00100000  // Use PWM clock divider
315 
#define SYSCTL_RCC_PWMDIV_MASK  0x000E0000  // PWM clock divider
316 
#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
317 
#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
318 
#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
319 
#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
320 
#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
321 
#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
322 
#define SYSCTL_RCC_PWRDN        0x00002000  // PLL power down
323 
#define SYSCTL_RCC_OE           0x00001000  // PLL output enable
324 
#define SYSCTL_RCC_BYPASS       0x00000800  // PLL bypass
325 
#define SYSCTL_RCC_PLLVER       0x00000400  // PLL verification timer enable
326 
#define SYSCTL_RCC_XTAL_MASK    0x000003C0  // Crystal attached to main osc
327 
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // Using a 3.579545MHz crystal
328 
#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140  // Using a 3.6864MHz crystal
329 
#define SYSCTL_RCC_XTAL_4MHz    0x00000180  // Using a 4MHz crystal
330 
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // Using a 4.096MHz crystal
331 
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // Using a 4.9152MHz crystal
332 
#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // Using a 5MHz crystal
333 
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // Using a 5.12MHz crystal
334 
#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // Using a 6MHz crystal
335 
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // Using a 6.144MHz crystal
336 
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // Using a 7.3728MHz crystal
337 
#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // Using a 8MHz crystal
338 
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // Using a 8.192MHz crystal
339 
#define SYSCTL_RCC_OSCSRC_MASK  0x00000030  // Oscillator input select
340 
#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // Use the main oscillator
341 
#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // Use the internal oscillator
342 
#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // Use the internal oscillator / 4
343 
#define SYSCTL_RCC_IOSCVER      0x00000008  // Int. osc. verification timer en
344 
#define SYSCTL_RCC_MOSCVER      0x00000004  // Main osc. verification timer en
345 
#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal oscillator disable
346 
#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main oscillator disable
347 
#define SYSCTL_RCC_SYSDIV_SHIFT 23          // Shift to the SYSDIV field
348 
#define SYSCTL_RCC_PWMDIV_SHIFT 17          // Shift to the PWMDIV field
349 
#define SYSCTL_RCC_XTAL_SHIFT   6           // Shift to the XTAL field
350 
#define SYSCTL_RCC_OSCSRC_SHIFT 4           // Shift to the OSCSRC field
351 
 
352 
//*****************************************************************************
353 
//
354 
// The following define the bit fields in the SYSCTL_PLLCFG register.
355 
//
356 
//*****************************************************************************
357 
#define SYSCTL_PLLCFG_OD_MASK   0x0000C000  // Output divider
358 
#define SYSCTL_PLLCFG_OD_1      0x00000000  // Output divider is 1
359 
#define SYSCTL_PLLCFG_OD_2      0x00004000  // Output divider is 2
360 
#define SYSCTL_PLLCFG_OD_4      0x00008000  // Output divider is 4
361 
#define SYSCTL_PLLCFG_F_MASK    0x00003FE0  // PLL multiplier
362 
#define SYSCTL_PLLCFG_R_MASK    0x0000001F  // Input predivider
363 
#define SYSCTL_PLLCFG_F_SHIFT   5
364 
#define SYSCTL_PLLCFG_R_SHIFT   0
365 
 
366 
//*****************************************************************************
367 
//
368 
// The following define the bit fields in the SYSCTL_CLKVCLR register.
369 
//
370 
//*****************************************************************************
371 
#define SYSCTL_CLKVCLR_CLR      0x00000001  // Clear clock verification fault
372 
 
373 
//*****************************************************************************
374 
//
375 
// The following define the bit fields in the SYSCTL_LDOARST register.
376 
//
377 
//*****************************************************************************
378 
#define SYSCTL_LDOARST_ARST     0x00000001  // Allow LDO to reset device
379 
 
380 
#endif // __HW_SYSCTL_H__

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