1 |
581 |
jeremybenn |
//*****************************************************************************
|
2 |
|
|
//
|
3 |
|
|
// sysctl.h - Prototypes for the system control driver.
|
4 |
|
|
//
|
5 |
|
|
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
6 |
|
|
//
|
7 |
|
|
// Software License Agreement
|
8 |
|
|
//
|
9 |
|
|
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
10 |
|
|
// exclusively on LMI's Stellaris Family of microcontroller products.
|
11 |
|
|
//
|
12 |
|
|
// The software is owned by LMI and/or its suppliers, and is protected under
|
13 |
|
|
// applicable copyright laws. All rights are reserved. Any use in violation
|
14 |
|
|
// of the foregoing restrictions may subject the user to criminal sanctions
|
15 |
|
|
// under applicable laws, as well as to civil liability for the breach of the
|
16 |
|
|
// terms and conditions of this license.
|
17 |
|
|
//
|
18 |
|
|
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
19 |
|
|
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
20 |
|
|
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
21 |
|
|
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
22 |
|
|
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
23 |
|
|
//
|
24 |
|
|
// This is part of revision 635 of the Stellaris Driver Library.
|
25 |
|
|
//
|
26 |
|
|
//*****************************************************************************
|
27 |
|
|
|
28 |
|
|
#ifndef __SYSCTL_H__
|
29 |
|
|
#define __SYSCTL_H__
|
30 |
|
|
|
31 |
|
|
#ifdef __cplusplus
|
32 |
|
|
extern "C"
|
33 |
|
|
{
|
34 |
|
|
#endif
|
35 |
|
|
|
36 |
|
|
//*****************************************************************************
|
37 |
|
|
//
|
38 |
|
|
// The following are values that can be passed to the
|
39 |
|
|
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
|
40 |
|
|
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
|
41 |
|
|
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
|
42 |
|
|
// is 3) can only be used with the SysCtlPeripheralPresent() API.
|
43 |
|
|
//
|
44 |
|
|
//*****************************************************************************
|
45 |
|
|
#define SYSCTL_PERIPH_PWM 0x00100000 // PWM
|
46 |
|
|
#define SYSCTL_PERIPH_ADC 0x00010000 // ADC
|
47 |
|
|
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
|
48 |
|
|
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
|
49 |
|
|
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
|
50 |
|
|
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
|
51 |
|
|
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
|
52 |
|
|
#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0
|
53 |
|
|
#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1
|
54 |
|
|
#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2
|
55 |
|
|
#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0
|
56 |
|
|
#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1
|
57 |
|
|
#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2
|
58 |
|
|
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
|
59 |
|
|
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
|
60 |
|
|
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
|
61 |
|
|
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
|
62 |
|
|
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
|
63 |
|
|
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
|
64 |
|
|
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
|
65 |
|
|
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
|
66 |
|
|
|
67 |
|
|
//*****************************************************************************
|
68 |
|
|
//
|
69 |
|
|
// The following are values that can be passed to the SysCtlPinPresent() API
|
70 |
|
|
// as the ulPin parameter.
|
71 |
|
|
//
|
72 |
|
|
//*****************************************************************************
|
73 |
|
|
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
|
74 |
|
|
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
|
75 |
|
|
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
|
76 |
|
|
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
|
77 |
|
|
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
|
78 |
|
|
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
|
79 |
|
|
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
|
80 |
|
|
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
|
81 |
|
|
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
|
82 |
|
|
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
|
83 |
|
|
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
|
84 |
|
|
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
|
85 |
|
|
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
|
86 |
|
|
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
|
87 |
|
|
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
|
88 |
|
|
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
|
89 |
|
|
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
|
90 |
|
|
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
|
91 |
|
|
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
|
92 |
|
|
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
|
93 |
|
|
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
|
94 |
|
|
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
|
95 |
|
|
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
|
96 |
|
|
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
|
97 |
|
|
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
|
98 |
|
|
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
|
99 |
|
|
|
100 |
|
|
//*****************************************************************************
|
101 |
|
|
//
|
102 |
|
|
// The following are values that can be passed to the SysCtlLDOSet() API as
|
103 |
|
|
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
|
104 |
|
|
//
|
105 |
|
|
//*****************************************************************************
|
106 |
|
|
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
|
107 |
|
|
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
|
108 |
|
|
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
|
109 |
|
|
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
|
110 |
|
|
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
|
111 |
|
|
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
|
112 |
|
|
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
|
113 |
|
|
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
|
114 |
|
|
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
|
115 |
|
|
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
|
116 |
|
|
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
|
117 |
|
|
|
118 |
|
|
//*****************************************************************************
|
119 |
|
|
//
|
120 |
|
|
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
|
121 |
|
|
//
|
122 |
|
|
//*****************************************************************************
|
123 |
|
|
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
|
124 |
|
|
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
|
125 |
|
|
|
126 |
|
|
//*****************************************************************************
|
127 |
|
|
//
|
128 |
|
|
// The following are values that can be passed to the SysCtlIntEnable(),
|
129 |
|
|
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
|
130 |
|
|
// by the SysCtlIntStatus() API.
|
131 |
|
|
//
|
132 |
|
|
//*****************************************************************************
|
133 |
|
|
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
|
134 |
|
|
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
|
135 |
|
|
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
|
136 |
|
|
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
|
137 |
|
|
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
|
138 |
|
|
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
|
139 |
|
|
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
|
140 |
|
|
|
141 |
|
|
//*****************************************************************************
|
142 |
|
|
//
|
143 |
|
|
// The following are values that can be passed to the SysCtlResetCauseClear()
|
144 |
|
|
// API or returned by the SysCtlResetCauseGet() API.
|
145 |
|
|
//
|
146 |
|
|
//*****************************************************************************
|
147 |
|
|
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
|
148 |
|
|
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
|
149 |
|
|
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
|
150 |
|
|
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
|
151 |
|
|
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
|
152 |
|
|
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
|
153 |
|
|
|
154 |
|
|
//*****************************************************************************
|
155 |
|
|
//
|
156 |
|
|
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
|
157 |
|
|
// API as the ulConfig parameter.
|
158 |
|
|
//
|
159 |
|
|
//*****************************************************************************
|
160 |
|
|
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
|
161 |
|
|
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
|
162 |
|
|
|
163 |
|
|
//*****************************************************************************
|
164 |
|
|
//
|
165 |
|
|
// The following are values that can be passed to the SysCtlPWMClockSet() API
|
166 |
|
|
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
|
167 |
|
|
// API.
|
168 |
|
|
//
|
169 |
|
|
//*****************************************************************************
|
170 |
|
|
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
|
171 |
|
|
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
|
172 |
|
|
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
|
173 |
|
|
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
|
174 |
|
|
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
|
175 |
|
|
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
|
176 |
|
|
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
|
177 |
|
|
|
178 |
|
|
//*****************************************************************************
|
179 |
|
|
//
|
180 |
|
|
// The following are values that can be passed to the SysCtlClockSet() API as
|
181 |
|
|
// the ulConfig parameter.
|
182 |
|
|
//
|
183 |
|
|
//*****************************************************************************
|
184 |
|
|
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
|
185 |
|
|
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
|
186 |
|
|
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
|
187 |
|
|
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
|
188 |
|
|
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
|
189 |
|
|
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
|
190 |
|
|
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
|
191 |
|
|
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
|
192 |
|
|
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
|
193 |
|
|
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
|
194 |
|
|
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
|
195 |
|
|
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
|
196 |
|
|
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
|
197 |
|
|
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
|
198 |
|
|
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
|
199 |
|
|
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
|
200 |
|
|
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
|
201 |
|
|
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
|
202 |
|
|
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
|
203 |
|
|
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
|
204 |
|
|
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
|
205 |
|
|
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
|
206 |
|
|
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
|
207 |
|
|
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
|
208 |
|
|
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
|
209 |
|
|
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
|
210 |
|
|
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
|
211 |
|
|
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
|
212 |
|
|
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
|
213 |
|
|
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
|
214 |
|
|
#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc
|
215 |
|
|
#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc
|
216 |
|
|
#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4
|
217 |
|
|
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
|
218 |
|
|
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
|
219 |
|
|
|
220 |
|
|
//*****************************************************************************
|
221 |
|
|
//
|
222 |
|
|
// Prototypes for the APIs.
|
223 |
|
|
//
|
224 |
|
|
//*****************************************************************************
|
225 |
|
|
extern unsigned long SysCtlSRAMSizeGet(void);
|
226 |
|
|
extern unsigned long SysCtlFlashSizeGet(void);
|
227 |
|
|
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
|
228 |
|
|
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
|
229 |
|
|
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
|
230 |
|
|
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
|
231 |
|
|
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
|
232 |
|
|
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
|
233 |
|
|
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
|
234 |
|
|
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
|
235 |
|
|
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
|
236 |
|
|
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
|
237 |
|
|
extern void SysCtlIntRegister(void (*pfnHandler)(void));
|
238 |
|
|
extern void SysCtlIntUnregister(void);
|
239 |
|
|
extern void SysCtlIntEnable(unsigned long ulInts);
|
240 |
|
|
extern void SysCtlIntDisable(unsigned long ulInts);
|
241 |
|
|
extern void SysCtlIntClear(unsigned long ulInts);
|
242 |
|
|
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
|
243 |
|
|
extern void SysCtlLDOSet(unsigned long ulVoltage);
|
244 |
|
|
extern unsigned long SysCtlLDOGet(void);
|
245 |
|
|
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
|
246 |
|
|
extern void SysCtlReset(void);
|
247 |
|
|
extern void SysCtlSleep(void);
|
248 |
|
|
extern void SysCtlDeepSleep(void);
|
249 |
|
|
extern unsigned long SysCtlResetCauseGet(void);
|
250 |
|
|
extern void SysCtlResetCauseClear(unsigned long ulCauses);
|
251 |
|
|
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
|
252 |
|
|
unsigned long ulDelay);
|
253 |
|
|
extern void SysCtlClockSet(unsigned long ulConfig);
|
254 |
|
|
extern unsigned long SysCtlClockGet(void);
|
255 |
|
|
extern void SysCtlPWMClockSet(unsigned long ulConfig);
|
256 |
|
|
extern unsigned long SysCtlPWMClockGet(void);
|
257 |
|
|
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
|
258 |
|
|
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
|
259 |
|
|
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
|
260 |
|
|
extern void SysCtlClkVerificationClear(void);
|
261 |
|
|
|
262 |
|
|
#ifdef __cplusplus
|
263 |
|
|
}
|
264 |
|
|
#endif
|
265 |
|
|
|
266 |
|
|
#endif // __SYSCTL_H__
|