OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S316_IAR/] [registertest.s] - Blame information for rev 615

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 581 jeremybenn 
        RSEG ICODE:CODE
2 
 
3 
        EXTERN vSetErrorLED
4 
 
5 
        PUBLIC vSetAndCheckRegisters
6 
 
7 
vSetAndCheckRegisters:
8 
        /* Fill the general purpose registers with known values. */
9 
        mov r11, #10
10 
        add r0, r11, #1
11 
        add r1, r11, #2
12 
        add r2, r11, #3
13 
        add r3, r11, #4
14 
        add r4, r11, #5
15 
        add r5, r11, #6
16 
        add r6, r11, #7
17 
        add r7, r11, #8
18 
        add r8, r11, #9
19 
        add r9, r11, #10
20 
        add r10, r11, #11
21 
        add r12, r11, #12
22 
 
23 
        /* Check the values are as expected. */
24 
        cmp r11, #10
25 
        bne set_error_led
26 
        cmp r0, #11
27 
        bne set_error_led
28 
        cmp r1, #12
29 
        bne set_error_led
30 
        cmp r2, #13
31 
        bne set_error_led
32 
        cmp r3, #14
33 
        bne set_error_led
34 
        cmp r4, #15
35 
        bne set_error_led
36 
        cmp r5, #16
37 
        bne set_error_led
38 
        cmp r6, #17
39 
        bne set_error_led
40 
        cmp r7, #18
41 
        bne set_error_led
42 
        cmp r8, #19
43 
        bne set_error_led
44 
        cmp r9, #20
45 
        bne set_error_led
46 
        cmp r10, #21
47 
        bne set_error_led
48 
        cmp r12, #22
49 
        bne set_error_led
50 
        bx lr
51 
 
52 
set_error_led:
53 
        push {r14}
54 
        ldr r1, =vSetErrorLED
55 
        blx r1
56 
        pop {r14}
57 
        bx lr
58 
 
59 
        END
60 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.