OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_GCC/] [hw_include/] [hw_ints.h] - Blame information for rev 581

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 581 jeremybenn
//*****************************************************************************
2
//
3
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
4
//
5
// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
6
//
7
// Software License Agreement
8
//
9
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10
// exclusively on LMI's Stellaris Family of microcontroller products.
11
//
12
// The software is owned by LMI and/or its suppliers, and is protected under
13
// applicable copyright laws.  All rights are reserved.  Any use in violation
14
// of the foregoing restrictions may subject the user to criminal sanctions
15
// under applicable laws, as well as to civil liability for the breach of the
16
// terms and conditions of this license.
17
//
18
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
22
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23
//
24
// This is part of revision 991 of the Stellaris Driver Library.
25
//
26
//*****************************************************************************
27
 
28
#ifndef __HW_INTS_H__
29
#define __HW_INTS_H__
30
 
31
//*****************************************************************************
32
//
33
// The following define the fault assignments.
34
//
35
//*****************************************************************************
36
#define FAULT_NMI               2           // NMI fault
37
#define FAULT_HARD              3           // Hard fault
38
#define FAULT_MPU               4           // MPU fault
39
#define FAULT_BUS               5           // Bus fault
40
#define FAULT_USAGE             6           // Usage fault
41
#define FAULT_SVCALL            11          // SVCall
42
#define FAULT_DEBUG             12          // Debug monitor
43
#define FAULT_PENDSV            14          // PendSV
44
#define FAULT_SYSTICK           15          // System Tick
45
 
46
//*****************************************************************************
47
//
48
// The following define the interrupt assignments.
49
//
50
//*****************************************************************************
51
#define INT_GPIOA               16          // GPIO Port A
52
#define INT_GPIOB               17          // GPIO Port B
53
#define INT_GPIOC               18          // GPIO Port C
54
#define INT_GPIOD               19          // GPIO Port D
55
#define INT_GPIOE               20          // GPIO Port E
56
#define INT_UART0               21          // UART0 Rx and Tx
57
#define INT_UART1               22          // UART1 Rx and Tx
58
#define INT_SSI                 23          // SSI Rx and Tx
59
#define INT_I2C                 24          // I2C Master and Slave
60
#define INT_PWM_FAULT           25          // PWM Fault
61
#define INT_PWM0                26          // PWM Generator 0
62
#define INT_PWM1                27          // PWM Generator 1
63
#define INT_PWM2                28          // PWM Generator 2
64
#define INT_QEI                 29          // Quadrature Encoder
65
#define INT_ADC0                30          // ADC Sequence 0
66
#define INT_ADC1                31          // ADC Sequence 1
67
#define INT_ADC2                32          // ADC Sequence 2
68
#define INT_ADC3                33          // ADC Sequence 3
69
#define INT_WATCHDOG            34          // Watchdog timer
70
#define INT_TIMER0A             35          // Timer 0 subtimer A
71
#define INT_TIMER0B             36          // Timer 0 subtimer B
72
#define INT_TIMER1A             37          // Timer 1 subtimer A
73
#define INT_TIMER1B             38          // Timer 1 subtimer B
74
#define INT_TIMER2A             39          // Timer 2 subtimer A
75
#define INT_TIMER2B             40          // Timer 2 subtimer B
76
#define INT_COMP0               41          // Analog Comparator 0
77
#define INT_COMP1               42          // Analog Comparator 1
78
#define INT_COMP2               43          // Analog Comparator 2
79
#define INT_SYSCTL              44          // System Control (PLL, OSC, BO)
80
#define INT_FLASH               45          // FLASH Control
81
 
82
//*****************************************************************************
83
//
84
// The total number of interrupts.
85
//
86
//*****************************************************************************
87
#define NUM_INTERRUPTS          46
88
 
89
//*****************************************************************************
90
//
91
// The total number of priority levels.
92
//
93
//*****************************************************************************
94
#define NUM_PRIORITY            8
95
#define NUM_PRIORITY_BITS       3
96
 
97
#endif // __HW_INTS_H__

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.