OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_GCC/] [init/] [startup.c] - Blame information for rev 655

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 581 jeremybenn
//*****************************************************************************
2
//
3
// startup.c - Boot code for Stellaris.
4
//
5
// Copyright (c) 2005-2007 Luminary Micro, Inc.  All rights reserved.
6
//
7
// Software License Agreement
8
//
9
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10
// exclusively on LMI's microcontroller products.
11
//
12
// The software is owned by LMI and/or its suppliers, and is protected under
13
// applicable copyright laws.  All rights are reserved.  Any use in violation
14
// of the foregoing restrictions may subject the user to criminal sanctions
15
// under applicable laws, as well as to civil liability for the breach of the
16
// terms and conditions of this license.
17
//
18
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
22
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23
//
24
// This is part of revision 1049 of the Stellaris Driver Library.
25
//
26
//*****************************************************************************
27
 
28
//*****************************************************************************
29
//
30
// Forward declaration of the default fault handlers.
31
//
32
//*****************************************************************************
33
void ResetISR(void);
34
static void NmiSR(void);
35
static void FaultISR(void);
36
static void IntDefaultHandler(void);
37
extern void xPortPendSVHandler(void);
38
extern void xPortSysTickHandler(void);
39
extern void vUART_ISR( void );
40
extern void vGPIO_ISR( void );
41
extern void vPortSVCHandler( void );
42
 
43
//*****************************************************************************
44
//
45
// The entry point for the application.
46
//
47
//*****************************************************************************
48
extern int main(void);
49
 
50
//*****************************************************************************
51
//
52
// Reserve space for the system stack.
53
//
54
//*****************************************************************************
55
#ifndef STACK_SIZE
56
#define STACK_SIZE                              64
57
#endif
58
static unsigned long pulStack[STACK_SIZE];
59
 
60
//*****************************************************************************
61
//
62
// The minimal vector table for a Cortex M3.  Note that the proper constructs
63
// must be placed on this to ensure that it ends up at physical address
64
// 0x0000.0000.
65
//
66
//*****************************************************************************
67
__attribute__ ((section(".isr_vector")))
68
void (* const g_pfnVectors[])(void) =
69
{
70
    (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
71
                                            // The initial stack pointer
72
    ResetISR,                               // The reset handler
73
    NmiSR,                                  // The NMI handler
74
    FaultISR,                               // The hard fault handler
75
    IntDefaultHandler,                      // The MPU fault handler
76
    IntDefaultHandler,                      // The bus fault handler
77
    IntDefaultHandler,                      // The usage fault handler
78
    0,                                      // Reserved
79
    0,                                      // Reserved
80
    0,                                      // Reserved
81
    0,                                      // Reserved
82
    vPortSVCHandler,                        // SVCall handler
83
    IntDefaultHandler,                      // Debug monitor handler
84
    0,                                      // Reserved
85
    xPortPendSVHandler,                     // The PendSV handler
86
    xPortSysTickHandler,                    // The SysTick handler
87
    IntDefaultHandler,                      // GPIO Port A
88
    IntDefaultHandler,                      // GPIO Port B
89
    vGPIO_ISR,                                                          // GPIO Port C
90
    IntDefaultHandler,                      // GPIO Port D
91
    IntDefaultHandler,                      // GPIO Port E
92
    vUART_ISR,                                                          // UART0 Rx and Tx
93
    IntDefaultHandler,                      // UART1 Rx and Tx
94
    IntDefaultHandler,                      // SSI Rx and Tx
95
    IntDefaultHandler,                      // I2C Master and Slave
96
    IntDefaultHandler,                      // PWM Fault
97
    IntDefaultHandler,                      // PWM Generator 0
98
    IntDefaultHandler,                      // PWM Generator 1
99
    IntDefaultHandler,                      // PWM Generator 2
100
    IntDefaultHandler,                      // Quadrature Encoder
101
    IntDefaultHandler,                      // ADC Sequence 0
102
    IntDefaultHandler,                      // ADC Sequence 1
103
    IntDefaultHandler,                      // ADC Sequence 2
104
    IntDefaultHandler,                      // ADC Sequence 3
105
    IntDefaultHandler,                      // Watchdog timer
106
    IntDefaultHandler,                      // Timer 0 subtimer A
107
    IntDefaultHandler,                      // Timer 0 subtimer B
108
    IntDefaultHandler,                      // Timer 1 subtimer A
109
    IntDefaultHandler,                      // Timer 1 subtimer B
110
    IntDefaultHandler,                      // Timer 2 subtimer A
111
    IntDefaultHandler,                      // Timer 2 subtimer B
112
    IntDefaultHandler,                      // Analog Comparator 0
113
    IntDefaultHandler,                      // Analog Comparator 1
114
    IntDefaultHandler,                      // Analog Comparator 2
115
    IntDefaultHandler,                      // System Control (PLL, OSC, BO)
116
    IntDefaultHandler                       // FLASH Control
117
};
118
 
119
//*****************************************************************************
120
//
121
// The following are constructs created by the linker, indicating where the
122
// the "data" and "bss" segments reside in memory.  The initializers for the
123
// for the "data" segment resides immediately following the "text" segment.
124
//
125
//*****************************************************************************
126
extern unsigned long _etext;
127
extern unsigned long _data;
128
extern unsigned long _edata;
129
extern unsigned long _bss;
130
extern unsigned long _ebss;
131
 
132
//*****************************************************************************
133
//
134
// This is the code that gets called when the processor first starts execution
135
// following a reset event.  Only the absolutely necessary set is performed,
136
// after which the application supplied main() routine is called.  Any fancy
137
// actions (such as making decisions based on the reset cause register, and
138
// resetting the bits in that register) are left solely in the hands of the
139
// application.
140
//
141
//*****************************************************************************
142
void
143
ResetISR(void)
144
{
145
    unsigned long *pulSrc, *pulDest;
146
 
147
    //
148
    // Copy the data segment initializers from flash to SRAM.
149
    //
150
    pulSrc = &_etext;
151
    for(pulDest = &_data; pulDest < &_edata; )
152
    {
153
        *pulDest++ = *pulSrc++;
154
    }
155
 
156
    //
157
    // Zero fill the bss segment.
158
    //
159
    for(pulDest = &_bss; pulDest < &_ebss; )
160
    {
161
        *pulDest++ = 0;
162
    }
163
 
164
    //
165
    // Call the application's entry point.
166
    //
167
    main();
168
}
169
 
170
//*****************************************************************************
171
//
172
// This is the code that gets called when the processor receives a NMI.  This
173
// simply enters an infinite loop, preserving the system state for examination
174
// by a debugger.
175
//
176
//*****************************************************************************
177
static void
178
NmiSR(void)
179
{
180
    //
181
    // Enter an infinite loop.
182
    //
183
    while(1)
184
    {
185
    }
186
}
187
 
188
//*****************************************************************************
189
//
190
// This is the code that gets called when the processor receives a fault
191
// interrupt.  This simply enters an infinite loop, preserving the system state
192
// for examination by a debugger.
193
//
194
//*****************************************************************************
195
static void
196
FaultISR(void)
197
{
198
    //
199
    // Enter an infinite loop.
200
    //
201
    while(1)
202
    {
203
    }
204
}
205
 
206
//*****************************************************************************
207
//
208
// This is the code that gets called when the processor receives an unexpected
209
// interrupt.  This simply enters an infinite loop, preserving the system state
210
// for examination by a debugger.
211
//
212
//*****************************************************************************
213
static void
214
IntDefaultHandler(void)
215
{
216
    //
217
    // Go into an infinite loop.
218
    //
219
    while(1)
220
    {
221
    }
222
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.