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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_IAR/] [LuminaryCode/] [hw_comp.h] - Blame information for rev 581

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1 581 jeremybenn
//*****************************************************************************
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//
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// hw_comp.h - Macros used when accessing the comparator hardware.
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//
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// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's Stellaris Family of microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws.  All rights are reserved.  Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 991 of the Stellaris Driver Library.
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//
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//*****************************************************************************
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#ifndef __HW_COMP_H__
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#define __HW_COMP_H__
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//*****************************************************************************
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//
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// The following define the offsets of the comparator registers.
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//
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//*****************************************************************************
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#define COMP_O_MIS              0x00000000  // Interrupt status register
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#define COMP_O_RIS              0x00000004  // Raw interrupt status register
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#define COMP_O_INTEN            0x00000008  // Interrupt enable register
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#define COMP_O_REFCTL           0x00000010  // Reference voltage control reg.
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#define COMP_O_ACSTAT0          0x00000020  // Comp0 status register
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#define COMP_O_ACCTL0           0x00000024  // Comp0 control register
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#define COMP_O_ACSTAT1          0x00000040  // Comp1 status register
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#define COMP_O_ACCTL1           0x00000044  // Comp1 control register
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#define COMP_O_ACSTAT2          0x00000060  // Comp2 status register
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#define COMP_O_ACCTL2           0x00000064  // Comp2 control register
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//*****************************************************************************
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//
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// The following define the bit fields in the COMP_MIS, COMP_RIS, and
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// COMP_INTEN registers.
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//
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//*****************************************************************************
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#define COMP_INT_2              0x00000004  // Comp2 interrupt
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#define COMP_INT_1              0x00000002  // Comp1 interrupt
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#define COMP_INT_0              0x00000001  // Comp0 interrupt
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//*****************************************************************************
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//
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// The following define the bit fields in the COMP_REFCTL register.
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//
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//*****************************************************************************
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#define COMP_REFCTL_EN          0x00000200  // Reference voltage enable
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#define COMP_REFCTL_RNG         0x00000100  // Reference voltage range
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#define COMP_REFCTL_VREF_MASK   0x0000000F  // Reference voltage select mask
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#define COMP_REFCTL_VREF_SHIFT  0
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//*****************************************************************************
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//
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// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and
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// COMP_ACSTAT2 registers.
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//
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//*****************************************************************************
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#define COMP_ACSTAT_OVAL        0x00000002  // Comparator output value
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//*****************************************************************************
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//
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// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and
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// COMP_ACCTL2 registers.
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//
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//*****************************************************************************
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#define COMP_ACCTL_TMASK        0x00000800  // Trigger enable
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#define COMP_ACCTL_ASRCP_MASK   0x00000600  // Vin+ source select mask
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#define COMP_ACCTL_ASRCP_PIN    0x00000000  // Dedicated Comp+ pin
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#define COMP_ACCTL_ASRCP_PIN0   0x00000200  // Comp0+ pin
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#define COMP_ACCTL_ASRCP_REF    0x00000400  // Internal voltage reference
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#define COMP_ACCTL_ASRCP_RES    0x00000600  // Reserved
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#define COMP_ACCTL_OEN          0x00000100  // Comparator output enable
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#define COMP_ACCTL_TSVAL        0x00000080  // Trigger polarity select
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#define COMP_ACCTL_TSEN_MASK    0x00000060  // Trigger sense mask
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#define COMP_ACCTL_TSEN_LEVEL   0x00000000  // Trigger is level sense
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#define COMP_ACCTL_TSEN_FALL    0x00000020  // Trigger is falling edge
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#define COMP_ACCTL_TSEN_RISE    0x00000040  // Trigger is rising edge
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#define COMP_ACCTL_TSEN_BOTH    0x00000060  // Trigger is both edges
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#define COMP_ACCTL_ISLVAL       0x00000010  // Interrupt polarity select
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#define COMP_ACCTL_ISEN_MASK    0x0000000C  // Interrupt sense mask
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#define COMP_ACCTL_ISEN_LEVEL   0x00000000  // Interrupt is level sense
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#define COMP_ACCTL_ISEN_FALL    0x00000004  // Interrupt is falling edge
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#define COMP_ACCTL_ISEN_RISE    0x00000008  // Interrupt is rising edge
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#define COMP_ACCTL_ISEN_BOTH    0x0000000C  // Interrupt is both edges
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#define COMP_ACCTL_CINV         0x00000002  // Comparator output invert
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//*****************************************************************************
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//
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// The following define the reset values for the comparator registers.
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//
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//*****************************************************************************
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#define COMP_RV_MIS             0x00000000  // Interrupt status register
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#define COMP_RV_RIS             0x00000000  // Raw interrupt status register
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#define COMP_RV_INTEN           0x00000000  // Interrupt enable register
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#define COMP_RV_REFCTL          0x00000000  // Reference voltage control reg.
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#define COMP_RV_ACSTAT0         0x00000000  // Comp0 status register
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#define COMP_RV_ACCTL0          0x00000000  // Comp0 control register
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#define COMP_RV_ACSTAT1         0x00000000  // Comp1 status register
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#define COMP_RV_ACCTL1          0x00000000  // Comp1 control register
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#define COMP_RV_ACSTAT2         0x00000000  // Comp2 status register
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#define COMP_RV_ACCTL2          0x00000000  // Comp2 control register
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#endif // __HW_COMP_H__

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