| 1 |
581 |
jeremybenn |
//*****************************************************************************
|
| 2 |
|
|
//
|
| 3 |
|
|
// hw_memmap.h - Macros defining the memory map of Stellaris.
|
| 4 |
|
|
//
|
| 5 |
|
|
// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
|
| 6 |
|
|
//
|
| 7 |
|
|
// Software License Agreement
|
| 8 |
|
|
//
|
| 9 |
|
|
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
|
| 10 |
|
|
// exclusively on LMI's Stellaris Family of microcontroller products.
|
| 11 |
|
|
//
|
| 12 |
|
|
// The software is owned by LMI and/or its suppliers, and is protected under
|
| 13 |
|
|
// applicable copyright laws. All rights are reserved. Any use in violation
|
| 14 |
|
|
// of the foregoing restrictions may subject the user to criminal sanctions
|
| 15 |
|
|
// under applicable laws, as well as to civil liability for the breach of the
|
| 16 |
|
|
// terms and conditions of this license.
|
| 17 |
|
|
//
|
| 18 |
|
|
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
| 19 |
|
|
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
| 20 |
|
|
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
| 21 |
|
|
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
| 22 |
|
|
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
| 23 |
|
|
//
|
| 24 |
|
|
// This is part of revision 991 of the Stellaris Driver Library.
|
| 25 |
|
|
//
|
| 26 |
|
|
//*****************************************************************************
|
| 27 |
|
|
|
| 28 |
|
|
#ifndef __HW_MEMMAP_H__
|
| 29 |
|
|
#define __HW_MEMMAP_H__
|
| 30 |
|
|
|
| 31 |
|
|
//*****************************************************************************
|
| 32 |
|
|
//
|
| 33 |
|
|
// The following define the base address of the memories and peripherals.
|
| 34 |
|
|
//
|
| 35 |
|
|
//*****************************************************************************
|
| 36 |
|
|
#define FLASH_BASE 0x00000000 // FLASH memory
|
| 37 |
|
|
#define SRAM_BASE 0x20000000 // SRAM memory
|
| 38 |
|
|
#define WATCHDOG_BASE 0x40000000 // Watchdog
|
| 39 |
|
|
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
|
| 40 |
|
|
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
|
| 41 |
|
|
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
|
| 42 |
|
|
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
|
| 43 |
|
|
#define SSI_BASE 0x40008000 // SSI
|
| 44 |
|
|
#define UART0_BASE 0x4000C000 // UART0
|
| 45 |
|
|
#define UART1_BASE 0x4000D000 // UART1
|
| 46 |
|
|
#define I2C_MASTER_BASE 0x40020000 // I2C Master
|
| 47 |
|
|
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
|
| 48 |
|
|
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
|
| 49 |
|
|
#define PWM_BASE 0x40028000 // PWM
|
| 50 |
|
|
#define QEI_BASE 0x4002C000 // QEI
|
| 51 |
|
|
#define TIMER0_BASE 0x40030000 // Timer0
|
| 52 |
|
|
#define TIMER1_BASE 0x40031000 // Timer1
|
| 53 |
|
|
#define TIMER2_BASE 0x40032000 // Timer2
|
| 54 |
|
|
#define ADC_BASE 0x40038000 // ADC
|
| 55 |
|
|
#define COMP_BASE 0x4003C000 // Analog comparators
|
| 56 |
|
|
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
|
| 57 |
|
|
#define SYSCTL_BASE 0x400FE000 // System Control
|
| 58 |
|
|
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
|
| 59 |
|
|
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
|
| 60 |
|
|
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
|
| 61 |
|
|
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
|
| 62 |
|
|
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
|
| 63 |
|
|
|
| 64 |
|
|
#endif // __HW_MEMMAP_H__
|
