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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_IAR/] [LuminaryCode/] [hw_ssi.h] - Blame information for rev 581

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1 581 jeremybenn
//*****************************************************************************
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//
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// hw_ssi.h - Macros used when accessing the SSI hardware.
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//
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// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's Stellaris Family of microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws.  All rights are reserved.  Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 991 of the Stellaris Driver Library.
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//
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//*****************************************************************************
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#ifndef __HW_SSI_H__
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#define __HW_SSI_H__
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//*****************************************************************************
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//
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// The following define the offsets of the SSI registers.
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//
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//*****************************************************************************
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#define SSI_O_CR0               0x00000000  // Control register 0
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#define SSI_O_CR1               0x00000004  // Control register 1
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#define SSI_O_DR                0x00000008  // Data register
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#define SSI_O_SR                0x0000000C  // Status register
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#define SSI_O_CPSR              0x00000010  // Clock prescale register
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#define SSI_O_IM                0x00000014  // Int mask set and clear register
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#define SSI_O_RIS               0x00000018  // Raw interrupt register
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#define SSI_O_MIS               0x0000001C  // Masked interrupt register
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#define SSI_O_ICR               0x00000020  // Interrupt clear register
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//*****************************************************************************
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//
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// The following define the bit fields in the SSI Control register 0.
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//
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//*****************************************************************************
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#define SSI_CR0_SCR             0x0000FF00  // Serial clock rate
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#define SSI_CR0_SPH             0x00000080  // SSPCLKOUT phase
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#define SSI_CR0_SPO             0x00000040  // SSPCLKOUT polarity
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#define SSI_CR0_FRF_MASK        0x00000030  // Frame format mask
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#define SSI_CR0_FRF_MOTO        0x00000000  // Motorola SPI frame format
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#define SSI_CR0_FRF_TI          0x00000010  // TI sync serial frame format
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#define SSI_CR0_FRF_NMW         0x00000020  // National Microwire frame format
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#define SSI_CR0_DSS             0x0000000F  // Data size select
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#define SSI_CR0_DSS_4           0x00000003  // 4 bit data
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#define SSI_CR0_DSS_5           0x00000004  // 5 bit data
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#define SSI_CR0_DSS_6           0x00000005  // 6 bit data
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#define SSI_CR0_DSS_7           0x00000006  // 7 bit data
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#define SSI_CR0_DSS_8           0x00000007  // 8 bit data
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#define SSI_CR0_DSS_9           0x00000008  // 9 bit data
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#define SSI_CR0_DSS_10          0x00000009  // 10 bit data
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#define SSI_CR0_DSS_11          0x0000000A  // 11 bit data
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#define SSI_CR0_DSS_12          0x0000000B  // 12 bit data
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#define SSI_CR0_DSS_13          0x0000000C  // 13 bit data
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#define SSI_CR0_DSS_14          0x0000000D  // 14 bit data
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#define SSI_CR0_DSS_15          0x0000000E  // 15 bit data
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#define SSI_CR0_DSS_16          0x0000000F  // 16 bit data
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//*****************************************************************************
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//
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// The following define the bit fields in the SSI Control register 1.
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//
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//*****************************************************************************
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#define SSI_CR1_SOD             0x00000008  // Slave mode output disable
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#define SSI_CR1_MS              0x00000004  // Master or slave mode select
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#define SSI_CR1_SSE             0x00000002  // Sync serial port enable
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#define SSI_CR1_LBM             0x00000001  // Loopback mode
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//*****************************************************************************
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//
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// The following define the bit fields in the SSI Status register.
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//
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//*****************************************************************************
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#define SSI_SR_BSY              0x00000010  // SSI busy
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#define SSI_SR_RFF              0x00000008  // RX FIFO full
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#define SSI_SR_RNE              0x00000004  // RX FIFO not empty
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#define SSI_SR_TNF              0x00000002  // TX FIFO not full
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#define SSI_SR_TFE              0x00000001  // TX FIFO empty
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//*****************************************************************************
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//
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// The following define the bit fields in the SSI clock prescale register.
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//
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//*****************************************************************************
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#define SSI_CPSR_CPSDVSR_MASK   0x000000FF  // Clock prescale
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//*****************************************************************************
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//
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// The following define information concerning the SSI Data register.
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//
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//*****************************************************************************
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#define TX_FIFO_SIZE            (8)         // Number of entries in the TX FIFO
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#define RX_FIFO_SIZE            (8)         // Number of entries in the RX FIFO
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//*****************************************************************************
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//
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// The following define the bit fields in the interrupt mask set and clear,
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// raw interrupt, masked interrupt, and interrupt clear registers.
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//
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//*****************************************************************************
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#define SSI_INT_TXFF            0x00000008  // TX FIFO interrupt
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#define SSI_INT_RXFF            0x00000004  // RX FIFO interrupt
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#define SSI_INT_RXTO            0x00000002  // RX timeout interrupt
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#define SSI_INT_RXOR            0x00000001  // RX overrun interrupt
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#endif // __HW_SSI_H__

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