OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_IAR/] [LuminaryCode/] [hw_sysctl.h] - Blame information for rev 613

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 581 jeremybenn 
//*****************************************************************************
2 
//
3 
// hw_sysctl.h - Macros used when accessing the system control hardware.
4 
//
5 
// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
6 
//
7 
// Software License Agreement
8 
//
9 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10 
// exclusively on LMI's Stellaris Family of microcontroller products.
11 
//
12 
// The software is owned by LMI and/or its suppliers, and is protected under
13 
// applicable copyright laws.  All rights are reserved.  Any use in violation
14 
// of the foregoing restrictions may subject the user to criminal sanctions
15 
// under applicable laws, as well as to civil liability for the breach of the
16 
// terms and conditions of this license.
17 
//
18 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19 
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20 
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21 
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
22 
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23 
//
24 
// This is part of revision 991 of the Stellaris Driver Library.
25 
//
26 
//*****************************************************************************
27 
 
28 
#ifndef __HW_SYSCTL_H__
29 
#define __HW_SYSCTL_H__
30 
 
31 
//*****************************************************************************
32 
//
33 
// The following define the offsets of the system control registers.
34 
//
35 
//*****************************************************************************
36 
#define SYSCTL_DID0             0x400fe000  // Device identification register 0
37 
#define SYSCTL_DID1             0x400fe004  // Device identification register 1
38 
#define SYSCTL_DC0              0x400fe008  // Device capabilities register 0
39 
#define SYSCTL_DC1              0x400fe010  // Device capabilities register 1
40 
#define SYSCTL_DC2              0x400fe014  // Device capabilities register 2
41 
#define SYSCTL_DC3              0x400fe018  // Device capabilities register 3
42 
#define SYSCTL_DC4              0x400fe01C  // Device capabilities register 4
43 
#define SYSCTL_PBORCTL          0x400fe030  // POR/BOR reset control register
44 
#define SYSCTL_LDOPCTL          0x400fe034  // LDO power control register
45 
#define SYSCTL_SRCR0            0x400fe040  // Software reset control reg 0
46 
#define SYSCTL_SRCR1            0x400fe044  // Software reset control reg 1
47 
#define SYSCTL_SRCR2            0x400fe048  // Software reset control reg 2
48 
#define SYSCTL_RIS              0x400fe050  // Raw interrupt status register
49 
#define SYSCTL_IMC              0x400fe054  // Interrupt mask/control register
50 
#define SYSCTL_MISC             0x400fe058  // Interrupt status register
51 
#define SYSCTL_RESC             0x400fe05c  // Reset cause register
52 
#define SYSCTL_RCC              0x400fe060  // Run-mode clock config register
53 
#define SYSCTL_PLLCFG           0x400fe064  // PLL configuration register
54 
#define SYSCTL_RCGC0            0x400fe100  // Run-mode clock gating register 0
55 
#define SYSCTL_RCGC1            0x400fe104  // Run-mode clock gating register 1
56 
#define SYSCTL_RCGC2            0x400fe108  // Run-mode clock gating register 2
57 
#define SYSCTL_SCGC0            0x400fe110  // Sleep-mode clock gating reg 0
58 
#define SYSCTL_SCGC1            0x400fe114  // Sleep-mode clock gating reg 1
59 
#define SYSCTL_SCGC2            0x400fe118  // Sleep-mode clock gating reg 2
60 
#define SYSCTL_DCGC0            0x400fe120  // Deep Sleep-mode clock gate reg 0
61 
#define SYSCTL_DCGC1            0x400fe124  // Deep Sleep-mode clock gate reg 1
62 
#define SYSCTL_DCGC2            0x400fe128  // Deep Sleep-mode clock gate reg 2
63 
#define SYSCTL_CLKVCLR          0x400fe150  // Clock verifcation clear register
64 
#define SYSCTL_LDOARST          0x400fe160  // LDO reset control register
65 
 
66 
//*****************************************************************************
67 
//
68 
// The following define the bit fields in the SYSCTL_DID0 register.
69 
//
70 
//*****************************************************************************
71 
#define SYSCTL_DID0_VER_MASK    0x70000000  // DID0 version mask
72 
#define SYSCTL_DID0_VER_0       0x00000000  // DID0 version 0
73 
#define SYSCTL_DID0_MAJ_MASK    0x0000FF00  // Major revision mask
74 
#define SYSCTL_DID0_MAJ_A       0x00000000  // Major revision A
75 
#define SYSCTL_DID0_MAJ_B       0x00000100  // Major revision B
76 
#define SYSCTL_DID0_MIN_MASK    0x000000FF  // Minor revision mask
77 
#define SYSCTL_DID0_MIN_0       0x00000000  // Minor revision 0
78 
#define SYSCTL_DID0_MIN_1       0x00000001  // Minor revision 1
79 
 
80 
//*****************************************************************************
81 
//
82 
// The following define the bit fields in the SYSCTL_DID1 register.
83 
//
84 
//*****************************************************************************
85 
#define SYSCTL_DID1_VER_MASK    0xF0000000  // Register version mask
86 
#define SYSCTL_DID1_FAM_MASK    0x0F000000  // Family mask
87 
#define SYSCTL_DID1_FAM_S       0x00000000  // Stellaris family
88 
#define SYSCTL_DID1_PRTNO_MASK  0x00FF0000  // Part number mask
89 
#define SYSCTL_DID1_PRTNO_101   0x00010000  // LM3S101
90 
#define SYSCTL_DID1_PRTNO_102   0x00020000  // LM3S102
91 
#define SYSCTL_DID1_PRTNO_301   0x00110000  // LM3S301
92 
#define SYSCTL_DID1_PRTNO_310   0x00120000  // LM3S310
93 
#define SYSCTL_DID1_PRTNO_315   0x00130000  // LM3S315
94 
#define SYSCTL_DID1_PRTNO_316   0x00140000  // LM3S316
95 
#define SYSCTL_DID1_PRTNO_328   0x00150000  // LM3S328
96 
#define SYSCTL_DID1_PRTNO_601   0x00210000  // LM3S601
97 
#define SYSCTL_DID1_PRTNO_610   0x00220000  // LM3S610
98 
#define SYSCTL_DID1_PRTNO_611   0x00230000  // LM3S611
99 
#define SYSCTL_DID1_PRTNO_612   0x00240000  // LM3S612
100 
#define SYSCTL_DID1_PRTNO_613   0x00250000  // LM3S613
101 
#define SYSCTL_DID1_PRTNO_615   0x00260000  // LM3S615
102 
#define SYSCTL_DID1_PRTNO_628   0x00270000  // LM3S628
103 
#define SYSCTL_DID1_PRTNO_801   0x00310000  // LM3S801
104 
#define SYSCTL_DID1_PRTNO_811   0x00320000  // LM3S811
105 
#define SYSCTL_DID1_PRTNO_812   0x00330000  // LM3S812
106 
#define SYSCTL_DID1_PRTNO_815   0x00340000  // LM3S815
107 
#define SYSCTL_DID1_PRTNO_828   0x00350000  // LM3S828
108 
#define SYSCTL_DID1_TEMP_MASK   0x000000E0  // Temperature range mask
109 
#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temp range (0..70C)
110 
#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temp range (-40..85C)
111 
#define SYSCTL_DID1_PKG_MASK    0x00000018  // Package mask
112 
#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // 28-pin SOIC
113 
#define SYSCTL_DID1_PKG_48QFP   0x00000008  // 48-pin QFP
114 
#define SYSCTL_DID1_ROHS        0x00000004  // Part is RoHS compliant
115 
#define SYSCTL_DID1_QUAL_MASK   0x00000003  // Qualification status mask
116 
#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering sample (unqualified)
117 
#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot production (unqualified)
118 
#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully qualified
119 
#define SYSCTL_DID1_PRTNO_SHIFT 16
120 
 
121 
//*****************************************************************************
122 
//
123 
// The following define the bit fields in the SYSCTL_DC0 register.
124 
//
125 
//*****************************************************************************
126 
#define SYSCTL_DC0_SRAMSZ_MASK  0xFFFF0000  // SRAM size mask
127 
#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2kB of SRAM
128 
#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4kB of SRAM
129 
#define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000  // 8kB of SRAM
130 
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF  // Flash size mask
131 
#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8kB of flash
132 
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16kB of flash
133 
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F  // 32kB of flash
134 
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F  // 64kB of flash
135 
 
136 
//*****************************************************************************
137 
//
138 
// The following define the bit fields in the SYSCTL_DC1 register.
139 
//
140 
//*****************************************************************************
141 
#define SYSCTL_DC1_PWM          0x00100000  // PWM module present
142 
#define SYSCTL_DC1_ADC          0x00010000  // ADC module present
143 
#define SYSCTL_DC1_SYSDIV_MASK  0x0000F000  // Minimum system divider mask
144 
#define SYSCTL_DC1_ADCSPD_MASK  0x00000F00  // ADC speed mask
145 
#define SYSCTL_DC1_ADCSPD_1M    0x00000300  // 1Msps ADC
146 
#define SYSCTL_DC1_ADCSPD_500K  0x00000200  // 500Ksps ADC
147 
#define SYSCTL_DC1_ADCSPD_250K  0x00000100  // 250Ksps ADC
148 
#define SYSCTL_DC1_ADCSPD_125K  0x00000000  // 125Ksps ADC
149 
#define SYSCTL_DC1_MPU          0x00000080  // Cortex M3 MPU present
150 
#define SYSCTL_DC1_TEMP         0x00000020  // Temperature sensor present
151 
#define SYSCTL_DC1_PLL          0x00000010  // PLL present
152 
#define SYSCTL_DC1_WDOG         0x00000008  // Watchdog present
153 
#define SYSCTL_DC1_SWO          0x00000004  // Serial wire output present
154 
#define SYSCTL_DC1_SWD          0x00000002  // Serial wire debug present
155 
#define SYSCTL_DC1_JTAG         0x00000001  // JTAG debug present
156 
 
157 
//*****************************************************************************
158 
//
159 
// The following define the bit fields in the SYSCTL_DC2 register.
160 
//
161 
//*****************************************************************************
162 
#define SYSCTL_DC2_COMP2        0x04000000  // Analog comparator 2 present
163 
#define SYSCTL_DC2_COMP1        0x02000000  // Analog comparator 1 present
164 
#define SYSCTL_DC2_COMP0        0x01000000  // Analog comparator 0 present
165 
#define SYSCTL_DC2_TIMER2       0x00040000  // Timer 2 present
166 
#define SYSCTL_DC2_TIMER1       0x00020000  // Timer 1 present
167 
#define SYSCTL_DC2_TIMER0       0x00010000  // Timer 0 present
168 
#define SYSCTL_DC2_I2C          0x00001000  // I2C present
169 
#define SYSCTL_DC2_QEI          0x00000100  // QEI present
170 
#define SYSCTL_DC2_SSI          0x00000010  // SSI present
171 
#define SYSCTL_DC2_UART1        0x00000002  // UART 1 present
172 
#define SYSCTL_DC2_UART0        0x00000001  // UART 0 present
173 
 
174 
//*****************************************************************************
175 
//
176 
// The following define the bit fields in the SYSCTL_DC3 register.
177 
//
178 
//*****************************************************************************
179 
#define SYSCTL_DC3_32KHZ        0x80000000  // 32kHz pin present
180 
#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 pin present
181 
#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 pin present
182 
#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 pin present
183 
#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 pin present
184 
#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 pin present
185 
#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 pin present
186 
#define SYSCTL_DC3_ADC7         0x00800000  // ADC7 pin present
187 
#define SYSCTL_DC3_ADC6         0x00400000  // ADC6 pin present
188 
#define SYSCTL_DC3_ADC5         0x00200000  // ADC5 pin present
189 
#define SYSCTL_DC3_ADC4         0x00100000  // ADC4 pin present
190 
#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 pin present
191 
#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 pin present
192 
#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 pin present
193 
#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 pin present
194 
#define SYSCTL_DC3_C2O          0x00004000  // C2o pin present
195 
#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ pin present
196 
#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- pin present
197 
#define SYSCTL_DC3_C1O          0x00000800  // C1o pin present
198 
#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ pin present
199 
#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- pin present
200 
#define SYSCTL_DC3_C0O          0x00000100  // C0o pin present
201 
#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ pin present
202 
#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- pin present
203 
#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 pin present
204 
#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 pin present
205 
#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 pin present
206 
#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 pin present
207 
#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 pin present
208 
#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 pin present
209 
 
210 
//*****************************************************************************
211 
//
212 
// The following define the bit fields in the SYSCTL_DC4 register.
213 
//
214 
//*****************************************************************************
215 
#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO port E present
216 
#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO port D present
217 
#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO port C present
218 
#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO port B present
219 
#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO port A present
220 
 
221 
//*****************************************************************************
222 
//
223 
// The following define the bit fields in the SYSCTL_PBORCTL register.
224 
//
225 
//*****************************************************************************
226 
#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC  // BOR wait timer
227 
#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR interrupt or reset
228 
#define SYSCTL_PBORCTL_BORWT    0x00000001  // BOR wait and check for noise
229 
#define SYSCTL_PBORCTL_BOR_SH   2
230 
 
231 
//*****************************************************************************
232 
//
233 
// The following define the bit fields in the SYSCTL_LDOPCTL register.
234 
//
235 
//*****************************************************************************
236 
#define SYSCTL_LDOPCTL_MASK     0x0000003F  // Voltage adjust mask
237 
#define SYSCTL_LDOPCTL_2_25V    0x00000005  // LDO output of 2.25V
238 
#define SYSCTL_LDOPCTL_2_30V    0x00000004  // LDO output of 2.30V
239 
#define SYSCTL_LDOPCTL_2_35V    0x00000003  // LDO output of 2.35V
240 
#define SYSCTL_LDOPCTL_2_40V    0x00000002  // LDO output of 2.40V
241 
#define SYSCTL_LDOPCTL_2_45V    0x00000001  // LDO output of 2.45V
242 
#define SYSCTL_LDOPCTL_2_50V    0x00000000  // LDO output of 2.50V
243 
#define SYSCTL_LDOPCTL_2_55V    0x0000001F  // LDO output of 2.55V
244 
#define SYSCTL_LDOPCTL_2_60V    0x0000001E  // LDO output of 2.60V
245 
#define SYSCTL_LDOPCTL_2_65V    0x0000001D  // LDO output of 2.65V
246 
#define SYSCTL_LDOPCTL_2_70V    0x0000001C  // LDO output of 2.70V
247 
#define SYSCTL_LDOPCTL_2_75V    0x0000001B  // LDO output of 2.75V
248 
 
249 
//*****************************************************************************
250 
//
251 
// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,
252 
// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
253 
//
254 
//*****************************************************************************
255 
#define SYSCTL_SET0_PWM         0x00100000  // PWM module
256 
#define SYSCTL_SET0_ADC         0x00010000  // ADC module
257 
#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00  // ADC speed mask
258 
#define SYSCTL_SET0_ADCSPD_1M   0x00000300  // 1Msps ADC
259 
#define SYSCTL_SET0_ADCSPD_500K 0x00000200  // 500Ksps ADC
260 
#define SYSCTL_SET0_ADCSPD_250K 0x00000100  // 250Ksps ADC
261 
#define SYSCTL_SET0_ADCSPD_125K 0x00000000  // 125Ksps ADC
262 
#define SYSCTL_SET0_WDOG        0x00000008  // Watchdog module
263 
 
264 
//*****************************************************************************
265 
//
266 
// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,
267 
// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
268 
//
269 
//*****************************************************************************
270 
#define SYSCTL_SET1_COMP2       0x04000000  // Analog comparator module 2
271 
#define SYSCTL_SET1_COMP1       0x02000000  // Analog comparator module 1
272 
#define SYSCTL_SET1_COMP0       0x01000000  // Analog comparator module 0
273 
#define SYSCTL_SET1_TIMER2      0x00040000  // Timer module 2
274 
#define SYSCTL_SET1_TIMER1      0x00020000  // Timer module 1
275 
#define SYSCTL_SET1_TIMER0      0x00010000  // Timer module 0
276 
#define SYSCTL_SET1_I2C         0x00001000  // I2C module
277 
#define SYSCTL_SET1_QEI         0x00000100  // QEI module
278 
#define SYSCTL_SET1_SSI         0x00000010  // SSI module
279 
#define SYSCTL_SET1_UART1       0x00000002  // UART module 1
280 
#define SYSCTL_SET1_UART0       0x00000001  // UART module 0
281 
 
282 
//*****************************************************************************
283 
//
284 
// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,
285 
// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
286 
//
287 
//*****************************************************************************
288 
#define SYSCTL_SET2_GPIOE       0x00000010  // GPIO E module
289 
#define SYSCTL_SET2_GPIOD       0x00000008  // GPIO D module
290 
#define SYSCTL_SET2_GPIOC       0x00000004  // GPIO C module
291 
#define SYSCTL_SET2_GPIOB       0x00000002  // GPIO B module
292 
#define SYSCTL_SET2_GPIOA       0x00000001  // GIPO A module
293 
 
294 
//*****************************************************************************
295 
//
296 
// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and
297 
// SYSCTL_IMS registers.
298 
//
299 
//*****************************************************************************
300 
#define SYSCTL_INT_PLL_LOCK     0x00000040  // PLL lock interrupt
301 
#define SYSCTL_INT_CUR_LIMIT    0x00000020  // Current limit interrupt
302 
#define SYSCTL_INT_IOSC_FAIL    0x00000010  // Internal oscillator failure int
303 
#define SYSCTL_INT_MOSC_FAIL    0x00000008  // Main oscillator failure int
304 
#define SYSCTL_INT_POR          0x00000004  // Power on reset interrupt
305 
#define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt
306 
#define SYSCTL_INT_PLL_FAIL     0x00000001  // PLL failure interrupt
307 
 
308 
//*****************************************************************************
309 
//
310 
// The following define the bit fields in the SYSCTL_RESC register.
311 
//
312 
//*****************************************************************************
313 
#define SYSCTL_RESC_LDO         0x00000020  // LDO power OK lost reset
314 
#define SYSCTL_RESC_SW          0x00000010  // Software reset
315 
#define SYSCTL_RESC_WDOG        0x00000008  // Watchdog reset
316 
#define SYSCTL_RESC_BOR         0x00000004  // Brown-out reset
317 
#define SYSCTL_RESC_POR         0x00000002  // Power on reset
318 
#define SYSCTL_RESC_EXT         0x00000001  // External reset
319 
 
320 
//*****************************************************************************
321 
//
322 
// The following define the bit fields in the SYSCTL_RCC register.
323 
//
324 
//*****************************************************************************
325 
#define SYSCTL_RCC_ACG          0x08000000  // Automatic clock gating
326 
#define SYSCTL_RCC_SYSDIV_MASK  0x07800000  // System clock divider
327 
#define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2
328 
#define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3
329 
#define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4
330 
#define SYSCTL_RCC_SYSDIV_5     0x02000000  // System clock /5
331 
#define SYSCTL_RCC_SYSDIV_6     0x02800000  // System clock /6
332 
#define SYSCTL_RCC_SYSDIV_7     0x03000000  // System clock /7
333 
#define SYSCTL_RCC_SYSDIV_8     0x03800000  // System clock /8
334 
#define SYSCTL_RCC_SYSDIV_9     0x04000000  // System clock /9
335 
#define SYSCTL_RCC_SYSDIV_10    0x04800000  // System clock /10
336 
#define SYSCTL_RCC_SYSDIV_11    0x05000000  // System clock /11
337 
#define SYSCTL_RCC_SYSDIV_12    0x05800000  // System clock /12
338 
#define SYSCTL_RCC_SYSDIV_13    0x06000000  // System clock /13
339 
#define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14
340 
#define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15
341 
#define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16
342 
#define SYSCTL_RCC_USE_SYSDIV   0x00400000  // Use sytem clock divider
343 
#define SYSCTL_RCC_USE_PWMDIV   0x00100000  // Use PWM clock divider
344 
#define SYSCTL_RCC_PWMDIV_MASK  0x000E0000  // PWM clock divider
345 
#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
346 
#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
347 
#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
348 
#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
349 
#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
350 
#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
351 
#define SYSCTL_RCC_PWRDN        0x00002000  // PLL power down
352 
#define SYSCTL_RCC_OE           0x00001000  // PLL output enable
353 
#define SYSCTL_RCC_BYPASS       0x00000800  // PLL bypass
354 
#define SYSCTL_RCC_PLLVER       0x00000400  // PLL verification timer enable
355 
#define SYSCTL_RCC_XTAL_MASK    0x000003C0  // Crystal attached to main osc
356 
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // Using a 3.579545MHz crystal
357 
#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140  // Using a 3.6864MHz crystal
358 
#define SYSCTL_RCC_XTAL_4MHz    0x00000180  // Using a 4MHz crystal
359 
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // Using a 4.096MHz crystal
360 
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // Using a 4.9152MHz crystal
361 
#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // Using a 5MHz crystal
362 
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // Using a 5.12MHz crystal
363 
#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // Using a 6MHz crystal
364 
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // Using a 6.144MHz crystal
365 
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // Using a 7.3728MHz crystal
366 
#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // Using a 8MHz crystal
367 
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // Using a 8.192MHz crystal
368 
#define SYSCTL_RCC_OSCSRC_MASK  0x00000030  // Oscillator input select
369 
#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // Use the main oscillator
370 
#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // Use the internal oscillator
371 
#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // Use the internal oscillator / 4
372 
#define SYSCTL_RCC_IOSCVER      0x00000008  // Int. osc. verification timer en
373 
#define SYSCTL_RCC_MOSCVER      0x00000004  // Main osc. verification timer en
374 
#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal oscillator disable
375 
#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main oscillator disable
376 
#define SYSCTL_RCC_SYSDIV_SHIFT 23          // Shift to the SYSDIV field
377 
#define SYSCTL_RCC_PWMDIV_SHIFT 17          // Shift to the PWMDIV field
378 
#define SYSCTL_RCC_XTAL_SHIFT   6           // Shift to the XTAL field
379 
#define SYSCTL_RCC_OSCSRC_SHIFT 4           // Shift to the OSCSRC field
380 
 
381 
//*****************************************************************************
382 
//
383 
// The following define the bit fields in the SYSCTL_PLLCFG register.
384 
//
385 
//*****************************************************************************
386 
#define SYSCTL_PLLCFG_OD_MASK   0x0000C000  // Output divider
387 
#define SYSCTL_PLLCFG_OD_1      0x00000000  // Output divider is 1
388 
#define SYSCTL_PLLCFG_OD_2      0x00004000  // Output divider is 2
389 
#define SYSCTL_PLLCFG_OD_4      0x00008000  // Output divider is 4
390 
#define SYSCTL_PLLCFG_F_MASK    0x00003FE0  // PLL multiplier
391 
#define SYSCTL_PLLCFG_R_MASK    0x0000001F  // Input predivider
392 
#define SYSCTL_PLLCFG_F_SHIFT   5
393 
#define SYSCTL_PLLCFG_R_SHIFT   0
394 
 
395 
//*****************************************************************************
396 
//
397 
// The following define the bit fields in the SYSCTL_CLKVCLR register.
398 
//
399 
//*****************************************************************************
400 
#define SYSCTL_CLKVCLR_CLR      0x00000001  // Clear clock verification fault
401 
 
402 
//*****************************************************************************
403 
//
404 
// The following define the bit fields in the SYSCTL_LDOARST register.
405 
//
406 
//*****************************************************************************
407 
#define SYSCTL_LDOARST_ARST     0x00000001  // Allow LDO to reset device
408 
 
409 
#endif // __HW_SYSCTL_H__

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.