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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_IAR/] [LuminaryCode/] [i2c.c] - Blame information for rev 728

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1 581 jeremybenn 
//*****************************************************************************
2 
//
3 
// i2c.c - Driver for Inter-IC (I2C) bus block.
4 
//
5 
// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
6 
//
7 
// Software License Agreement
8 
//
9 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10 
// exclusively on LMI's Stellaris Family of microcontroller products.
11 
//
12 
// The software is owned by LMI and/or its suppliers, and is protected under
13 
// applicable copyright laws.  All rights are reserved.  Any use in violation
14 
// of the foregoing restrictions may subject the user to criminal sanctions
15 
// under applicable laws, as well as to civil liability for the breach of the
16 
// terms and conditions of this license.
17 
//
18 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19 
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20 
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21 
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
22 
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23 
//
24 
// This is part of revision 991 of the Stellaris Driver Library.
25 
//
26 
//*****************************************************************************
27 
 
28 
//*****************************************************************************
29 
//
30 
//! \addtogroup i2c_api
31 
//! @{
32 
//
33 
//*****************************************************************************
34 
 
35 
#include "../hw_i2c.h"
36 
#include "../hw_ints.h"
37 
#include "../hw_memmap.h"
38 
#include "../hw_types.h"
39 
#include "debug.h"
40 
#include "i2c.h"
41 
#include "interrupt.h"
42 
#include "sysctl.h"
43 
 
44 
//*****************************************************************************
45 
//
46 
//! Initializes the I2C Master block.
47 
//!
48 
//! \param ulBase base address of the I2C Master module
49 
//! \param bFast set up for fast data transfers
50 
//!
51 
//! This function initializes operation of the I2C Master block. Upon
52 
//! successful initialization of the I2C block, this function will have
53 
//! set the bus speed for the master, and will have enabled the I2C Master
54 
//! block.
55 
//!
56 
//! If the parameter \e bFast is \b true, then the master block will be
57 
//! set up to transfer data at 400 kbps; otherwise, it will be set up to
58 
//! transfer data at 100 kbps.
59 
//!
60 
//! The I2C clocking is dependent upon the system clock rate returned by
61 
//! SysCtlClockGet(); if it does not return the correct system clock rate then
62 
//! the I2C clock rate will be incorrect.
63 
//!
64 
//! \return None.
65 
//
66 
//*****************************************************************************
67 
#if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN)
68 
void
69 
I2CMasterInit(unsigned long ulBase, tBoolean bFast)
70 
{
71 
    unsigned long ulSysClk;
72 
    unsigned long ulSCLFreq;
73 
    unsigned long ulTPR;
74 
 
75 
    //
76 
    // Check the arguments.
77 
    //
78 
    ASSERT(ulBase == I2C_MASTER_BASE);
79 
 
80 
    //
81 
    // Must enable the device before doing anything else.
82 
    //
83 
    I2CMasterEnable(ulBase);
84 
 
85 
    //
86 
    // Get the system clock speed.
87 
    //
88 
    ulSysClk = SysCtlClockGet();
89 
 
90 
    //
91 
    // Get the desired SCL speed.
92 
    //
93 
    if(bFast == true)
94 
    {
95 
        ulSCLFreq = I2C_SCL_FAST;
96 
    }
97 
    else
98 
    {
99 
        ulSCLFreq = I2C_SCL_STANDARD;
100 
    }
101 
 
102 
    //
103 
    // Compute the clock divider that achieves the fastest speed less than or
104 
    // equal to the desired speed.  The numerator is biases to favor a larger
105 
    // clock divider so that the resulting clock is always less than or equal
106 
    // to the desired clock, never greater.
107 
    //
108 
    ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) /
109 
              (2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1);
110 
    HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR;
111 
}
112 
#endif
113 
 
114 
//*****************************************************************************
115 
//
116 
//! Initializes the I2C Slave block.
117 
//!
118 
//! \param ulBase base address of the I2C Slave module
119 
//! \param ucSlaveAddr 7-bit slave address
120 
//!
121 
//! This function initializes operation of the I2C Slave block. Upon
122 
//! successful initialization of the I2C blocks, this function will have
123 
//! set the slave address and have enabled the I2C Slave block.
124 
//!
125 
//! The parameter \e ucSlaveAddr is the value that will be compared
126 
//! against the slave address sent by an I2C master.
127 
//!
128 
//! \return None.
129 
//
130 
//*****************************************************************************
131 
#if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN)
132 
void
133 
I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr)
134 
{
135 
    //
136 
    // Check the arguments.
137 
    //
138 
    ASSERT(ulBase == I2C_SLAVE_BASE);
139 
    ASSERT(!(ucSlaveAddr & 0x80));
140 
 
141 
    //
142 
    // Must enable the device before doing anything else.
143 
    //
144 
    I2CSlaveEnable(ulBase);
145 
 
146 
    //
147 
    // Set up the slave address.
148 
    //
149 
    HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr;
150 
}
151 
#endif
152 
 
153 
//*****************************************************************************
154 
//
155 
//! Enables the I2C Master block.
156 
//!
157 
//! \param ulBase base address of the I2C Master module
158 
//!
159 
//! This will enable operation of the I2C Master block.
160 
//!
161 
//! \return None.
162 
//
163 
//*****************************************************************************
164 
#if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN)
165 
void
166 
I2CMasterEnable(unsigned long ulBase)
167 
{
168 
    //
169 
    // Check the arguments.
170 
    //
171 
    ASSERT(ulBase == I2C_MASTER_BASE);
172 
 
173 
    //
174 
    // Enable the master block.
175 
    //
176 
    HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE;
177 
}
178 
#endif
179 
 
180 
//*****************************************************************************
181 
//
182 
//! Enables the I2C Slave block.
183 
//!
184 
//! \param ulBase base address of the I2C Slave module
185 
//!
186 
//! This will enable operation of the I2C Slave block.
187 
//!
188 
//! \return None.
189 
//
190 
//*****************************************************************************
191 
#if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN)
192 
void
193 
I2CSlaveEnable(unsigned long ulBase)
194 
{
195 
    //
196 
    // Check the arguments.
197 
    //
198 
    ASSERT(ulBase == I2C_SLAVE_BASE);
199 
 
200 
    //
201 
    // Enable the clock to the slave block.
202 
    //
203 
    HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE;
204 
 
205 
    //
206 
    // Enable the slave.
207 
    //
208 
    HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA;
209 
}
210 
#endif
211 
 
212 
//*****************************************************************************
213 
//
214 
//! Disables the I2C master block.
215 
//!
216 
//! \param ulBase base address of the I2C Master module
217 
//!
218 
//! This will disable operation of the I2C master block.
219 
//!
220 
//! \return None.
221 
//
222 
//*****************************************************************************
223 
#if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
224 
void
225 
I2CMasterDisable(unsigned long ulBase)
226 
{
227 
    //
228 
    // Check the arguments.
229 
    //
230 
    ASSERT(ulBase == I2C_MASTER_BASE);
231 
 
232 
    //
233 
    // Disable the master block.
234 
    //
235 
    HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE);
236 
}
237 
#endif
238 
 
239 
//*****************************************************************************
240 
//
241 
//! Disables the I2C slave block.
242 
//!
243 
//! \param ulBase base address of the I2C Slave module
244 
//!
245 
//! This will disable operation of the I2C slave block.
246 
//!
247 
//! \return None.
248 
//
249 
//*****************************************************************************
250 
#if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN)
251 
void
252 
I2CSlaveDisable(unsigned long ulBase)
253 
{
254 
    //
255 
    // Check the arguments.
256 
    //
257 
    ASSERT(ulBase == I2C_SLAVE_BASE);
258 
 
259 
    //
260 
    // Disable the slave.
261 
    //
262 
    HWREG(ulBase + I2C_SLAVE_O_CSR) = 0;
263 
 
264 
    //
265 
    // Disable the clock to the slave block.
266 
    //
267 
    HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE);
268 
}
269 
#endif
270 
 
271 
//*****************************************************************************
272 
//
273 
//! Registers an interrupt handler for the I2C module
274 
//!
275 
//! \param ulBase base address of the I2C module
276 
//! \param pfnHandler is a pointer to the function to be called when the
277 
//! synchronous serial interface interrupt occurs.
278 
//!
279 
//! This sets the handler to be called when an I2C interrupt occurs.  This
280 
//! will enable the global interrupt in the interrupt controller; specific I2C
281 
//! interrupts must be enabled via I2CMasterIntEnable() and
282 
//! I2CSlaveIntEnable().  If necessary, it is the interrupt handler's
283 
//! responsibility to clear the interrupt source via I2CMasterIntClear() and
284 
//! I2CSlaveIntClear().
285 
//!
286 
//! \sa IntRegister() for important information about registering interrupt
287 
//! handlers.
288 
//!
289 
//! \return None.
290 
//
291 
//*****************************************************************************
292 
#if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
293 
void
294 
I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
295 
{
296 
    //
297 
    // Check the arguments.
298 
    //
299 
    ASSERT(ulBase == I2C_MASTER_BASE);
300 
 
301 
    //
302 
    // Register the interrupt handler, returning an error if an error occurs.
303 
    //
304 
    IntRegister(INT_I2C, pfnHandler);
305 
 
306 
    //
307 
    // Enable the I2C interrupt.
308 
    //
309 
    IntEnable(INT_I2C);
310 
}
311 
#endif
312 
 
313 
//*****************************************************************************
314 
//
315 
//! Unregisters an interrupt handler for the I2C module.
316 
//!
317 
//! \param ulBase base address of the I2C module
318 
//!
319 
//! This function will clear the handler to be called when an I2C
320 
//! interrupt occurs.  This will also mask off the interrupt in the interrupt
321 
//! controller so that the interrupt handler no longer is called.
322 
//!
323 
//! \sa IntRegister() for important information about registering interrupt
324 
//! handlers.
325 
//!
326 
//! \return None.
327 
//
328 
//*****************************************************************************
329 
#if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
330 
void
331 
I2CIntUnregister(unsigned long ulBase)
332 
{
333 
    //
334 
    // Check the arguments.
335 
    //
336 
    ASSERT(ulBase == I2C_MASTER_BASE);
337 
 
338 
    //
339 
    // Disable the interrupt.
340 
    //
341 
    IntDisable(INT_I2C);
342 
 
343 
    //
344 
    // Unregister the interrupt handler.
345 
    //
346 
    IntUnregister(INT_I2C);
347 
}
348 
#endif
349 
 
350 
//*****************************************************************************
351 
//
352 
//! Enables the I2C Master interrupt.
353 
//!
354 
//! \param ulBase base address of the I2C Master module
355 
//!
356 
//! Enables the I2C Master interrupt source.
357 
//!
358 
//! \return None.
359 
//
360 
//*****************************************************************************
361 
#if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN)
362 
void
363 
I2CMasterIntEnable(unsigned long ulBase)
364 
{
365 
    //
366 
    // Check the arguments.
367 
    //
368 
    ASSERT(ulBase == I2C_MASTER_BASE);
369 
 
370 
    //
371 
    // Enable the master interrupt.
372 
    //
373 
    HWREG(ulBase + I2C_MASTER_O_IMR) = 1;
374 
}
375 
#endif
376 
 
377 
//*****************************************************************************
378 
//
379 
//! Enables the I2C Slave interrupt.
380 
//!
381 
//! \param ulBase base address of the I2C Slave module
382 
//!
383 
//! Enables the I2C Slave interrupt source.
384 
//!
385 
//! \return None.
386 
//
387 
//*****************************************************************************
388 
#if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN)
389 
void
390 
I2CSlaveIntEnable(unsigned long ulBase)
391 
{
392 
    //
393 
    // Check the arguments.
394 
    //
395 
    ASSERT(ulBase == I2C_SLAVE_BASE);
396 
 
397 
    //
398 
    // Enable the slave interrupt.
399 
    //
400 
    HWREG(ulBase + I2C_SLAVE_O_IM) = 1;
401 
}
402 
#endif
403 
 
404 
//*****************************************************************************
405 
//
406 
//! Disables the I2C Master interrupt.
407 
//!
408 
//! \param ulBase base address of the I2C Master module
409 
//!
410 
//! Disables the I2C Master interrupt source.
411 
//!
412 
//! \return None.
413 
//
414 
//*****************************************************************************
415 
#if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
416 
void
417 
I2CMasterIntDisable(unsigned long ulBase)
418 
{
419 
    //
420 
    // Check the arguments.
421 
    //
422 
    ASSERT(ulBase == I2C_MASTER_BASE);
423 
 
424 
    //
425 
    // Disable the master interrupt.
426 
    //
427 
    HWREG(ulBase + I2C_MASTER_O_IMR) = 0;
428 
}
429 
#endif
430 
 
431 
//*****************************************************************************
432 
//
433 
//! Disables the I2C Slave interrupt.
434 
//!
435 
//! \param ulBase base address of the I2C Slave module
436 
//!
437 
//! Disables the I2C Slave interrupt source.
438 
//!
439 
//! \return None.
440 
//
441 
//*****************************************************************************
442 
#if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
443 
void
444 
I2CSlaveIntDisable(unsigned long ulBase)
445 
{
446 
    //
447 
    // Check the arguments.
448 
    //
449 
    ASSERT(ulBase == I2C_SLAVE_BASE);
450 
 
451 
    //
452 
    // Disable the slave interrupt.
453 
    //
454 
    HWREG(ulBase + I2C_SLAVE_O_IM) = 0;
455 
}
456 
#endif
457 
 
458 
//*****************************************************************************
459 
//
460 
//! Gets the current I2C Master interrupt status.
461 
//!
462 
//! \param ulBase base address of the I2C Master module
463 
//! \param bMasked is false if the raw interrupt status is requested and
464 
//! true if the masked interrupt status is requested.
465 
//!
466 
//! This returns the interrupt status for the I2C Master module.
467 
//! Either the raw interrupt status or the status of interrupts that are
468 
//! allowed to reflect to the processor can be returned.
469 
//!
470 
//! \return The current interrupt status, returned as \b true if active
471 
//! or \b false if not active.
472 
//
473 
//*****************************************************************************
474 
#if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
475 
tBoolean
476 
I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked)
477 
{
478 
    //
479 
    // Check the arguments.
480 
    //
481 
    ASSERT(ulBase == I2C_MASTER_BASE);
482 
 
483 
    //
484 
    // Return either the interrupt status or the raw interrupt status as
485 
    // requested.
486 
    //
487 
    if(bMasked)
488 
    {
489 
        return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false);
490 
    }
491 
    else
492 
    {
493 
        return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false);
494 
    }
495 
}
496 
#endif
497 
 
498 
//*****************************************************************************
499 
//
500 
//! Gets the current I2C Slave interrupt status.
501 
//!
502 
//! \param ulBase base address of the I2C Slave module
503 
//! \param bMasked is false if the raw interrupt status is requested and
504 
//! true if the masked interrupt status is requested.
505 
//!
506 
//! This returns the interrupt status for the I2C Slave module.
507 
//! Either the raw interrupt status or the status of interrupts that are
508 
//! allowed to reflect to the processor can be returned.
509 
//!
510 
//! \return The current interrupt status, returned as \b true if active
511 
//! or \b false if not active.
512 
//
513 
//*****************************************************************************
514 
#if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
515 
tBoolean
516 
I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked)
517 
{
518 
    //
519 
    // Check the arguments.
520 
    //
521 
    ASSERT(ulBase == I2C_SLAVE_BASE);
522 
 
523 
    //
524 
    // Return either the interrupt status or the raw interrupt status as
525 
    // requested.
526 
    //
527 
    if(bMasked)
528 
    {
529 
        return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false);
530 
    }
531 
    else
532 
    {
533 
        return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false);
534 
    }
535 
}
536 
#endif
537 
 
538 
//*****************************************************************************
539 
//
540 
//! Clears I2C Master interrupt sources.
541 
//!
542 
//! \param ulBase base address of the I2C Master module
543 
//!
544 
//! The I2C Master interrupt source is cleared, so that it no longer asserts.
545 
//! This must be done in the interrupt handler to keep it from being called
546 
//! again immediately upon exit.
547 
//!
548 
//! \return None.
549 
//
550 
//*****************************************************************************
551 
#if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
552 
void
553 
I2CMasterIntClear(unsigned long ulBase)
554 
{
555 
    //
556 
    // Check the arguments.
557 
    //
558 
    ASSERT(ulBase == I2C_MASTER_BASE);
559 
 
560 
    //
561 
    // Clear the I2C master interrupt source.
562 
    //
563 
    HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC;
564 
 
565 
    //
566 
    // Workaround for I2C master interrupt clear errata for rev B Stellaris
567 
    // devices.  For later devices, this write is ignored and therefore
568 
    // harmless (other than the slight performance hit).
569 
    //
570 
    HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC;
571 
}
572 
#endif
573 
 
574 
//*****************************************************************************
575 
//
576 
//! Clears I2C Slave interrupt sources.
577 
//!
578 
//! \param ulBase base address of the I2C Slave module
579 
//!
580 
//! The I2C Slave interrupt source is cleared, so that it no longer asserts.
581 
//! This must be done in the interrupt handler to keep it from being called
582 
//! again immediately upon exit.
583 
//!
584 
//! \return None.
585 
//
586 
//*****************************************************************************
587 
#if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
588 
void
589 
I2CSlaveIntClear(unsigned long ulBase)
590 
{
591 
    //
592 
    // Check the arguments.
593 
    //
594 
    ASSERT(ulBase == I2C_SLAVE_BASE);
595 
 
596 
    //
597 
    // Clear the I2C slave interrupt source.
598 
    //
599 
    HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC;
600 
}
601 
#endif
602 
 
603 
//*****************************************************************************
604 
//
605 
//! Sets the address that the I2C Master will place on the bus.
606 
//!
607 
//! \param ulBase base address of the I2C Master module
608 
//! \param ucSlaveAddr 7-bit slave address
609 
//! \param bReceive flag indicating the type of communication with the slave
610 
//!
611 
//! This function will set the address that the I2C Master will place on the
612 
//! bus when initiating a transaction. When the parameter \e bReceive is set
613 
//! to \b true, the address will indicate that the I2C Master is initiating
614 
//! a read from the slave; otherwise the address will indicate that the I2C
615 
//! Master is initiating a write to the slave.
616 
//!
617 
//! \return None.
618 
//
619 
//*****************************************************************************
620 
#if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN)
621 
void
622 
I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr,
623 
                      tBoolean bReceive)
624 
{
625 
    //
626 
    // Check the arguments.
627 
    //
628 
    ASSERT(ulBase == I2C_MASTER_BASE);
629 
    ASSERT(!(ucSlaveAddr & 0x80));
630 
 
631 
    //
632 
    // Set the address of the slave with which the master will communicate.
633 
    //
634 
    HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive;
635 
}
636 
#endif
637 
 
638 
//*****************************************************************************
639 
//
640 
//! Indicates whether or not the I2C Master is busy.
641 
//!
642 
//! \param ulBase base address of the I2C Master module
643 
//!
644 
//! This function returns an indication of whether or not the I2C Master is
645 
//! busy transmitting or receiving data.
646 
//!
647 
//! \return Returns \b true if the I2C Master is busy; otherwise, returns
648 
//! \b false.
649 
//
650 
//*****************************************************************************
651 
#if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN)
652 
tBoolean
653 
I2CMasterBusy(unsigned long ulBase)
654 
{
655 
    //
656 
    // Check the arguments.
657 
    //
658 
    ASSERT(ulBase == I2C_MASTER_BASE);
659 
 
660 
    //
661 
    // Return the busy status.
662 
    //
663 
    if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY)
664 
    {
665 
        return(true);
666 
    }
667 
    else
668 
    {
669 
        return(false);
670 
    }
671 
}
672 
#endif
673 
 
674 
//*****************************************************************************
675 
//
676 
//! Indicates whether or not the I2C bus is busy.
677 
//!
678 
//! \param ulBase base address of the I2C Master module
679 
//!
680 
//! This function returns an indication of whether or not the I2C bus is
681 
//! busy. This function can be used in a multi-master environment to
682 
//! determine if another master is currently using the bus.
683 
//!
684 
//! \return Returns \b true if the I2C bus is busy; otherwise, returns
685 
//! \b false.
686 
//
687 
//*****************************************************************************
688 
#if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN)
689 
tBoolean
690 
I2CMasterBusBusy(unsigned long ulBase)
691 
{
692 
    //
693 
    // Check the arguments.
694 
    //
695 
    ASSERT(ulBase == I2C_MASTER_BASE);
696 
 
697 
    //
698 
    // Return the bus busy status.
699 
    //
700 
    if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY)
701 
    {
702 
        return(true);
703 
    }
704 
    else
705 
    {
706 
        return(false);
707 
    }
708 
}
709 
#endif
710 
 
711 
//*****************************************************************************
712 
//
713 
//! Controls the state of the I2C Master module.
714 
//!
715 
//! \param ulBase base address of the I2C Master module
716 
//! \param ulCmd command to be issued to the I2C Master module
717 
//!
718 
//! This function is used to control the state of the Master module send and
719 
//! receive operations. The parameter \e ucCmd can be one of the following
720 
//! values:
721 
//!
722 
//! - I2C_MASTER_CMD_SINGLE_SEND
723 
//! - I2C_MASTER_CMD_SINGLE_RECEIVE
724 
//! - I2C_MASTER_CMD_BURST_SEND_START
725 
//! - I2C_MASTER_CMD_BURST_SEND_CONT
726 
//! - I2C_MASTER_CMD_BURST_SEND_FINISH
727 
//! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
728 
//! - I2C_MASTER_CMD_BURST_RECEIVE_START
729 
//! - I2C_MASTER_CMD_BURST_RECEIVE_CONT
730 
//! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH
731 
//! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
732 
//!
733 
//! \return None.
734 
//
735 
//*****************************************************************************
736 
#if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN)
737 
void
738 
I2CMasterControl(unsigned long ulBase, unsigned long ulCmd)
739 
{
740 
    //
741 
    // Check the arguments.
742 
    //
743 
    ASSERT(ulBase == I2C_MASTER_BASE);
744 
    ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) ||
745 
           (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
746 
           (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) ||
747 
           (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
748 
           (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
749 
           (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
750 
           (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
751 
           (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
752 
           (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
753 
           (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
754 
 
755 
    //
756 
    // Send the command.
757 
    //
758 
    HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd;
759 
}
760 
#endif
761 
 
762 
//*****************************************************************************
763 
//
764 
//! Gets the error status of the I2C Master module.
765 
//!
766 
//! \param ulBase base address of the I2C Master module
767 
//!
768 
//! This function is used to obtain the error status of the Master module
769 
//! send and receive operations. It returns one of the following values:
770 
//!
771 
//! - I2C_MASTER_ERR_NONE
772 
//! - I2C_MASTER_ERR_ADDR_ACK
773 
//! - I2C_MASTER_ERR_DATA_ACK
774 
//! - I2C_MASTER_ERR_ARB_LOST
775 
//!
776 
//! \return None.
777 
//
778 
//*****************************************************************************
779 
#if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN)
780 
unsigned long
781 
I2CMasterErr(unsigned long ulBase)
782 
{
783 
    unsigned long ulErr;
784 
 
785 
    //
786 
    // Check the arguments.
787 
    //
788 
    ASSERT(ulBase == I2C_MASTER_BASE);
789 
 
790 
    //
791 
    // Get the raw error state
792 
    //
793 
    ulErr = HWREG(ulBase + I2C_MASTER_O_CS);
794 
 
795 
    //
796 
    // If the I2C master is busy, then all the other bit are invalid, and
797 
    // don't have an error to report.
798 
    //
799 
    if(ulErr & I2C_MASTER_CS_BUSY)
800 
    {
801 
        return(I2C_MASTER_ERR_NONE);
802 
    }
803 
 
804 
    //
805 
    // Check for errors.
806 
    //
807 
    if(ulErr & I2C_MASTER_CS_ERROR)
808 
    {
809 
        return(ulErr & (I2C_MASTER_CS_ERR_MASK));
810 
    }
811 
    else
812 
    {
813 
        return(I2C_MASTER_ERR_NONE);
814 
    }
815 
}
816 
#endif
817 
 
818 
//*****************************************************************************
819 
//
820 
//! Transmits a byte from the I2C Master.
821 
//!
822 
//! \param ulBase base address of the I2C Master module
823 
//! \param ucData data to be transmitted from the I2C Master
824 
//!
825 
//! This function will place the supplied data into I2C Master Data Register.
826 
//!
827 
//! \return None.
828 
//
829 
//*****************************************************************************
830 
#if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN)
831 
void
832 
I2CMasterDataPut(unsigned long ulBase, unsigned char ucData)
833 
{
834 
    //
835 
    // Check the arguments.
836 
    //
837 
    ASSERT(ulBase == I2C_MASTER_BASE);
838 
 
839 
    //
840 
    // Write the byte.
841 
    //
842 
    HWREG(ulBase + I2C_MASTER_O_DR) = ucData;
843 
}
844 
#endif
845 
 
846 
//*****************************************************************************
847 
//
848 
//! Receives a byte that has been sent to the I2C Master.
849 
//!
850 
//! \param ulBase base address of the I2C Master module
851 
//!
852 
//! This function reads a byte of data from the I2C Master Data Register.
853 
//!
854 
//! \return Returns the byte received from by the I2C Master, cast as an
855 
//! unsigned long.
856 
//
857 
//*****************************************************************************
858 
#if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN)
859 
unsigned long
860 
I2CMasterDataGet(unsigned long ulBase)
861 
{
862 
    //
863 
    // Check the arguments.
864 
    //
865 
    ASSERT(ulBase == I2C_MASTER_BASE);
866 
 
867 
    //
868 
    // Read a byte.
869 
    //
870 
    return(HWREG(ulBase + I2C_MASTER_O_DR));
871 
}
872 
#endif
873 
 
874 
//*****************************************************************************
875 
//
876 
//! Gets the I2C Slave module status
877 
//!
878 
//! \param ulBase base address of the I2C Slave module
879 
//!
880 
//! This function will return the action requested from a master, if any. The
881 
//! possible values returned are:
882 
//!
883 
//! - I2C_SLAVE_ACT_NONE
884 
//! - I2C_SLAVE_ACT_RREQ
885 
//! - I2C_SLAVE_ACT_TREQ
886 
//!
887 
//! where I2C_SLAVE_ACT_NONE means that no action has been requested of the
888 
//! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent
889 
//! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C
890 
//! master has requested that the I2C Slave module send data.
891 
//!
892 
//! \return None.
893 
//
894 
//*****************************************************************************
895 
#if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN)
896 
unsigned long
897 
I2CSlaveStatus(unsigned long ulBase)
898 
{
899 
    //
900 
    // Check the arguments.
901 
    //
902 
    ASSERT(ulBase == I2C_SLAVE_BASE);
903 
 
904 
    //
905 
    // Return the slave status.
906 
    //
907 
    return(HWREG(ulBase + I2C_SLAVE_O_CSR));
908 
}
909 
#endif
910 
 
911 
//*****************************************************************************
912 
//
913 
//! Transmits a byte from the I2C Slave.
914 
//!
915 
//! \param ulBase base address of the I2C Slave module
916 
//! \param ucData data to be transmitted from the I2C Slave
917 
//!
918 
//! This function will place the supplied data into I2C Slave Data Register.
919 
//!
920 
//! \return None.
921 
//
922 
//*****************************************************************************
923 
#if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN)
924 
void
925 
I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData)
926 
{
927 
    //
928 
    // Check the arguments.
929 
    //
930 
    ASSERT(ulBase == I2C_SLAVE_BASE);
931 
 
932 
    //
933 
    // Write the byte.
934 
    //
935 
    HWREG(ulBase + I2C_SLAVE_O_DR) = ucData;
936 
}
937 
#endif
938 
 
939 
//*****************************************************************************
940 
//
941 
//! Receives a byte that has been sent to the I2C Slave.
942 
//!
943 
//! \param ulBase base address of the I2C Slave module
944 
//!
945 
//! This function reads a byte of data from the I2C Slave Data Register.
946 
//!
947 
//! \return Returns the byte received from by the I2C Slave, cast as an
948 
//! unsigned long.
949 
//
950 
//*****************************************************************************
951 
#if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN)
952 
unsigned long
953 
I2CSlaveDataGet(unsigned long ulBase)
954 
{
955 
    //
956 
    // Check the arguments.
957 
    //
958 
    ASSERT(ulBase == I2C_SLAVE_BASE);
959 
 
960 
    //
961 
    // Read a byte.
962 
    //
963 
    return(HWREG(ulBase + I2C_SLAVE_O_DR));
964 
}
965 
#endif
966 
 
967 
//*****************************************************************************
968 
//
969 
// Close the Doxygen group.
970 
//! @}
971 
//
972 
//*****************************************************************************

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