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//*****************************************************************************
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//
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// pwm.c - API for the PWM modules
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//
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// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's Stellaris Family of microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 991 of the Stellaris Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup pwm_api
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//! @{
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//
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//*****************************************************************************
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#include "../hw_ints.h"
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#include "../hw_memmap.h"
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#include "../hw_pwm.h"
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#include "../hw_types.h"
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#include "debug.h"
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#include "interrupt.h"
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#include "pwm.h"
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//*****************************************************************************
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//
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// Misc macros for manipulating the encoded generator and output defines used
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// by the API.
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//
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//*****************************************************************************
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#define PWM_GEN_BADDR(_mod_, _gen_) \
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((_mod_) + (_gen_))
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#define PWM_OUT_BADDR(_mod_, _out_) \
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((_mod_) + ((_out_) & 0xFFFFFFC0))
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#define PWM_IS_OUTPUT_ODD(_out_) \
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((_out_) & 0x00000001)
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//*****************************************************************************
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//
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//! Configures a PWM generator.
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//!
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//! \param ulBase is the base address of the PWM module.
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//! \param ulGen is the PWM generator to configure. Must be one of
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//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
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//! \param ulConfig is the configuration for the PWM generator.
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//!
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//! This function is used to set the mode of operation for a PWM generator.
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//! The counting mode, synchronization mode, and debug behavior are all
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//! configured. After configuration, the generator is left in the disabled
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//! state.
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//!
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//! A PWM generator can count in two different modes: count down mode or count
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//! up/down mode. In count down mode, it will count from a value down to zero,
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//! and then reset to the preset value. This will produce left-aligned PWM
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//! signals (i.e. the rising edge of the two PWM signals produced by the
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//! generator will occur at the same time). In count up/down mode, it will
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//! count up from zero to the preset value, count back down to zero, and then
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//! repeat the process. This will produce center-aligned PWM signals (i.e. the
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//! middle of the high/low period of the PWM signals produced by the generator
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//! will occur at the same time).
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//!
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//! When the PWM generator parameters (period and pulse width) are modified,
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//! their affect on the output PWM signals can be delayed. In synchronous
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//! mode, the parameter updates are not applied until a synchronization event
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//! occurs. This allows multiple parameters to be modified and take affect
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//! simultaneously, instead of one at a time. Additionally, parameters to
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//! multiple PWM generators in synchronous mode can be updated simultaneously,
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//! allowing them to be treated as if they were a unified generator. In
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//! non-synchronous mode, the parameter updates are not delayed until a
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//! synchronization event. In either mode, the parameter updates only occur
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//! when the counter is at zero to help prevent oddly formed PWM signals during
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//! the update (i.e. a PWM pulse that is too short or too long).
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//!
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//! The PWM generator can either pause or continue running when the processor
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//! is stopped via the debugger. If configured to pause, it will continue to
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//! count until it reaches zero, at which point it will pause until the
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//! processor is restarted. If configured to continue running, it will keep
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//! counting as if nothing had happened.
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//!
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//! The \b ulConfig parameter contains the desired configuration. It is the
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//! logical OR of the following: \b PWM_GEN_MODE_DOWN or
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//! \b PWM_GEN_MODE_UP_DOWN to specify the counting mode, \b PWM_GEN_MODE_SYNC
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//! or \b PWM_GEN_MODE_NO_SYNC to specify the synchronization mode, and
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//! \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug
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//! behavior.
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//!
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//! \note Changes to the counter mode will affect the period of the PWM signals
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//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after
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//! any changes to the counter mode of a generator.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_genconfigure) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
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unsigned long ulConfig)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == PWM_BASE);
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ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
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(ulGen == PWM_GEN_2));
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//
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// Compute the generator's base address.
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//
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ulGen = PWM_GEN_BADDR(ulBase, ulGen);
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//
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// Change the global configuration of the generator.
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//
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HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) &
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~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG |
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PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD |
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PWM_X_CTL_CMPBUPD)) | ulConfig);
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//
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// Set the individual PWM generator controls.
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//
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if(ulConfig & PWM_X_CTL_MODE)
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{
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//
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// In up/down count mode, set the signal high on up count comparison
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// and low on down count comparison (i.e. center align the signals).
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//
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HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE <<
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PWM_GEN_ACT_A_UP_SHIFT) |
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(PWM_GEN_ACT_ZERO <<
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PWM_GEN_ACT_A_DN_SHIFT));
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HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE <<
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PWM_GEN_ACT_B_UP_SHIFT) |
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(PWM_GEN_ACT_ZERO <<
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PWM_GEN_ACT_B_DN_SHIFT));
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}
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else
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{
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//
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// In down count mode, set the signal high on load and low on count
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// comparison (i.e. left align the signals).
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//
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HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE <<
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PWM_GEN_ACT_LOAD_SHIFT) |
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(PWM_GEN_ACT_ZERO <<
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PWM_GEN_ACT_A_DN_SHIFT));
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HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE <<
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PWM_GEN_ACT_LOAD_SHIFT) |
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(PWM_GEN_ACT_ZERO <<
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PWM_GEN_ACT_B_DN_SHIFT));
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}
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}
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#endif
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//*****************************************************************************
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//
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//! Set the period of a PWM generator.
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//!
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//! \param ulBase is the base address of the PWM module.
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//! \param ulGen is the PWM generator to be modified. Must be one of
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//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
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//! \param ulPeriod specifies the period of PWM generator output, measured
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//! in clock ticks.
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//!
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//! This function sets the period of the specified PWM generator block, where
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//! the period of the generator block is defined as the number of \b PWM
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//! clock ticks between pulses on the generator block \b zero signal.
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//!
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//! \note Any subsequent calls made to this function before an update occurs
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//! will cause the previous values to be overwritten.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_genperiodset) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
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unsigned long ulPeriod)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == PWM_BASE);
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ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
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(ulGen == PWM_GEN_2));
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//
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// Compute the generator's base address.
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//
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ulGen = PWM_GEN_BADDR(ulBase, ulGen);
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//
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// Set the reload register based on the mode.
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//
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if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
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{
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//
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// In up/down count mode, set the reload register to half the requested
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// period.
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//
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ASSERT((ulPeriod / 2) < 65536);
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HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2;
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}
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else
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{
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//
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// In down count mode, set the reload register to the requested period
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// minus one.
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//
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ASSERT((ulPeriod <= 65536) && (ulPeriod != 0));
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HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1;
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}
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}
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#endif
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//*****************************************************************************
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//
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//! Gets the period of a PWM generator block.
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//!
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//! \param ulBase is the base address of the PWM module.
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//! \param ulGen is the PWM generator to query. Must be one of
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//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
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//!
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//! This function gets the period of the specified PWM generator block. The
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//! period of the generator block is defined as the number of \b PWM clock
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//! ticks between pulses on the generator block \b zero signal.
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//!
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//! If the update of the counter for the specified PWM generator has yet
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//! to be completed, the value returned may not be the active period. The
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//! value returned is the programmed period, measured in \b PWM clock ticks.
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//!
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//! \return Returns the programmed period of the specified generator block
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//! in \b PWM clock ticks.
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//
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//*****************************************************************************
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#if defined(GROUP_genperiodget) || defined(BUILD_ALL) || defined(DOXYGEN)
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unsigned long
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PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == PWM_BASE);
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ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
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(ulGen == PWM_GEN_2));
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//
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// Compute the generator's base address.
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//
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ulGen = PWM_GEN_BADDR(ulBase, ulGen);
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//
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// Figure out the counter mode.
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//
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if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
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{
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//
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// The period is twice the reload register value.
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//
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return(HWREG(ulGen + PWM_O_X_LOAD) * 2);
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}
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else
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{
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//
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// The period is the reload register value plus one.
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//
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return(HWREG(ulGen + PWM_O_X_LOAD) + 1);
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}
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}
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#endif
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//*****************************************************************************
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//
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//! Enables the timer/counter for a PWM generator block.
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//!
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//! \param ulBase is the base address of the PWM module.
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//! \param ulGen is the PWM generator to be enabled. Must be one of
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//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
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//!
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//! This function allows the \b PWM clock to drive the timer/counter for the
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//! specified generator block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#if defined(GROUP_genenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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PWMGenEnable(unsigned long ulBase, unsigned long ulGen)
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{
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//
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// Check the arguments.
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//
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ASSERT(ulBase == PWM_BASE);
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ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
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(ulGen == PWM_GEN_2));
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//
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// Enable the PWM generator.
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//
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HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE;
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}
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#endif
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//*****************************************************************************
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//
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//! Disables the timer/counter for a PWM generator block.
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//!
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//! \param ulBase is the base address of the PWM module.
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//! \param ulGen is the PWM generator to be disabled. Must be one of
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//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
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//!
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//! This function blocks the \b PWM clock from driving the timer/counter for
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//! the specified generator block.
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//!
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//! \return None.
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//
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//*****************************************************************************
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336 |
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#if defined(GROUP_gendisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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void
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PWMGenDisable(unsigned long ulBase, unsigned long ulGen)
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{
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340 |
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//
|
341 |
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// Check the arguments.
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342 |
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//
|
343 |
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ASSERT(ulBase == PWM_BASE);
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344 |
|
|
ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
|
345 |
|
|
(ulGen == PWM_GEN_2));
|
346 |
|
|
|
347 |
|
|
//
|
348 |
|
|
// Disable the PWM generator.
|
349 |
|
|
//
|
350 |
|
|
HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE);
|
351 |
|
|
}
|
352 |
|
|
#endif
|
353 |
|
|
|
354 |
|
|
//*****************************************************************************
|
355 |
|
|
//
|
356 |
|
|
//! Sets the pulse width for the specified PWM output.
|
357 |
|
|
//!
|
358 |
|
|
//! \param ulBase is the base address of the PWM module.
|
359 |
|
|
//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0,
|
360 |
|
|
//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5.
|
361 |
|
|
//! \param ulWidth specifies the width of the positive portion of the pulse.
|
362 |
|
|
//!
|
363 |
|
|
//! This function sets the pulse width for the specified PWM output, where the
|
364 |
|
|
//! pulse width is defined as the number of \b PWM clock ticks.
|
365 |
|
|
//!
|
366 |
|
|
//! \note Any subsequent calls made to this function before an update occurs
|
367 |
|
|
//! will cause the previous values to be overwritten.
|
368 |
|
|
//!
|
369 |
|
|
//! \return None.
|
370 |
|
|
//
|
371 |
|
|
//*****************************************************************************
|
372 |
|
|
#if defined(GROUP_pulsewidthset) || defined(BUILD_ALL) || defined(DOXYGEN)
|
373 |
|
|
void
|
374 |
|
|
PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
|
375 |
|
|
unsigned long ulWidth)
|
376 |
|
|
{
|
377 |
|
|
unsigned long ulGenBase, ulReg;
|
378 |
|
|
|
379 |
|
|
//
|
380 |
|
|
// Check the arguments.
|
381 |
|
|
//
|
382 |
|
|
ASSERT(ulBase == PWM_BASE);
|
383 |
|
|
ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||
|
384 |
|
|
(ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||
|
385 |
|
|
(ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5));
|
386 |
|
|
|
387 |
|
|
//
|
388 |
|
|
// Compute the generator's base address.
|
389 |
|
|
//
|
390 |
|
|
ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
|
391 |
|
|
|
392 |
|
|
//
|
393 |
|
|
// If the counter is in up/down count mode, divide the width by two.
|
394 |
|
|
//
|
395 |
|
|
if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
|
396 |
|
|
{
|
397 |
|
|
ulWidth /= 2;
|
398 |
|
|
}
|
399 |
|
|
|
400 |
|
|
//
|
401 |
|
|
// Get the period.
|
402 |
|
|
//
|
403 |
|
|
ulReg = HWREG(ulGenBase + PWM_O_X_LOAD);
|
404 |
|
|
|
405 |
|
|
//
|
406 |
|
|
// Make sure the width is not too large.
|
407 |
|
|
//
|
408 |
|
|
ASSERT(ulWidth < ulReg);
|
409 |
|
|
|
410 |
|
|
//
|
411 |
|
|
// Compute the compare value.
|
412 |
|
|
//
|
413 |
|
|
ulReg = ulReg - ulWidth;
|
414 |
|
|
|
415 |
|
|
//
|
416 |
|
|
// Write to the appropriate registers.
|
417 |
|
|
//
|
418 |
|
|
if(PWM_IS_OUTPUT_ODD(ulPWMOut))
|
419 |
|
|
{
|
420 |
|
|
HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg;
|
421 |
|
|
}
|
422 |
|
|
else
|
423 |
|
|
{
|
424 |
|
|
HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg;
|
425 |
|
|
}
|
426 |
|
|
}
|
427 |
|
|
#endif
|
428 |
|
|
|
429 |
|
|
//*****************************************************************************
|
430 |
|
|
//
|
431 |
|
|
//! Gets the pulse width of a PWM output.
|
432 |
|
|
//!
|
433 |
|
|
//! \param ulBase is the base address of the PWM module.
|
434 |
|
|
//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0,
|
435 |
|
|
//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5.
|
436 |
|
|
//!
|
437 |
|
|
//! This function gets the currently programmed pulse width for the
|
438 |
|
|
//! specified PWM output. If the update of the comparator for the specified
|
439 |
|
|
//! output has yet to be completed, the value returned may not be the active
|
440 |
|
|
//! pulse width. The value returned is the programmed pulse width, measured
|
441 |
|
|
//! in \b PWM clock ticks.
|
442 |
|
|
//!
|
443 |
|
|
//! \return Returns the width of the pulse in \b PWM clock ticks.
|
444 |
|
|
//
|
445 |
|
|
//*****************************************************************************
|
446 |
|
|
#if defined(GROUP_pulsewidthget) || defined(BUILD_ALL) || defined(DOXYGEN)
|
447 |
|
|
unsigned long
|
448 |
|
|
PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut)
|
449 |
|
|
{
|
450 |
|
|
unsigned long ulGenBase, ulReg, ulLoad;
|
451 |
|
|
|
452 |
|
|
//
|
453 |
|
|
// Check the arguments.
|
454 |
|
|
//
|
455 |
|
|
ASSERT(ulBase == PWM_BASE);
|
456 |
|
|
ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||
|
457 |
|
|
(ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||
|
458 |
|
|
(ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5));
|
459 |
|
|
|
460 |
|
|
//
|
461 |
|
|
// Compute the generator's base address.
|
462 |
|
|
//
|
463 |
|
|
ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
|
464 |
|
|
|
465 |
|
|
//
|
466 |
|
|
// Then compute the pulse width. If mode is UpDown, set
|
467 |
|
|
// width = (load-compare)*2. Otherwise, set width = load - compare
|
468 |
|
|
//
|
469 |
|
|
ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD);
|
470 |
|
|
if(PWM_IS_OUTPUT_ODD(ulPWMOut))
|
471 |
|
|
{
|
472 |
|
|
ulReg = HWREG(ulGenBase + PWM_O_X_CMPB);
|
473 |
|
|
}
|
474 |
|
|
else
|
475 |
|
|
{
|
476 |
|
|
ulReg = HWREG(ulGenBase + PWM_O_X_CMPA);
|
477 |
|
|
}
|
478 |
|
|
ulReg = ulLoad - ulReg;
|
479 |
|
|
|
480 |
|
|
//
|
481 |
|
|
// If in up/down count mode, double the pulse width.
|
482 |
|
|
//
|
483 |
|
|
if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
|
484 |
|
|
{
|
485 |
|
|
ulReg = ulReg * 2;
|
486 |
|
|
}
|
487 |
|
|
|
488 |
|
|
//
|
489 |
|
|
// Return the pulse width.
|
490 |
|
|
//
|
491 |
|
|
return(ulReg);
|
492 |
|
|
}
|
493 |
|
|
#endif
|
494 |
|
|
|
495 |
|
|
//*****************************************************************************
|
496 |
|
|
//
|
497 |
|
|
//! Enables the PWM dead band output, and sets the dead band delays.
|
498 |
|
|
//!
|
499 |
|
|
//! \param ulBase is the base address of the PWM module.
|
500 |
|
|
//! \param ulGen is the PWM generator to modify. Must be one of
|
501 |
|
|
//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
|
502 |
|
|
//! \param usRise specifies the width of delay from the rising edge.
|
503 |
|
|
//! \param usFall specifies the width of delay from the falling edge.
|
504 |
|
|
//!
|
505 |
|
|
//! This function sets the dead bands for the specified PWM generator,
|
506 |
|
|
//! where the dead bands are defined as the number of \b PWM clock ticks
|
507 |
|
|
//! from the rising or falling edge of the generator's \b OutA signal.
|
508 |
|
|
//! Note that this function causes the coupling of \b OutB to \b OutA.
|
509 |
|
|
//!
|
510 |
|
|
//! \return None.
|
511 |
|
|
//
|
512 |
|
|
//*****************************************************************************
|
513 |
|
|
#if defined(GROUP_deadbandenable) || defined(BUILD_ALL) || defined(DOXYGEN)
|
514 |
|
|
void
|
515 |
|
|
PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
|
516 |
|
|
unsigned short usRise, unsigned short usFall)
|
517 |
|
|
{
|
518 |
|
|
//
|
519 |
|
|
// Check the arguments.
|
520 |
|
|
//
|
521 |
|
|
ASSERT(ulBase == PWM_BASE);
|
522 |
|
|
ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
|
523 |
|
|
(ulGen == PWM_GEN_2));
|
524 |
|
|
ASSERT(usRise < 4096);
|
525 |
|
|
ASSERT(usFall < 4096);
|
526 |
|
|
|
527 |
|
|
//
|
528 |
|
|
// Compute the generator's base address.
|
529 |
|
|
//
|
530 |
|
|
ulGen = PWM_GEN_BADDR(ulBase, ulGen);
|
531 |
|
|
|
532 |
|
|
//
|
533 |
|
|
// Write the dead band delay values.
|
534 |
|
|
//
|
535 |
|
|
HWREG(ulGen + PWM_O_X_DBRISE) = usRise;
|
536 |
|
|
HWREG(ulGen + PWM_O_X_DBFALL) = usFall;
|
537 |
|
|
|
538 |
|
|
//
|
539 |
|
|
// Enable the deadband functionality.
|
540 |
|
|
//
|
541 |
|
|
HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_DBCTL_ENABLE;
|
542 |
|
|
}
|
543 |
|
|
#endif
|
544 |
|
|
|
545 |
|
|
//*****************************************************************************
|
546 |
|
|
//
|
547 |
|
|
//! Disables the PWM dead band output.
|
548 |
|
|
//!
|
549 |
|
|
//! \param ulBase is the base address of the PWM module.
|
550 |
|
|
//! \param ulGen is the PWM generator to modify. Must be one of
|
551 |
|
|
//! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
|
552 |
|
|
//!
|
553 |
|
|
//! This function disables the dead band mode for the specified PWM generator.
|
554 |
|
|
//! Doing so decouples the \b OutA and \b OutB signals.
|
555 |
|
|
//!
|
556 |
|
|
//! \return None.
|
557 |
|
|
//
|
558 |
|
|
//*****************************************************************************
|
559 |
|
|
#if defined(GROUP_deadbanddisable) || defined(BUILD_ALL) || defined(DOXYGEN)
|
560 |
|
|
void
|
561 |
|
|
PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen)
|
562 |
|
|
{
|
563 |
|
|
//
|
564 |
|
|
// Check the arguments.
|
565 |
|
|
//
|
566 |
|
|
ASSERT(ulBase == PWM_BASE);
|
567 |
|
|
ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
|
568 |
|
|
(ulGen == PWM_GEN_2));
|
569 |
|
|
|
570 |
|
|
//
|
571 |
|
|
// Disable the deadband functionality.
|
572 |
|
|
//
|
573 |
|
|
HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= ~(PWM_DBCTL_ENABLE);
|
574 |
|
|
}
|
575 |
|
|
#endif
|
576 |
|
|
|
577 |
|
|
//*****************************************************************************
|
578 |
|
|
//
|
579 |
|
|
//! Synchronizes all pending updates.
|
580 |
|
|
//!
|
581 |
|
|
//! \param ulBase is the base address of the PWM module.
|
582 |
|
|
//! \param ulGenBits are the PWM generator blocks to be updated. Must be the
|
583 |
|
|
//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or
|
584 |
|
|
//! \b PWM_GEN_2_BIT.
|
585 |
|
|
//!
|
586 |
|
|
//! For the selected PWM generators, this function causes all queued updates to
|
587 |
|
|
//! the period or pulse width to be applied the next time the corresponding
|
588 |
|
|
//! counter becomes zero.
|
589 |
|
|
//!
|
590 |
|
|
//! \return None.
|
591 |
|
|
//
|
592 |
|
|
//*****************************************************************************
|
593 |
|
|
#if defined(GROUP_syncupdate) || defined(BUILD_ALL) || defined(DOXYGEN)
|
594 |
|
|
void
|
595 |
|
|
PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits)
|
596 |
|
|
{
|
597 |
|
|
//
|
598 |
|
|
// Check the arguments.
|
599 |
|
|
//
|
600 |
|
|
ASSERT(ulBase == PWM_BASE);
|
601 |
|
|
ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT)));
|
602 |
|
|
|
603 |
|
|
//
|
604 |
|
|
// Update the PWM timing registers.
|
605 |
|
|
//
|
606 |
|
|
HWREG(ulBase + PWM_O_CTL) = ulGenBits;
|
607 |
|
|
}
|
608 |
|
|
#endif
|
609 |
|
|
|
610 |
|
|
//*****************************************************************************
|
611 |
|
|
//
|
612 |
|
|
//! Synchronizes the counters in one or multiple PWM generator blocks.
|
613 |
|
|
//!
|
614 |
|
|
//! \param ulBase is the base address of the PWM module.
|
615 |
|
|
//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be
|
616 |
|
|
//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or
|
617 |
|
|
//! \b PWM_GEN_2_BIT.
|
618 |
|
|
//!
|
619 |
|
|
//! For the selected PWM module, this function synchronizes the time base
|
620 |
|
|
//! of the generator blocks by causing the specified generator counters to be
|
621 |
|
|
//! reset to zero.
|
622 |
|
|
//!
|
623 |
|
|
//! \return None.
|
624 |
|
|
//
|
625 |
|
|
//*****************************************************************************
|
626 |
|
|
#if defined(GROUP_synctimebase) || defined(BUILD_ALL) || defined(DOXYGEN)
|
627 |
|
|
void
|
628 |
|
|
PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits)
|
629 |
|
|
{
|
630 |
|
|
//
|
631 |
|
|
// Check the arguments.
|
632 |
|
|
//
|
633 |
|
|
ASSERT(ulBase == PWM_BASE);
|
634 |
|
|
ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT)));
|
635 |
|
|
|
636 |
|
|
//
|
637 |
|
|
// Synchronize the counters in the specified generators by writing to
|
638 |
|
|
// the module's synchronization register.
|
639 |
|
|
//
|
640 |
|
|
HWREG(ulBase + PWM_O_SYNC) = ulGenBits;
|
641 |
|
|
}
|
642 |
|
|
#endif
|
643 |
|
|
|
644 |
|
|
//*****************************************************************************
|
645 |
|
|
//
|
646 |
|
|
//! Enables or disables PWM outputs.
|
647 |
|
|
//!
|
648 |
|
|
//! \param ulBase is the base address of the PWM module.
|
649 |
|
|
//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
|
650 |
|
|
//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
|
651 |
|
|
//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT.
|
652 |
|
|
//! \param bEnable determines if the signal is enabled or disabled.
|
653 |
|
|
//!
|
654 |
|
|
//! This function is used to enable or disable the selected PWM outputs. The
|
655 |
|
|
//! outputs are selected using the parameter \e ulPWMOutBits. The parameter
|
656 |
|
|
//! \e bEnable determines the state of the selected outputs. If \e bEnable is
|
657 |
|
|
//! \b true, then the selected PWM outputs are enabled, or placed in the active
|
658 |
|
|
//! state. If \e bEnable is \b false, then the selected outputs are disabled,
|
659 |
|
|
//! or placed in the inactive state.
|
660 |
|
|
//!
|
661 |
|
|
//! \return None.
|
662 |
|
|
//
|
663 |
|
|
//*****************************************************************************
|
664 |
|
|
#if defined(GROUP_outputstate) || defined(BUILD_ALL) || defined(DOXYGEN)
|
665 |
|
|
void
|
666 |
|
|
PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
|
667 |
|
|
tBoolean bEnable)
|
668 |
|
|
{
|
669 |
|
|
//
|
670 |
|
|
// Check the arguments.
|
671 |
|
|
//
|
672 |
|
|
ASSERT(ulBase == PWM_BASE);
|
673 |
|
|
ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
|
674 |
|
|
PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT)));
|
675 |
|
|
|
676 |
|
|
//
|
677 |
|
|
// Read the module's ENABLE output control register, and set or clear
|
678 |
|
|
// the requested bits.
|
679 |
|
|
//
|
680 |
|
|
if(bEnable == true)
|
681 |
|
|
{
|
682 |
|
|
HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits;
|
683 |
|
|
}
|
684 |
|
|
else
|
685 |
|
|
{
|
686 |
|
|
HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits);
|
687 |
|
|
}
|
688 |
|
|
}
|
689 |
|
|
#endif
|
690 |
|
|
|
691 |
|
|
//*****************************************************************************
|
692 |
|
|
//
|
693 |
|
|
//! Selects the inversion mode for PWM outputs.
|
694 |
|
|
//!
|
695 |
|
|
//! \param ulBase is the base address of the PWM module.
|
696 |
|
|
//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
|
697 |
|
|
//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
|
698 |
|
|
//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT.
|
699 |
|
|
//! \param bInvert determines if the signal is inverted or passed through.
|
700 |
|
|
//!
|
701 |
|
|
//! This function is used to select the inversion mode for the selected PWM
|
702 |
|
|
//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
|
703 |
|
|
//! The parameter \e bInvert determines the inversion mode for the selected
|
704 |
|
|
//! outputs. If \e bInvert is \b true, this function will cause the specified
|
705 |
|
|
//! PWM output signals to be inverted, or made active low. If \e bInvert is
|
706 |
|
|
//! \b false, the specified output will be passed through as is, or be made
|
707 |
|
|
//! active high.
|
708 |
|
|
//!
|
709 |
|
|
//! \return None.
|
710 |
|
|
//
|
711 |
|
|
//*****************************************************************************
|
712 |
|
|
#if defined(GROUP_outputinvert) || defined(BUILD_ALL) || defined(DOXYGEN)
|
713 |
|
|
void
|
714 |
|
|
PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
|
715 |
|
|
tBoolean bInvert)
|
716 |
|
|
{
|
717 |
|
|
//
|
718 |
|
|
// Check the arguments.
|
719 |
|
|
//
|
720 |
|
|
ASSERT(ulBase == PWM_BASE);
|
721 |
|
|
ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
|
722 |
|
|
PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT)));
|
723 |
|
|
|
724 |
|
|
//
|
725 |
|
|
// Read the module's INVERT output control register, and set or clear
|
726 |
|
|
// the requested bits.
|
727 |
|
|
//
|
728 |
|
|
if(bInvert == true)
|
729 |
|
|
{
|
730 |
|
|
HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits;
|
731 |
|
|
}
|
732 |
|
|
else
|
733 |
|
|
{
|
734 |
|
|
HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits);
|
735 |
|
|
}
|
736 |
|
|
}
|
737 |
|
|
#endif
|
738 |
|
|
|
739 |
|
|
//*****************************************************************************
|
740 |
|
|
//
|
741 |
|
|
//! Specifies the state of PWM outputs in response to a fault condition.
|
742 |
|
|
//!
|
743 |
|
|
//! \param ulBase is the base address of the PWM module.
|
744 |
|
|
//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
|
745 |
|
|
//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
|
746 |
|
|
//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT.
|
747 |
|
|
//! \param bFaultKill determines if the signal is killed or passed through
|
748 |
|
|
//! during an active fault condition.
|
749 |
|
|
//!
|
750 |
|
|
//! This function sets the fault handling characteristics of the selected PWM
|
751 |
|
|
//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
|
752 |
|
|
//! The parameter \e bFaultKill determines the fault handling characteristics
|
753 |
|
|
//! for the selected outputs. If \e bFaultKill is \b true, then the selected
|
754 |
|
|
//! outputs will be made inactive. If \e bFaultKill is \b false, then the
|
755 |
|
|
//! selected outputs are unaffected by the detected fault.
|
756 |
|
|
//!
|
757 |
|
|
//! \return None.
|
758 |
|
|
//
|
759 |
|
|
//*****************************************************************************
|
760 |
|
|
#if defined(GROUP_outputfault) || defined(BUILD_ALL) || defined(DOXYGEN)
|
761 |
|
|
void
|
762 |
|
|
PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
|
763 |
|
|
tBoolean bFaultKill)
|
764 |
|
|
{
|
765 |
|
|
//
|
766 |
|
|
// Check the arguments.
|
767 |
|
|
//
|
768 |
|
|
ASSERT(ulBase == PWM_BASE);
|
769 |
|
|
ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
|
770 |
|
|
PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT)));
|
771 |
|
|
|
772 |
|
|
//
|
773 |
|
|
// Read the module's FAULT output control register, and set or clear
|
774 |
|
|
// the requested bits.
|
775 |
|
|
//
|
776 |
|
|
if(bFaultKill == true)
|
777 |
|
|
{
|
778 |
|
|
HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits;
|
779 |
|
|
}
|
780 |
|
|
else
|
781 |
|
|
{
|
782 |
|
|
HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits);
|
783 |
|
|
}
|
784 |
|
|
}
|
785 |
|
|
#endif
|
786 |
|
|
|
787 |
|
|
//*****************************************************************************
|
788 |
|
|
//
|
789 |
|
|
//! Registers an interrupt handler for the specified PWM generator block.
|
790 |
|
|
//!
|
791 |
|
|
//! \param ulBase is the base address of the PWM module.
|
792 |
|
|
//! \param ulGen is the PWM generator in question.
|
793 |
|
|
//! \param pfnIntHandler is a pointer to the function to be called when the PWM
|
794 |
|
|
//! generator interrupt occurs.
|
795 |
|
|
//!
|
796 |
|
|
//! This function will ensure that the interrupt handler specified by
|
797 |
|
|
//! \e pfnIntHandler is called when an interrupt is detected for the specified
|
798 |
|
|
//! PWM generator block. This function will also enable the corresponding
|
799 |
|
|
//! PWM generator interrupt in the interrupt controller; individual generator
|
800 |
|
|
//! interrupts and interrupt sources must be enabled with PWMIntEnable() and
|
801 |
|
|
//! PWMGenIntTrigEnable().
|
802 |
|
|
//!
|
803 |
|
|
//! \sa IntRegister() for important information about registering interrupt
|
804 |
|
|
//! handlers.
|
805 |
|
|
//!
|
806 |
|
|
//! \return None.
|
807 |
|
|
//
|
808 |
|
|
//*****************************************************************************
|
809 |
|
|
#if defined(GROUP_genintregister) || defined(BUILD_ALL) || defined(DOXYGEN)
|
810 |
|
|
void
|
811 |
|
|
PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
|
812 |
|
|
void (*pfnIntHandler)(void))
|
813 |
|
|
{
|
814 |
|
|
unsigned long ulInt;
|
815 |
|
|
|
816 |
|
|
//
|
817 |
|
|
// Check the arguments.
|
818 |
|
|
//
|
819 |
|
|
ASSERT(ulBase == PWM_BASE);
|
820 |
|
|
ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
|
821 |
|
|
(ulGen == PWM_GEN_2));
|
822 |
|
|
|
823 |
|
|
//
|
824 |
|
|
// Get the interrupt number associated with the specified generator.
|
825 |
|
|
//
|
826 |
|
|
ulInt = INT_PWM0 + (ulGen >> 6) - 1;
|
827 |
|
|
|
828 |
|
|
//
|
829 |
|
|
// Register the interrupt handler.
|
830 |
|
|
//
|
831 |
|
|
IntRegister(ulInt, pfnIntHandler);
|
832 |
|
|
|
833 |
|
|
//
|
834 |
|
|
// Enable the PWMx interrupt.
|
835 |
|
|
//
|
836 |
|
|
IntEnable(ulInt);
|
837 |
|
|
}
|
838 |
|
|
#endif
|
839 |
|
|
|
840 |
|
|
//*****************************************************************************
|
841 |
|
|
//
|
842 |
|
|
//! Removes an interrupt handler for the specified PWM generator block.
|
843 |
|
|
//!
|
844 |
|
|
//! \param ulBase is the base address of the PWM module.
|
845 |
|
|
//! \param ulGen is the PWM generator in question.
|
846 |
|
|
//!
|
847 |
|
|
//! This function will unregister the interrupt handler for the specified
|
848 |
|
|
//! PWM generator block. This function will also disable the corresponding
|
849 |
|
|
//! PWM generator interrupt in the interrupt controller; individual generator
|
850 |
|
|
//! interrupts and interrupt sources must be disabled with PWMIntDisable() and
|
851 |
|
|
//! PWMGenIntTrigDisable().
|
852 |
|
|
//!
|
853 |
|
|
//! \sa IntRegister() for important information about registering interrupt
|
854 |
|
|
//! handlers.
|
855 |
|
|
//!
|
856 |
|
|
//! \return None.
|
857 |
|
|
//
|
858 |
|
|
//*****************************************************************************
|
859 |
|
|
#if defined(GROUP_genintunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
|
860 |
|
|
void
|
861 |
|
|
PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen)
|
862 |
|
|
{
|
863 |
|
|
unsigned long ulInt;
|
864 |
|
|
|
865 |
|
|
//
|
866 |
|
|
// Check the arguments.
|
867 |
|
|
//
|
868 |
|
|
ASSERT(ulBase == PWM_BASE);
|
869 |
|
|
ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
|
870 |
|
|
(ulGen == PWM_GEN_2));
|
871 |
|
|
|
872 |
|
|
//
|
873 |
|
|
// Get the interrupt number associated with the specified generator.
|
874 |
|
|
//
|
875 |
|
|
ulInt = INT_PWM0 + (ulGen >> 6) - 1;
|
876 |
|
|
|
877 |
|
|
//
|
878 |
|
|
// Disable the PWMx interrupt.
|
879 |
|
|
//
|
880 |
|
|
IntDisable(ulInt);
|
881 |
|
|
|
882 |
|
|
//
|
883 |
|
|
// Unregister the interrupt handler.
|
884 |
|
|
//
|
885 |
|
|
IntUnregister(ulInt);
|
886 |
|
|
}
|
887 |
|
|
#endif
|
888 |
|
|
|
889 |
|
|
//*****************************************************************************
|
890 |
|
|
//
|
891 |
|
|
//! Registers an interrupt handler for a fault condition detected in a PWM
|
892 |
|
|
//! module.
|
893 |
|
|
//!
|
894 |
|
|
//! \param ulBase is the base address of the PWM module.
|
895 |
|
|
//! \param pfnIntHandler is a pointer to the function to be called when the PWM
|
896 |
|
|
//! fault interrupt occurs.
|
897 |
|
|
//!
|
898 |
|
|
//! This function will ensure that the interrupt handler specified by
|
899 |
|
|
//! \e pfnIntHandler is called when a fault interrupt is detected for the
|
900 |
|
|
//! selected PWM module. This function will also enable the PWM fault
|
901 |
|
|
//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the
|
902 |
|
|
//! module level using PWMIntEnable().
|
903 |
|
|
//!
|
904 |
|
|
//! \sa IntRegister() for important information about registering interrupt
|
905 |
|
|
//! handlers.
|
906 |
|
|
//!
|
907 |
|
|
//! \return None.
|
908 |
|
|
//
|
909 |
|
|
//*****************************************************************************
|
910 |
|
|
#if defined(GROUP_faultintregister) || defined(BUILD_ALL) || defined(DOXYGEN)
|
911 |
|
|
void
|
912 |
|
|
PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void))
|
913 |
|
|
{
|
914 |
|
|
//
|
915 |
|
|
// Check the arguments.
|
916 |
|
|
//
|
917 |
|
|
ASSERT(ulBase == PWM_BASE);
|
918 |
|
|
|
919 |
|
|
//
|
920 |
|
|
// Register the interrupt handler, returning an error if one occurs.
|
921 |
|
|
//
|
922 |
|
|
IntRegister(INT_PWM_FAULT, pfnIntHandler);
|
923 |
|
|
|
924 |
|
|
//
|
925 |
|
|
// Enable the PWM fault interrupt.
|
926 |
|
|
//
|
927 |
|
|
IntEnable(INT_PWM_FAULT);
|
928 |
|
|
}
|
929 |
|
|
#endif
|
930 |
|
|
|
931 |
|
|
//*****************************************************************************
|
932 |
|
|
//
|
933 |
|
|
//! Removes the PWM fault condition interrupt handler.
|
934 |
|
|
//!
|
935 |
|
|
//! \param ulBase is the base address of the PWM module.
|
936 |
|
|
//!
|
937 |
|
|
//! This function will remove the interrupt handler for a PWM fault interrupt
|
938 |
|
|
//! from the selected PWM module. This function will also disable the PWM
|
939 |
|
|
//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled
|
940 |
|
|
//! at the module level using PWMIntDisable().
|
941 |
|
|
//!
|
942 |
|
|
//! \sa IntRegister() for important information about registering interrupt
|
943 |
|
|
//! handlers.
|
944 |
|
|
//!
|
945 |
|
|
//! \return None.
|
946 |
|
|
//
|
947 |
|
|
//*****************************************************************************
|
948 |
|
|
#if defined(GROUP_faultintunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
|
949 |
|
|
void
|
950 |
|
|
PWMFaultIntUnregister(unsigned long ulBase)
|
951 |
|
|
{
|
952 |
|
|
//
|
953 |
|
|
// Check the arguments.
|
954 |
|
|
//
|
955 |
|
|
ASSERT(ulBase == PWM_BASE);
|
956 |
|
|
|
957 |
|
|
//
|
958 |
|
|
// Disable the PWM fault interrupt.
|
959 |
|
|
//
|
960 |
|
|
IntDisable(INT_PWM_FAULT);
|
961 |
|
|
|
962 |
|
|
//
|
963 |
|
|
// Unregister the interrupt handler, returning an error if one occurs.
|
964 |
|
|
//
|
965 |
|
|
IntUnregister(INT_PWM_FAULT);
|
966 |
|
|
}
|
967 |
|
|
#endif
|
968 |
|
|
|
969 |
|
|
//*****************************************************************************
|
970 |
|
|
//
|
971 |
|
|
//! Enables interrupts and triggers for the specified PWM generator block.
|
972 |
|
|
//!
|
973 |
|
|
//! \param ulBase is the base address of the PWM module.
|
974 |
|
|
//! \param ulGen is the PWM generator to have interrupts and triggers enabled.
|
975 |
|
|
//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
|
976 |
|
|
//! \param ulIntTrig specifies the interrupts and triggers to be enabled.
|
977 |
|
|
//!
|
978 |
|
|
//! Unmasks the specified interrupt(s) and trigger(s) by setting the
|
979 |
|
|
//! specified bits of the interrupt/trigger enable register for the specified
|
980 |
|
|
//! PWM generator. The defined values for the bits are as follows:
|
981 |
|
|
//!
|
982 |
|
|
//! - PWM_INT_CNT_ZERO
|
983 |
|
|
//! - PWM_INT_CNT_LOAD
|
984 |
|
|
//! - PWM_INT_CMP_AU
|
985 |
|
|
//! - PWM_INT_CMP_AD
|
986 |
|
|
//! - PWM_INT_CMP_BU
|
987 |
|
|
//! - PWM_INT_CMP_BD
|
988 |
|
|
//! - PWM_TR_CNT_ZERO
|
989 |
|
|
//! - PWM_TR_CNT_LOAD
|
990 |
|
|
//! - PWM_TR_CMP_AU
|
991 |
|
|
//! - PWM_TR_CMP_AD
|
992 |
|
|
//! - PWM_TR_CMP_BU
|
993 |
|
|
//! - PWM_TR_CMP_BD
|
994 |
|
|
//!
|
995 |
|
|
//! \return None.
|
996 |
|
|
//
|
997 |
|
|
//*****************************************************************************
|
998 |
|
|
#if defined(GROUP_geninttrigenable) || defined(BUILD_ALL) || defined(DOXYGEN)
|
999 |
|
|
void
|
1000 |
|
|
PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
|
1001 |
|
|
unsigned long ulIntTrig)
|
1002 |
|
|
{
|
1003 |
|
|
//
|
1004 |
|
|
// Check the arguments.
|
1005 |
|
|
//
|
1006 |
|
|
ASSERT(ulBase == PWM_BASE);
|
1007 |
|
|
ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
|
1008 |
|
|
(ulGen == PWM_GEN_2));
|
1009 |
|
|
|
1010 |
|
|
//
|
1011 |
|
|
// Enable the specified interrupts/triggers.
|
1012 |
|
|
//
|
1013 |
|
|
HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig;
|
1014 |
|
|
}
|
1015 |
|
|
#endif
|
1016 |
|
|
|
1017 |
|
|
//*****************************************************************************
|
1018 |
|
|
//
|
1019 |
|
|
//! Disables interrupts for the specified PWM generator block.
|
1020 |
|
|
//!
|
1021 |
|
|
//! \param ulBase is the base address of the PWM module.
|
1022 |
|
|
//! \param ulGen is the PWM generator to have interrupts and triggers disabled.
|
1023 |
|
|
//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
|
1024 |
|
|
//! \param ulIntTrig specifies the interrupts and triggers to be disabled.
|
1025 |
|
|
//!
|
1026 |
|
|
//! Masks the specified interrupt(s) and trigger(s) by clearing the
|
1027 |
|
|
//! specified bits of the interrupt/trigger enable register for the specified
|
1028 |
|
|
//! PWM generator. The defined values for the bits are as follows:
|
1029 |
|
|
//!
|
1030 |
|
|
//! - PWM_INT_CNT_ZERO
|
1031 |
|
|
//! - PWM_INT_CNT_LOAD
|
1032 |
|
|
//! - PWM_INT_CMP_AU
|
1033 |
|
|
//! - PWM_INT_CMP_AD
|
1034 |
|
|
//! - PWM_INT_CMP_BU
|
1035 |
|
|
//! - PWM_INT_CMP_BD
|
1036 |
|
|
//! - PWM_TR_CNT_ZERO
|
1037 |
|
|
//! - PWM_TR_CNT_LOAD
|
1038 |
|
|
//! - PWM_TR_CMP_AU
|
1039 |
|
|
//! - PWM_TR_CMP_AD
|
1040 |
|
|
//! - PWM_TR_CMP_BU
|
1041 |
|
|
//! - PWM_TR_CMP_BD
|
1042 |
|
|
//!
|
1043 |
|
|
//! \return None.
|
1044 |
|
|
//
|
1045 |
|
|
//*****************************************************************************
|
1046 |
|
|
#if defined(GROUP_geninttrigdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
|
1047 |
|
|
void
|
1048 |
|
|
PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
|
1049 |
|
|
unsigned long ulIntTrig)
|
1050 |
|
|
{
|
1051 |
|
|
//
|
1052 |
|
|
// Check the arguments.
|
1053 |
|
|
//
|
1054 |
|
|
ASSERT(ulBase == PWM_BASE);
|
1055 |
|
|
ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
|
1056 |
|
|
(ulGen == PWM_GEN_2));
|
1057 |
|
|
|
1058 |
|
|
//
|
1059 |
|
|
// Disable the specified interrupts/triggers.
|
1060 |
|
|
//
|
1061 |
|
|
HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig);
|
1062 |
|
|
}
|
1063 |
|
|
#endif
|
1064 |
|
|
|
1065 |
|
|
//*****************************************************************************
|
1066 |
|
|
//
|
1067 |
|
|
//! Gets interrupt status for the specified PWM generator block.
|
1068 |
|
|
//!
|
1069 |
|
|
//! \param ulBase is the base address of the PWM module.
|
1070 |
|
|
//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
|
1071 |
|
|
//! \b PWM_GEN_1, or \b PWM_GEN_2.
|
1072 |
|
|
//! \param bMasked specifies whether masked or raw interrupt status is
|
1073 |
|
|
//! returned.
|
1074 |
|
|
//!
|
1075 |
|
|
//! If \e bMasked is set as \b true, then the masked interrupt status is
|
1076 |
|
|
//! returned; otherwise, the raw interrupt status will be returned.
|
1077 |
|
|
//!
|
1078 |
|
|
//! \return Returns the contents of the interrupt status register, or the
|
1079 |
|
|
//! contents of the raw interrupt status register, for the specified
|
1080 |
|
|
//! PWM generator.
|
1081 |
|
|
//
|
1082 |
|
|
//*****************************************************************************
|
1083 |
|
|
#if defined(GROUP_genintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
|
1084 |
|
|
unsigned long
|
1085 |
|
|
PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked)
|
1086 |
|
|
{
|
1087 |
|
|
//
|
1088 |
|
|
// Check the arguments.
|
1089 |
|
|
//
|
1090 |
|
|
ASSERT(ulBase == PWM_BASE);
|
1091 |
|
|
ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
|
1092 |
|
|
(ulGen == PWM_GEN_2));
|
1093 |
|
|
|
1094 |
|
|
//
|
1095 |
|
|
// Compute the generator's base address.
|
1096 |
|
|
//
|
1097 |
|
|
ulGen = PWM_GEN_BADDR(ulBase, ulGen);
|
1098 |
|
|
|
1099 |
|
|
//
|
1100 |
|
|
// Read and return the specified generator's raw or enabled interrupt
|
1101 |
|
|
// status.
|
1102 |
|
|
//
|
1103 |
|
|
if(bMasked == true)
|
1104 |
|
|
{
|
1105 |
|
|
return(HWREG(ulGen + PWM_O_X_ISC));
|
1106 |
|
|
}
|
1107 |
|
|
else
|
1108 |
|
|
{
|
1109 |
|
|
return(HWREG(ulGen + PWM_O_X_RIS));
|
1110 |
|
|
}
|
1111 |
|
|
}
|
1112 |
|
|
#endif
|
1113 |
|
|
|
1114 |
|
|
//*****************************************************************************
|
1115 |
|
|
//
|
1116 |
|
|
//! Clears the specified interrupt(s) for the specified PWM generator block.
|
1117 |
|
|
//!
|
1118 |
|
|
//! \param ulBase is the base address of the PWM module.
|
1119 |
|
|
//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
|
1120 |
|
|
//! \b PWM_GEN_1, or \b PWM_GEN_2.
|
1121 |
|
|
//! \param ulInts specifies the interrupts to be cleared.
|
1122 |
|
|
//!
|
1123 |
|
|
//! Clears the specified interrupt(s) by writing a 1 to the specified bits
|
1124 |
|
|
//! of the interrupt status register for the specified PWM generator. The
|
1125 |
|
|
//! defined values for the bits are as follows:
|
1126 |
|
|
//!
|
1127 |
|
|
//! - PWM_INT_CNT_ZERO
|
1128 |
|
|
//! - PWM_INT_CNT_LOAD
|
1129 |
|
|
//! - PWM_INT_CMP_AU
|
1130 |
|
|
//! - PWM_INT_CMP_AD
|
1131 |
|
|
//! - PWM_INT_CMP_BU
|
1132 |
|
|
//! - PWM_INT_CMP_BD
|
1133 |
|
|
//!
|
1134 |
|
|
//! \return None.
|
1135 |
|
|
//
|
1136 |
|
|
//*****************************************************************************
|
1137 |
|
|
#if defined(GROUP_genintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
|
1138 |
|
|
void
|
1139 |
|
|
PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts)
|
1140 |
|
|
{
|
1141 |
|
|
//
|
1142 |
|
|
// Check the arguments.
|
1143 |
|
|
//
|
1144 |
|
|
ASSERT(ulBase == PWM_BASE);
|
1145 |
|
|
ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
|
1146 |
|
|
(ulGen == PWM_GEN_2));
|
1147 |
|
|
|
1148 |
|
|
//
|
1149 |
|
|
// Clear the requested interrupts by writing ones to the specified bit
|
1150 |
|
|
// of the module's interrupt enable register.
|
1151 |
|
|
//
|
1152 |
|
|
HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts;
|
1153 |
|
|
}
|
1154 |
|
|
#endif
|
1155 |
|
|
|
1156 |
|
|
//*****************************************************************************
|
1157 |
|
|
//
|
1158 |
|
|
//! Enables generator and fault interrupts for a PWM module.
|
1159 |
|
|
//!
|
1160 |
|
|
//! \param ulBase is the base address of the PWM module.
|
1161 |
|
|
//! \param ulGenFault contains the interrupts to be enabled. Must be a logical
|
1162 |
|
|
//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, or
|
1163 |
|
|
//! \b PWM_INT_FAULT.
|
1164 |
|
|
//!
|
1165 |
|
|
//! Unmasks the specified interrupt(s) by setting the specified bits of
|
1166 |
|
|
//! the interrupt enable register for the selected PWM module.
|
1167 |
|
|
//!
|
1168 |
|
|
//! \return None.
|
1169 |
|
|
//
|
1170 |
|
|
//*****************************************************************************
|
1171 |
|
|
#if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
|
1172 |
|
|
void
|
1173 |
|
|
PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault)
|
1174 |
|
|
{
|
1175 |
|
|
//
|
1176 |
|
|
// Check the arguments.
|
1177 |
|
|
//
|
1178 |
|
|
ASSERT(ulBase == PWM_BASE);
|
1179 |
|
|
|
1180 |
|
|
//
|
1181 |
|
|
// Read the module's interrupt enable register, and enable interrupts
|
1182 |
|
|
// for the specified PWM generators.
|
1183 |
|
|
//
|
1184 |
|
|
HWREG(ulBase + PWM_O_INTEN) |= ulGenFault;
|
1185 |
|
|
}
|
1186 |
|
|
#endif
|
1187 |
|
|
|
1188 |
|
|
//*****************************************************************************
|
1189 |
|
|
//
|
1190 |
|
|
//! Disables generator and fault interrupts for a PWM module.
|
1191 |
|
|
//!
|
1192 |
|
|
//! \param ulBase is the base address of the PWM module.
|
1193 |
|
|
//! \param ulGenFault contains the interrupts to be disabled. Must be a
|
1194 |
|
|
//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
|
1195 |
|
|
//! or \b PWM_INT_FAULT.
|
1196 |
|
|
//!
|
1197 |
|
|
//! Masks the specified interrupt(s) by clearing the specified bits of
|
1198 |
|
|
//! the interrupt enable register for the selected PWM module.
|
1199 |
|
|
//!
|
1200 |
|
|
//! \return None.
|
1201 |
|
|
//
|
1202 |
|
|
//*****************************************************************************
|
1203 |
|
|
#if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
|
1204 |
|
|
void
|
1205 |
|
|
PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault)
|
1206 |
|
|
{
|
1207 |
|
|
//
|
1208 |
|
|
// Check the arguments.
|
1209 |
|
|
//
|
1210 |
|
|
ASSERT(ulBase == PWM_BASE);
|
1211 |
|
|
|
1212 |
|
|
//
|
1213 |
|
|
// Read the module's interrupt enable register, and disable interrupts
|
1214 |
|
|
// for the specified PWM generators.
|
1215 |
|
|
//
|
1216 |
|
|
HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault);
|
1217 |
|
|
}
|
1218 |
|
|
#endif
|
1219 |
|
|
|
1220 |
|
|
//*****************************************************************************
|
1221 |
|
|
//
|
1222 |
|
|
//! Clears the fault interrupt for a PWM module.
|
1223 |
|
|
//!
|
1224 |
|
|
//! \param ulBase is the base address of the PWM module.
|
1225 |
|
|
//!
|
1226 |
|
|
//! Clears the fault interrupt by writing to the appropriate bit of the
|
1227 |
|
|
//! interrupt status register for the selected PWM module.
|
1228 |
|
|
//!
|
1229 |
|
|
//! \return None.
|
1230 |
|
|
//
|
1231 |
|
|
//*****************************************************************************
|
1232 |
|
|
#if defined(GROUP_faultintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
|
1233 |
|
|
void
|
1234 |
|
|
PWMFaultIntClear(unsigned long ulBase)
|
1235 |
|
|
{
|
1236 |
|
|
//
|
1237 |
|
|
// Check the arguments.
|
1238 |
|
|
//
|
1239 |
|
|
ASSERT(ulBase == PWM_BASE);
|
1240 |
|
|
|
1241 |
|
|
//
|
1242 |
|
|
// Write the only writeable bit in the module's interrupt register.
|
1243 |
|
|
//
|
1244 |
|
|
HWREG(ulBase + PWM_O_ISC) = PWM_INT_INTFAULT;
|
1245 |
|
|
}
|
1246 |
|
|
#endif
|
1247 |
|
|
|
1248 |
|
|
//*****************************************************************************
|
1249 |
|
|
//
|
1250 |
|
|
//! Gets the interrupt status for a PWM module.
|
1251 |
|
|
//!
|
1252 |
|
|
//! \param ulBase is the base address of the PWM module.
|
1253 |
|
|
//! \param bMasked specifies whether masked or raw interrupt status is
|
1254 |
|
|
//! returned.
|
1255 |
|
|
//!
|
1256 |
|
|
//! If \e bMasked is set as \b true, then the masked interrupt status is
|
1257 |
|
|
//! returned; otherwise, the raw interrupt status will be returned.
|
1258 |
|
|
//!
|
1259 |
|
|
//! \return The current interrupt status, enumerated as a bit field of
|
1260 |
|
|
//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, and \b PWM_INT_FAULT.
|
1261 |
|
|
//!
|
1262 |
|
|
//*****************************************************************************
|
1263 |
|
|
#if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
|
1264 |
|
|
unsigned long
|
1265 |
|
|
PWMIntStatus(unsigned long ulBase, tBoolean bMasked)
|
1266 |
|
|
{
|
1267 |
|
|
//
|
1268 |
|
|
// Check the arguments.
|
1269 |
|
|
//
|
1270 |
|
|
ASSERT(ulBase == PWM_BASE);
|
1271 |
|
|
|
1272 |
|
|
//
|
1273 |
|
|
// Read and return either the module's raw or enabled interrupt status.
|
1274 |
|
|
//
|
1275 |
|
|
if(bMasked == true)
|
1276 |
|
|
{
|
1277 |
|
|
return(HWREG(ulBase + PWM_O_ISC));
|
1278 |
|
|
}
|
1279 |
|
|
else
|
1280 |
|
|
{
|
1281 |
|
|
return(HWREG(ulBase + PWM_O_RIS));
|
1282 |
|
|
}
|
1283 |
|
|
}
|
1284 |
|
|
#endif
|
1285 |
|
|
|
1286 |
|
|
//*****************************************************************************
|
1287 |
|
|
//
|
1288 |
|
|
// Close the Doxygen group.
|
1289 |
|
|
//! @}
|
1290 |
|
|
//
|
1291 |
|
|
//*****************************************************************************
|