OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_IAR/] [startup.c] - Blame information for rev 860

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 581 jeremybenn
//*****************************************************************************
2
//
3
// startup_ewarm.c - Boot code for Stellaris.
4
//
5
// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
6
//
7
// Software License Agreement
8
//
9
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10
// exclusively on LMI's Stellaris Family of microcontroller products.
11
//
12
// The software is owned by LMI and/or its suppliers, and is protected under
13
// applicable copyright laws.  All rights are reserved.  Any use in violation
14
// of the foregoing restrictions may subject the user to criminal sanctions
15
// under applicable laws, as well as to civil liability for the breach of the
16
// terms and conditions of this license.
17
//
18
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
22
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23
//
24
// This is part of revision 991 of the Stellaris Driver Library.
25
//
26
//*****************************************************************************
27
 
28
//*****************************************************************************
29
//
30
// Enable the IAR extensions for this source file.
31
//
32
//*****************************************************************************
33
#pragma language=extended
34
 
35
//*****************************************************************************
36
//
37
// Forward declaration of the default fault handlers.
38
//
39
//*****************************************************************************
40
static void NmiSR(void);
41
static void FaultISR(void);
42
static void IntDefaultHandler(void);
43
 
44
//*****************************************************************************
45
//
46
// The entry point for the application.
47
//
48
//*****************************************************************************
49
extern void __iar_program_start(void);
50
 
51
//*****************************************************************************
52
//
53
// External declaration for the interrupt handler used by the application.
54
//
55
//*****************************************************************************
56
extern void xPortPendSVHandler(void);
57
extern void xPortSysTickHandler(void);
58
extern void vGPIO_ISR(void);
59
extern void vUART_ISR(void);
60
extern void vPortSVCHandler( void );
61
 
62
//*****************************************************************************
63
//
64
// Reserve space for the system stack.
65
//
66
//*****************************************************************************
67
#ifndef STACK_SIZE
68
#define STACK_SIZE                              64
69
#endif
70
static unsigned long pulStack[STACK_SIZE] @ ".noinit";
71
 
72
//*****************************************************************************
73
//
74
// A union that describes the entries of the vector table.  The union is needed
75
// since the first entry is the stack pointer and the remainder are function
76
// pointers.
77
//
78
//*****************************************************************************
79
typedef union
80
{
81
    void (*pfnHandler)(void);
82
    unsigned long ulPtr;
83
}
84
uVectorEntry;
85
 
86
//*****************************************************************************
87
//
88
// The minimal vector table for a Cortex M3.  Note that the proper constructs
89
// must be placed on this to ensure that it ends up at physical address
90
// 0x0000.0000.
91
//
92
//*****************************************************************************
93
__root const uVectorEntry __vector_table[] @ ".intvec" =
94
{
95
    { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) },
96
                                            // The initial stack pointer
97
    __iar_program_start,                    // The reset handler
98
    NmiSR,                                  // The NMI handler
99
    FaultISR,                               // The hard fault handler
100
    IntDefaultHandler,                      // The MPU fault handler
101
    IntDefaultHandler,                      // The bus fault handler
102
    IntDefaultHandler,                      // The usage fault handler
103
    0,                                      // Reserved
104
    0,                                      // Reserved
105
    0,                                      // Reserved
106
    0,                                      // Reserved
107
    vPortSVCHandler,                        // SVCall handler
108
    IntDefaultHandler,                      // Debug monitor handler
109
    0,                                      // Reserved
110
    xPortPendSVHandler,                     // The PendSV handler
111
    xPortSysTickHandler,                    // The SysTick handler
112
    IntDefaultHandler,                      // GPIO Port A
113
    IntDefaultHandler,                      // GPIO Port B
114
    vGPIO_ISR,                              // GPIO Port C
115
    IntDefaultHandler,                      // GPIO Port D
116
    IntDefaultHandler,                      // GPIO Port E
117
    vUART_ISR,                              // UART0 Rx and Tx
118
    IntDefaultHandler,                      // UART1 Rx and Tx
119
    IntDefaultHandler,                      // SSI Rx and Tx
120
    IntDefaultHandler,                      // I2C Master and Slave
121
    IntDefaultHandler,                      // PWM Fault
122
    IntDefaultHandler,                      // PWM Generator 0
123
    IntDefaultHandler,                      // PWM Generator 1
124
    IntDefaultHandler,                      // PWM Generator 2
125
    IntDefaultHandler,                      // Quadrature Encoder
126
    IntDefaultHandler,                      // ADC Sequence 0
127
    IntDefaultHandler,                      // ADC Sequence 1
128
    IntDefaultHandler,                      // ADC Sequence 2
129
    IntDefaultHandler,                      // ADC Sequence 3
130
    IntDefaultHandler,                      // Watchdog timer
131
    IntDefaultHandler,                      // Timer 0 subtimer A
132
    IntDefaultHandler,                      // Timer 0 subtimer B
133
    IntDefaultHandler,                      // Timer 1 subtimer A
134
    IntDefaultHandler,                      // Timer 1 subtimer B
135
    IntDefaultHandler,                      // Timer 2 subtimer A
136
    IntDefaultHandler,                      // Timer 2 subtimer B
137
    IntDefaultHandler,                      // Analog Comparator 0
138
    IntDefaultHandler,                      // Analog Comparator 1
139
    IntDefaultHandler,                      // Analog Comparator 2
140
    IntDefaultHandler,                      // System Control (PLL, OSC, BO)
141
    IntDefaultHandler                       // FLASH Control
142
};
143
 
144
 
145
//*****************************************************************************
146
//
147
// This is the code that gets called when the processor receives a NMI.  This
148
// simply enters an infinite loop, preserving the system state for examination
149
// by a debugger.
150
//
151
//*****************************************************************************
152
static void
153
NmiSR(void)
154
{
155
    //
156
    // Enter an infinite loop.
157
    //
158
    while(1)
159
    {
160
    }
161
}
162
 
163
//*****************************************************************************
164
//
165
// This is the code that gets called when the processor receives a fault
166
// interrupt.  This simply enters an infinite loop, preserving the system state
167
// for examination by a debugger.
168
//
169
//*****************************************************************************
170
static void
171
FaultISR(void)
172
{
173
    //
174
    // Enter an infinite loop.
175
    //
176
    while(1)
177
    {
178
    }
179
}
180
 
181
//*****************************************************************************
182
//
183
// This is the code that gets called when the processor receives an unexpected
184
// interrupt.  This simply enters an infinite loop, preserving the system state
185
// for examination by a debugger.
186
//
187
//*****************************************************************************
188
static void
189
IntDefaultHandler(void)
190
{
191
    //
192
    // Go into an infinite loop.
193
    //
194
    while(1)
195
    {
196
    }
197
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.