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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_KEIL/] [LuminaryCode/] [hw_i2c.h] - Blame information for rev 581

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1 581 jeremybenn
//*****************************************************************************
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//
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// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
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//
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// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's Stellaris Family of microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws.  All rights are reserved.  Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 816 of the Stellaris Driver Library.
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//
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//*****************************************************************************
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#ifndef __HW_I2C_H__
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#define __HW_I2C_H__
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//*****************************************************************************
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//
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// The following defines the offset between the I2C master and slave registers.
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//
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//*****************************************************************************
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#define I2C_O_SLAVE             0x00000800  // Offset from master to slave
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//*****************************************************************************
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//
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// The following define the offsets of the I2C master registers.
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//
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//*****************************************************************************
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#define I2C_MASTER_O_SA         0x00000000  // Slave address register
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#define I2C_MASTER_O_CS         0x00000004  // Control and Status register
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#define I2C_MASTER_O_DR         0x00000008  // Data register
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#define I2C_MASTER_O_TPR        0x0000000C  // Timer period register
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#define I2C_MASTER_O_IMR        0x00000010  // Interrupt mask register
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#define I2C_MASTER_O_RIS        0x00000014  // Raw interrupt status register
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#define I2C_MASTER_O_MIS        0x00000018  // Masked interrupt status reg
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#define I2C_MASTER_O_MICR       0x0000001c  // Interrupt clear register
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#define I2C_MASTER_O_CR         0x00000020  // Configuration register
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//*****************************************************************************
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//
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// The following define the offsets of the I2C slave registers.
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//
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//*****************************************************************************
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#define I2C_SLAVE_O_OAR         0x00000000  // Own address register
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#define I2C_SLAVE_O_CSR         0x00000004  // Control/Status register
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#define I2C_SLAVE_O_DR          0x00000008  // Data register
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#define I2C_SLAVE_O_IM          0x0000000C  // Interrupt mask register
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#define I2C_SLAVE_O_RIS         0x00000010  // Raw interrupt status register
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#define I2C_SLAVE_O_MIS         0x00000014  // Masked interrupt status reg
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#define I2C_SLAVE_O_SICR        0x00000018  // Interrupt clear register
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//*****************************************************************************
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//
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// The followng define the bit fields in the I2C master slave address register.
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//
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//*****************************************************************************
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#define I2C_MASTER_SA_SA_MASK   0x000000FE  // Slave address
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#define I2C_MASTER_SA_RS        0x00000001  // Receive/send
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#define I2C_MASTER_SA_SA_SHIFT  1
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Master Control and Status
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// register.
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//
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//*****************************************************************************
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#define I2C_MASTER_CS_ACK       0x00000008  // Acknowlegde
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#define I2C_MASTER_CS_STOP      0x00000004  // Stop
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#define I2C_MASTER_CS_START     0x00000002  // Start
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#define I2C_MASTER_CS_RUN       0x00000001  // Run
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#define I2C_MASTER_CS_BUS_BUSY  0x00000040  // Bus busy
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#define I2C_MASTER_CS_IDLE      0x00000020  // Idle
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#define I2C_MASTER_CS_ARB_LOST  0x00000010  // Lost arbitration
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#define I2C_MASTER_CS_DATA_ACK  0x00000008  // Data byte not acknowledged
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#define I2C_MASTER_CS_ADDR_ACK  0x00000004  // Address byte not acknowledged
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#define I2C_MASTER_CS_ERROR     0x00000002  // Error occurred
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#define I2C_MASTER_CS_BUSY      0x00000001  // Controller is TX/RX data
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#define I2C_MASTER_CS_ERR_MASK  0x0000001C
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//*****************************************************************************
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//
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// The following define values used in determining the contents of the I2C
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// Master Timer Period register.
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//
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//*****************************************************************************
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#define I2C_MASTER_TPR_SCL_HP   0x00000004  // SCL high period
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#define I2C_MASTER_TPR_SCL_LP   0x00000006  // SCL low period
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#define I2C_MASTER_TPR_SCL      (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
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#define I2C_SCL_STANDARD        100000      // SCL standard frequency
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#define I2C_SCL_FAST            400000      // SCL fast frequency
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Master Interrupt Mask
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// register.
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//
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//*****************************************************************************
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#define I2C_MASTER_IMR_IM       0x00000001  // Master interrupt mask
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Master Raw Interrupt Status
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// register.
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//
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//*****************************************************************************
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#define I2C_MASTER_RIS_RIS      0x00000001  // Master raw interrupt status
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Master Masked Interrupt
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// Status register.
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//
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//*****************************************************************************
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#define I2C_MASTER_MIS_MIS      0x00000001  // Master masked interrupt status
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Master Interrupt Clear
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// register.
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//
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//*****************************************************************************
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#define I2C_MASTER_MICR_IC      0x00000001  // Master interrupt clear
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Master Configuration
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// register.
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//
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//*****************************************************************************
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#define I2C_MASTER_CR_SFE       0x00000020  // Slave function enable
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#define I2C_MASTER_CR_MFE       0x00000010  // Master function enable
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#define I2C_MASTER_CR_LPBK      0x00000001  // Loopback enable
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Slave Own Address register.
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//
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//*****************************************************************************
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#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F  // Slave address
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Slave Control/Status
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// register.
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//
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//*****************************************************************************
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#define I2C_SLAVE_CSR_DA        0x00000001  // Enable the device
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#define I2C_SLAVE_CSR_TREQ      0x00000002  // Transmit request received
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#define I2C_SLAVE_CSR_RREQ      0x00000001  // Receive data from I2C master
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Slave Interrupt Mask
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// register.
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//
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//*****************************************************************************
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#define I2C_SLAVE_IMR_IM       0x00000001  // Slave interrupt mask
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Slave Raw Interrupt Status
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// register.
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//
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//*****************************************************************************
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#define I2C_SLAVE_RIS_RIS      0x00000001  // Slave raw interrupt status
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Slave Masked Interrupt
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// Status register.
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//
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//*****************************************************************************
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#define I2C_SLAVE_MIS_MIS      0x00000001  // Slave masked interrupt status
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//*****************************************************************************
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//
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// The following define the bit fields in the I2C Slave Interrupt Clear
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// register.
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//
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//*****************************************************************************
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#define I2C_SLAVE_SICR_IC      0x00000001  // Slave interrupt clear
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#endif // __HW_I2C_H__

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