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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_KEIL/] [LuminaryCode/] [hw_nvic.h] - Blame information for rev 675

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1 581 jeremybenn 
//*****************************************************************************
2 
//
3 
// hw_nvic.h - Macros used when accessing the NVIC hardware.
4 
//
5 
// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
6 
//
7 
// Software License Agreement
8 
//
9 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10 
// exclusively on LMI's Stellaris Family of microcontroller products.
11 
//
12 
// The software is owned by LMI and/or its suppliers, and is protected under
13 
// applicable copyright laws.  All rights are reserved.  Any use in violation
14 
// of the foregoing restrictions may subject the user to criminal sanctions
15 
// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
17 
//
18 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19 
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20 
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21 
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
22 
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23 
//
24 
// This is part of revision 816 of the Stellaris Driver Library.
25 
//
26 
//*****************************************************************************
27 
 
28 
#ifndef __HW_NVIC_H__
29 
#define __HW_NVIC_H__
30 
 
31 
//*****************************************************************************
32 
//
33 
// The following define the addresses of the NVIC registers.
34 
//
35 
//*****************************************************************************
36 
#define NVIC_INT_TYPE           0xE000E004  // Interrupt Controller Type Reg.
37 
#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status Reg.
38 
#define NVIC_ST_RELOAD          0xE000E014  // SysTick Reload Value Register
39 
#define NVIC_ST_CURRENT         0xE000E018  // SysTick Current Value Register
40 
#define NVIC_ST_CAL             0xE000E01C  // SysTick Calibration Value Reg.
41 
#define NVIC_EN0                0xE000E100  // IRQ 0 to 31 Set Enable Register
42 
#define NVIC_DIS0               0xE000E180  // IRQ 0 to 31 Clear Enable Reg.
43 
#define NVIC_PEND0              0xE000E200  // IRQ 0 to 31 Set Pending Register
44 
#define NVIC_UNPEND0            0xE000E280  // IRQ 0 to 31 Clear Pending Reg.
45 
#define NVIC_ACTIVE0            0xE000E300  // IRQ 0 to 31 Active Register
46 
#define NVIC_PRI0               0xE000E400  // IRQ 0 to 3 Priority Register
47 
#define NVIC_PRI1               0xE000E404  // IRQ 4 to 7 Priority Register
48 
#define NVIC_PRI2               0xE000E408  // IRQ 8 to 11 Priority Register
49 
#define NVIC_PRI3               0xE000E40C  // IRQ 12 to 15 Priority Register
50 
#define NVIC_PRI4               0xE000E410  // IRQ 16 to 19 Priority Register
51 
#define NVIC_PRI5               0xE000E414  // IRQ 20 to 23 Priority Register
52 
#define NVIC_PRI6               0xE000E418  // IRQ 24 to 27 Priority Register
53 
#define NVIC_PRI7               0xE000E41C  // IRQ 28 to 31 Priority Register
54 
#define NVIC_CPUID              0xE000ED00  // CPUID Base Register
55 
#define NVIC_INT_CTRL           0xE000ED04  // Interrupt Control State Register
56 
#define NVIC_VTABLE             0xE000ED08  // Vector Table Offset Register
57 
#define NVIC_APINT              0xE000ED0C  // App. Int & Reset Control Reg.
58 
#define NVIC_SYS_CTRL           0xE000ED10  // System Control Register
59 
#define NVIC_CFG_CTRL           0xE000ED14  // Configuration Control Register
60 
#define NVIC_SYS_PRI1           0xE000ED18  // Sys. Handlers 4 to 7 Priority
61 
#define NVIC_SYS_PRI2           0xE000ED1C  // Sys. Handlers 8 to 11 Priority
62 
#define NVIC_SYS_PRI3           0xE000ED20  // Sys. Handlers 12 to 15 Priority
63 
#define NVIC_SYS_HND_CTRL       0xE000ED24  // System Handler Control and State
64 
#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status Reg.
65 
#define NVIC_HFAULT_STAT        0xE000ED2C  // Hard Fault Status Register
66 
#define NVIC_DEBUG_STAT         0xE000ED30  // Debug Status Register
67 
#define NVIC_MM_ADDR            0xE000ED34  // Mem Manage Address Register
68 
#define NVIC_FAULT_ADDR         0xE000ED38  // Bus Fault Address Register
69 
#define NVIC_MPU_TYPE           0xE000ED90  // MPU Type Register
70 
#define NVIC_MPU_CTRL           0xE000ED94  // MPU Control Register
71 
#define NVIC_MPU_NUMBER         0xE000ED98  // MPU Region Number Register
72 
#define NVIC_MPU_BASE           0xE000ED9C  // MPU Region Base Address Register
73 
#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute & Size Reg.
74 
#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg.
75 
#define NVIC_DBG_XFER           0xE000EDF4  // Debug Core Reg. Transfer Select
76 
#define NVIC_DBG_DATA           0xE000EDF8  // Debug Core Register Data
77 
#define NVIC_DBG_INT            0xE000EDFC  // Debug Reset Interrupt Control
78 
#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt Reg.
79 
 
80 
//*****************************************************************************
81 
//
82 
// The following define the bit fields in the NVIC_INT_TYPE register.
83 
//
84 
//*****************************************************************************
85 
#define NVIC_INT_TYPE_LINES_M   0x0000001F  // Number of interrupt lines (x32)
86 
#define NVIC_INT_TYPE_LINES_S   0
87 
 
88 
//*****************************************************************************
89 
//
90 
// The following define the bit fields in the NVIC_ST_CTRL register.
91 
//
92 
//*****************************************************************************
93 
#define NVIC_ST_CTRL_COUNT      0x00010000  // Count flag
94 
#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
95 
#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt enable
96 
#define NVIC_ST_CTRL_ENABLE     0x00000001  // Counter mode
97 
 
98 
//*****************************************************************************
99 
//
100 
// The following define the bit fields in the NVIC_ST_RELOAD register.
101 
//
102 
//*****************************************************************************
103 
#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Counter load value
104 
#define NVIC_ST_RELOAD_S        0
105 
 
106 
//*****************************************************************************
107 
//
108 
// The following define the bit fields in the NVIC_ST_CURRENT register.
109 
//
110 
//*****************************************************************************
111 
#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Counter current value
112 
#define NVIC_ST_CURRENT_S       0
113 
 
114 
//*****************************************************************************
115 
//
116 
// The following define the bit fields in the NVIC_ST_CAL register.
117 
//
118 
//*****************************************************************************
119 
#define NVIC_ST_CAL_NOREF       0x80000000  // No reference clock
120 
#define NVIC_ST_CAL_SKEW        0x40000000  // Clock skew
121 
#define NVIC_ST_CAL_ONEMS_M     0x00FFFFFF  // 1ms reference value
122 
#define NVIC_ST_CAL_ONEMS_S     0
123 
 
124 
//*****************************************************************************
125 
//
126 
// The following define the bit fields in the NVIC_EN0 register.
127 
//
128 
//*****************************************************************************
129 
#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
130 
#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
131 
#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
132 
#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
133 
#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
134 
#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
135 
#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
136 
#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
137 
#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
138 
#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
139 
#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
140 
#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
141 
#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
142 
#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
143 
#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
144 
#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
145 
#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
146 
#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
147 
#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
148 
#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
149 
#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
150 
#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
151 
#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
152 
#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
153 
#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
154 
#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
155 
#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
156 
#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
157 
#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
158 
#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
159 
#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
160 
#define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
161 
 
162 
//*****************************************************************************
163 
//
164 
// The following define the bit fields in the NVIC_DIS0 register.
165 
//
166 
//*****************************************************************************
167 
#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
168 
#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
169 
#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
170 
#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
171 
#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
172 
#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
173 
#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
174 
#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
175 
#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
176 
#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
177 
#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
178 
#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
179 
#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
180 
#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
181 
#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
182 
#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
183 
#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
184 
#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
185 
#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
186 
#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
187 
#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
188 
#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
189 
#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
190 
#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
191 
#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
192 
#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
193 
#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
194 
#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
195 
#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
196 
#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
197 
#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
198 
#define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
199 
 
200 
//*****************************************************************************
201 
//
202 
// The following define the bit fields in the NVIC_PEND0 register.
203 
//
204 
//*****************************************************************************
205 
#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
206 
#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
207 
#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
208 
#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
209 
#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
210 
#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
211 
#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
212 
#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
213 
#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
214 
#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
215 
#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
216 
#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
217 
#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
218 
#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
219 
#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
220 
#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
221 
#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
222 
#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
223 
#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
224 
#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
225 
#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
226 
#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
227 
#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
228 
#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
229 
#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
230 
#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
231 
#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
232 
#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
233 
#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
234 
#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
235 
#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
236 
#define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
237 
 
238 
//*****************************************************************************
239 
//
240 
// The following define the bit fields in the NVIC_UNPEND0 register.
241 
//
242 
//*****************************************************************************
243 
#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
244 
#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
245 
#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
246 
#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
247 
#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
248 
#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
249 
#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
250 
#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
251 
#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
252 
#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
253 
#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
254 
#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
255 
#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
256 
#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
257 
#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
258 
#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
259 
#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
260 
#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
261 
#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
262 
#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
263 
#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
264 
#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
265 
#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
266 
#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
267 
#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
268 
#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
269 
#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
270 
#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
271 
#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
272 
#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
273 
#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
274 
#define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
275 
 
276 
//*****************************************************************************
277 
//
278 
// The following define the bit fields in the NVIC_ACTIVE0 register.
279 
//
280 
//*****************************************************************************
281 
#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
282 
#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
283 
#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
284 
#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
285 
#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
286 
#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
287 
#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
288 
#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
289 
#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
290 
#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
291 
#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
292 
#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
293 
#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
294 
#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
295 
#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
296 
#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
297 
#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
298 
#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
299 
#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
300 
#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
301 
#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
302 
#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
303 
#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
304 
#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
305 
#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
306 
#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
307 
#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
308 
#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
309 
#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
310 
#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
311 
#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
312 
#define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
313 
 
314 
//*****************************************************************************
315 
//
316 
// The following define the bit fields in the NVIC_PRI0 register.
317 
//
318 
//*****************************************************************************
319 
#define NVIC_PRI0_INT3_M        0xFF000000  // Interrupt 3 priority mask
320 
#define NVIC_PRI0_INT2_M        0x00FF0000  // Interrupt 2 priority mask
321 
#define NVIC_PRI0_INT1_M        0x0000FF00  // Interrupt 1 priority mask
322 
#define NVIC_PRI0_INT0_M        0x000000FF  // Interrupt 0 priority mask
323 
#define NVIC_PRI0_INT3_S        24
324 
#define NVIC_PRI0_INT2_S        16
325 
#define NVIC_PRI0_INT1_S        8
326 
#define NVIC_PRI0_INT0_S        0
327 
 
328 
//*****************************************************************************
329 
//
330 
// The following define the bit fields in the NVIC_PRI1 register.
331 
//
332 
//*****************************************************************************
333 
#define NVIC_PRI1_INT7_M        0xFF000000  // Interrupt 7 priority mask
334 
#define NVIC_PRI1_INT6_M        0x00FF0000  // Interrupt 6 priority mask
335 
#define NVIC_PRI1_INT5_M        0x0000FF00  // Interrupt 5 priority mask
336 
#define NVIC_PRI1_INT4_M        0x000000FF  // Interrupt 4 priority mask
337 
#define NVIC_PRI1_INT7_S        24
338 
#define NVIC_PRI1_INT6_S        16
339 
#define NVIC_PRI1_INT5_S        8
340 
#define NVIC_PRI1_INT4_S        0
341 
 
342 
//*****************************************************************************
343 
//
344 
// The following define the bit fields in the NVIC_PRI2 register.
345 
//
346 
//*****************************************************************************
347 
#define NVIC_PRI2_INT11_M       0xFF000000  // Interrupt 11 priority mask
348 
#define NVIC_PRI2_INT10_M       0x00FF0000  // Interrupt 10 priority mask
349 
#define NVIC_PRI2_INT9_M        0x0000FF00  // Interrupt 9 priority mask
350 
#define NVIC_PRI2_INT8_M        0x000000FF  // Interrupt 8 priority mask
351 
#define NVIC_PRI2_INT11_S       24
352 
#define NVIC_PRI2_INT10_S       16
353 
#define NVIC_PRI2_INT9_S        8
354 
#define NVIC_PRI2_INT8_S        0
355 
 
356 
//*****************************************************************************
357 
//
358 
// The following define the bit fields in the NVIC_PRI3 register.
359 
//
360 
//*****************************************************************************
361 
#define NVIC_PRI3_INT15_M       0xFF000000  // Interrupt 15 priority mask
362 
#define NVIC_PRI3_INT14_M       0x00FF0000  // Interrupt 14 priority mask
363 
#define NVIC_PRI3_INT13_M       0x0000FF00  // Interrupt 13 priority mask
364 
#define NVIC_PRI3_INT12_M       0x000000FF  // Interrupt 12 priority mask
365 
#define NVIC_PRI3_INT15_S       24
366 
#define NVIC_PRI3_INT14_S       16
367 
#define NVIC_PRI3_INT13_S       8
368 
#define NVIC_PRI3_INT12_S       0
369 
 
370 
//*****************************************************************************
371 
//
372 
// The following define the bit fields in the NVIC_PRI4 register.
373 
//
374 
//*****************************************************************************
375 
#define NVIC_PRI4_INT19_M       0xFF000000  // Interrupt 19 priority mask
376 
#define NVIC_PRI4_INT18_M       0x00FF0000  // Interrupt 18 priority mask
377 
#define NVIC_PRI4_INT17_M       0x0000FF00  // Interrupt 17 priority mask
378 
#define NVIC_PRI4_INT16_M       0x000000FF  // Interrupt 16 priority mask
379 
#define NVIC_PRI4_INT19_S       24
380 
#define NVIC_PRI4_INT18_S       16
381 
#define NVIC_PRI4_INT17_S       8
382 
#define NVIC_PRI4_INT16_S       0
383 
 
384 
//*****************************************************************************
385 
//
386 
// The following define the bit fields in the NVIC_PRI5 register.
387 
//
388 
//*****************************************************************************
389 
#define NVIC_PRI5_INT23_M       0xFF000000  // Interrupt 23 priority mask
390 
#define NVIC_PRI5_INT22_M       0x00FF0000  // Interrupt 22 priority mask
391 
#define NVIC_PRI5_INT21_M       0x0000FF00  // Interrupt 21 priority mask
392 
#define NVIC_PRI5_INT20_M       0x000000FF  // Interrupt 20 priority mask
393 
#define NVIC_PRI5_INT23_S       24
394 
#define NVIC_PRI5_INT22_S       16
395 
#define NVIC_PRI5_INT21_S       8
396 
#define NVIC_PRI5_INT20_S       0
397 
 
398 
//*****************************************************************************
399 
//
400 
// The following define the bit fields in the NVIC_PRI6 register.
401 
//
402 
//*****************************************************************************
403 
#define NVIC_PRI6_INT27_M       0xFF000000  // Interrupt 27 priority mask
404 
#define NVIC_PRI6_INT26_M       0x00FF0000  // Interrupt 26 priority mask
405 
#define NVIC_PRI6_INT25_M       0x0000FF00  // Interrupt 25 priority mask
406 
#define NVIC_PRI6_INT24_M       0x000000FF  // Interrupt 24 priority mask
407 
#define NVIC_PRI6_INT27_S       24
408 
#define NVIC_PRI6_INT26_S       16
409 
#define NVIC_PRI6_INT25_S       8
410 
#define NVIC_PRI6_INT24_S       0
411 
 
412 
//*****************************************************************************
413 
//
414 
// The following define the bit fields in the NVIC_PRI7 register.
415 
//
416 
//*****************************************************************************
417 
#define NVIC_PRI7_INT31_M       0xFF000000  // Interrupt 31 priority mask
418 
#define NVIC_PRI7_INT30_M       0x00FF0000  // Interrupt 30 priority mask
419 
#define NVIC_PRI7_INT29_M       0x0000FF00  // Interrupt 29 priority mask
420 
#define NVIC_PRI7_INT28_M       0x000000FF  // Interrupt 28 priority mask
421 
#define NVIC_PRI7_INT31_S       24
422 
#define NVIC_PRI7_INT30_S       16
423 
#define NVIC_PRI7_INT29_S       8
424 
#define NVIC_PRI7_INT28_S       0
425 
 
426 
//*****************************************************************************
427 
//
428 
// The following define the bit fields in the NVIC_CPUID register.
429 
//
430 
//*****************************************************************************
431 
#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer
432 
#define NVIC_CPUID_VAR_M        0x00F00000  // Variant
433 
#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Processor part number
434 
#define NVIC_CPUID_REV_M        0x0000000F  // Revision
435 
 
436 
//*****************************************************************************
437 
//
438 
// The following define the bit fields in the NVIC_INT_CTRL register.
439 
//
440 
//*****************************************************************************
441 
#define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI
442 
#define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV
443 
#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV
444 
#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling
445 
#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending
446 
#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception
447 
#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to base
448 
#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF  // Current active exception
449 
#define NVIC_INT_CTRL_VEC_PEN_S 12
450 
#define NVIC_INT_CTRL_VEC_ACT_S 0
451 
 
452 
//*****************************************************************************
453 
//
454 
// The following define the bit fields in the NVIC_VTABLE register.
455 
//
456 
//*****************************************************************************
457 
#define NVIC_VTABLE_BASE        0x20000000  // Vector table base
458 
#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector table offset
459 
#define NVIC_VTABLE_OFFSET_S    8
460 
 
461 
//*****************************************************************************
462 
//
463 
// The following define the bit fields in the NVIC_APINT register.
464 
//
465 
//*****************************************************************************
466 
#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Vector key mask
467 
#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
468 
#define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess
469 
#define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group
470 
#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
471 
#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
472 
#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
473 
#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
474 
#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
475 
#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
476 
#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
477 
#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
478 
#define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request
479 
#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info
480 
#define NVIC_APINT_VECT_RESET   0x00000001  // System reset
481 
 
482 
//*****************************************************************************
483 
//
484 
// The following define the bit fields in the NVIC_SYS_CTRL register.
485 
//
486 
//*****************************************************************************
487 
#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wakeup on pend
488 
#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep sleep enable
489 
#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR exit
490 
 
491 
//*****************************************************************************
492 
//
493 
// The following define the bit fields in the NVIC_CFG_CTRL register.
494 
//
495 
//*****************************************************************************
496 
#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore bus fault in NMI/fault
497 
#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on divide by 0
498 
#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on unaligned access
499 
#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004  // Allow deep interrupt trigger
500 
#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow main interrupt trigger
501 
#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread state control
502 
 
503 
//*****************************************************************************
504 
//
505 
// The following define the bit fields in the NVIC_SYS_PRI1 register.
506 
//
507 
//*****************************************************************************
508 
#define NVIC_SYS_PRI1_RES_M     0xFF000000  // Priority of reserved handler
509 
#define NVIC_SYS_PRI1_USAGE_M   0x00FF0000  // Priority of usage fault handler
510 
#define NVIC_SYS_PRI1_BUS_M     0x0000FF00  // Priority of bus fault handler
511 
#define NVIC_SYS_PRI1_MEM_M     0x000000FF  // Priority of mem manage handler
512 
#define NVIC_SYS_PRI1_USAGE_S   16
513 
#define NVIC_SYS_PRI1_BUS_S     8
514 
#define NVIC_SYS_PRI1_MEM_S     0
515 
 
516 
//*****************************************************************************
517 
//
518 
// The following define the bit fields in the NVIC_SYS_PRI2 register.
519 
//
520 
//*****************************************************************************
521 
#define NVIC_SYS_PRI2_SVC_M     0xFF000000  // Priority of SVCall handler
522 
#define NVIC_SYS_PRI2_RES_M     0x00FFFFFF  // Priority of reserved handlers
523 
#define NVIC_SYS_PRI2_SVC_S     24
524 
 
525 
//*****************************************************************************
526 
//
527 
// The following define the bit fields in the NVIC_SYS_PRI3 register.
528 
//
529 
//*****************************************************************************
530 
#define NVIC_SYS_PRI3_TICK_M    0xFF000000  // Priority of Sys Tick handler
531 
#define NVIC_SYS_PRI3_PENDSV_M  0x00FF0000  // Priority of PendSV handler
532 
#define NVIC_SYS_PRI3_RES_M     0x0000FF00  // Priority of reserved handler
533 
#define NVIC_SYS_PRI3_DEBUG_M   0x000000FF  // Priority of debug handler
534 
#define NVIC_SYS_PRI3_TICK_S    24
535 
#define NVIC_SYS_PRI3_PENDSV_S  16
536 
#define NVIC_SYS_PRI3_DEBUG_S   0
537 
 
538 
//*****************************************************************************
539 
//
540 
// The following define the bit fields in the NVIC_SYS_HND_CTRL register.
541 
//
542 
//*****************************************************************************
543 
#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage fault enable
544 
#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus fault enable
545 
#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Mem manage fault enable
546 
#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVCall is pended
547 
#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus fault is pended
548 
#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // Sys tick is active
549 
#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV is active
550 
#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Monitor is active
551 
#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVCall is active
552 
#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage fault is active
553 
#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus fault is active
554 
#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Mem manage is active
555 
 
556 
//*****************************************************************************
557 
//
558 
// The following define the bit fields in the NVIC_FAULT_STAT register.
559 
//
560 
//*****************************************************************************
561 
#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide by zero fault
562 
#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned access fault
563 
#define NVIC_FAULT_STAT_NOCP    0x00080000  // No coprocessor fault
564 
#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC fault
565 
#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid state fault
566 
#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined instruction fault
567 
#define NVIC_FAULT_STAT_BFARV   0x00008000  // BFAR is valid
568 
#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack bus fault
569 
#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack bus fault
570 
#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error
571 
#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error
572 
#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault
573 
#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid
574 
#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation
575 
#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation
576 
#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation
577 
#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation
578 
 
579 
//*****************************************************************************
580 
//
581 
// The following define the bit fields in the NVIC_HFAULT_STAT register.
582 
//
583 
//*****************************************************************************
584 
#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event
585 
#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler
586 
#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault
587 
 
588 
//*****************************************************************************
589 
//
590 
// The following define the bit fields in the NVIC_DEBUG_STAT register.
591 
//
592 
//*****************************************************************************
593 
#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
594 
#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
595 
#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
596 
#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
597 
#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request
598 
 
599 
//*****************************************************************************
600 
//
601 
// The following define the bit fields in the NVIC_MM_ADDR register.
602 
//
603 
//*****************************************************************************
604 
#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address
605 
#define NVIC_MM_ADDR_S          0
606 
 
607 
//*****************************************************************************
608 
//
609 
// The following define the bit fields in the NVIC_FAULT_ADDR register.
610 
//
611 
//*****************************************************************************
612 
#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address
613 
#define NVIC_FAULT_ADDR_S       0
614 
 
615 
//*****************************************************************************
616 
//
617 
// The following define the bit fields in the NVIC_EXC_STACK register.
618 
//
619 
//*****************************************************************************
620 
#define NVIC_EXC_STACK_DEEP     0x00000001  // Exception stack
621 
 
622 
//*****************************************************************************
623 
//
624 
// The following define the bit fields in the NVIC_EXC_NUM register.
625 
//
626 
//*****************************************************************************
627 
#define NVIC_EXC_NUM_M          0x000003FF  // Exception number
628 
#define NVIC_EXC_NUM_S          0
629 
 
630 
//*****************************************************************************
631 
//
632 
// The following define the bit fields in the NVIC_COPRO register.
633 
//
634 
//*****************************************************************************
635 
#define NVIC_COPRO_15_M         0xC0000000  // Coprocessor 15 access mask
636 
#define NVIC_COPRO_15_DENIED    0x00000000  // Coprocessor 15 access denied
637 
#define NVIC_COPRO_15_PRIV      0x40000000  // Coprocessor 15 privileged addess
638 
#define NVIC_COPRO_15_FULL      0xC0000000  // Coprocessor 15 full access
639 
#define NVIC_COPRO_14_M         0x30000000  // Coprocessor 14 access mask
640 
#define NVIC_COPRO_14_DENIED    0x00000000  // Coprocessor 14 access denied
641 
#define NVIC_COPRO_14_PRIV      0x10000000  // Coprocessor 14 privileged addess
642 
#define NVIC_COPRO_14_FULL      0x30000000  // Coprocessor 14 full access
643 
#define NVIC_COPRO_13_M         0x0C000000  // Coprocessor 13 access mask
644 
#define NVIC_COPRO_13_DENIED    0x00000000  // Coprocessor 13 access denied
645 
#define NVIC_COPRO_13_PRIV      0x04000000  // Coprocessor 13 privileged addess
646 
#define NVIC_COPRO_13_FULL      0x0C000000  // Coprocessor 13 full access
647 
#define NVIC_COPRO_12_M         0x03000000  // Coprocessor 12 access mask
648 
#define NVIC_COPRO_12_DENIED    0x00000000  // Coprocessor 12 access denied
649 
#define NVIC_COPRO_12_PRIV      0x01000000  // Coprocessor 12 privileged addess
650 
#define NVIC_COPRO_12_FULL      0x03000000  // Coprocessor 12 full access
651 
#define NVIC_COPRO_11_M         0x00C00000  // Coprocessor 11 access mask
652 
#define NVIC_COPRO_11_DENIED    0x00000000  // Coprocessor 11 access denied
653 
#define NVIC_COPRO_11_PRIV      0x00400000  // Coprocessor 11 privileged addess
654 
#define NVIC_COPRO_11_FULL      0x00C00000  // Coprocessor 11 full access
655 
#define NVIC_COPRO_10_M         0x00300000  // Coprocessor 10 access mask
656 
#define NVIC_COPRO_10_DENIED    0x00000000  // Coprocessor 10 access denied
657 
#define NVIC_COPRO_10_PRIV      0x00100000  // Coprocessor 10 privileged addess
658 
#define NVIC_COPRO_10_FULL      0x00300000  // Coprocessor 10 full access
659 
#define NVIC_COPRO_9_M          0x000C0000  // Coprocessor 9 access mask
660 
#define NVIC_COPRO_9_DENIED     0x00000000  // Coprocessor 9 access denied
661 
#define NVIC_COPRO_9_PRIV       0x00040000  // Coprocessor 9 privileged addess
662 
#define NVIC_COPRO_9_FULL       0x000C0000  // Coprocessor 9 full access
663 
#define NVIC_COPRO_8_M          0x00030000  // Coprocessor 8 access mask
664 
#define NVIC_COPRO_8_DENIED     0x00000000  // Coprocessor 8 access denied
665 
#define NVIC_COPRO_8_PRIV       0x00010000  // Coprocessor 8 privileged addess
666 
#define NVIC_COPRO_8_FULL       0x00030000  // Coprocessor 8 full access
667 
#define NVIC_COPRO_7_M          0x0000C000  // Coprocessor 7 access mask
668 
#define NVIC_COPRO_7_DENIED     0x00000000  // Coprocessor 7 access denied
669 
#define NVIC_COPRO_7_PRIV       0x00004000  // Coprocessor 7 privileged addess
670 
#define NVIC_COPRO_7_FULL       0x0000C000  // Coprocessor 7 full access
671 
#define NVIC_COPRO_6_M          0x00003000  // Coprocessor 6 access mask
672 
#define NVIC_COPRO_6_DENIED     0x00000000  // Coprocessor 6 access denied
673 
#define NVIC_COPRO_6_PRIV       0x00001000  // Coprocessor 6 privileged addess
674 
#define NVIC_COPRO_6_FULL       0x00003000  // Coprocessor 6 full access
675 
#define NVIC_COPRO_5_M          0x00000C00  // Coprocessor 5 access mask
676 
#define NVIC_COPRO_5_DENIED     0x00000000  // Coprocessor 5 access denied
677 
#define NVIC_COPRO_5_PRIV       0x00000400  // Coprocessor 5 privileged addess
678 
#define NVIC_COPRO_5_FULL       0x00000C00  // Coprocessor 5 full access
679 
#define NVIC_COPRO_4_M          0x00000300  // Coprocessor 4 access mask
680 
#define NVIC_COPRO_4_DENIED     0x00000000  // Coprocessor 4 access denied
681 
#define NVIC_COPRO_4_PRIV       0x00000100  // Coprocessor 4 privileged addess
682 
#define NVIC_COPRO_4_FULL       0x00000300  // Coprocessor 4 full access
683 
#define NVIC_COPRO_3_M          0x000000C0  // Coprocessor 3 access mask
684 
#define NVIC_COPRO_3_DENIED     0x00000000  // Coprocessor 3 access denied
685 
#define NVIC_COPRO_3_PRIV       0x00000040  // Coprocessor 3 privileged addess
686 
#define NVIC_COPRO_3_FULL       0x000000C0  // Coprocessor 3 full access
687 
#define NVIC_COPRO_2_M          0x00000030  // Coprocessor 2 access mask
688 
#define NVIC_COPRO_2_DENIED     0x00000000  // Coprocessor 2 access denied
689 
#define NVIC_COPRO_2_PRIV       0x00000010  // Coprocessor 2 privileged addess
690 
#define NVIC_COPRO_2_FULL       0x00000030  // Coprocessor 2 full access
691 
#define NVIC_COPRO_1_M          0x0000000C  // Coprocessor 1 access mask
692 
#define NVIC_COPRO_1_DENIED     0x00000000  // Coprocessor 1 access denied
693 
#define NVIC_COPRO_1_PRIV       0x00000004  // Coprocessor 1 privileged addess
694 
#define NVIC_COPRO_1_FULL       0x0000000C  // Coprocessor 1 full access
695 
#define NVIC_COPRO_0_M          0x00000003  // Coprocessor 0 access mask
696 
#define NVIC_COPRO_0_DENIED     0x00000000  // Coprocessor 0 access denied
697 
#define NVIC_COPRO_0_PRIV       0x00000001  // Coprocessor 0 privileged addess
698 
#define NVIC_COPRO_0_FULL       0x00000003  // Coprocessor 0 full access
699 
 
700 
//*****************************************************************************
701 
//
702 
// The following define the bit fields in the NVIC_MPU_TYPE register.
703 
//
704 
//*****************************************************************************
705 
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions
706 
#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions
707 
#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU
708 
#define NVIC_MPU_TYPE_IREGION_S 16
709 
#define NVIC_MPU_TYPE_DREGION_S 8
710 
 
711 
//*****************************************************************************
712 
//
713 
// The following define the bit fields in the NVIC_MPU_CTRL register.
714 
//
715 
//*****************************************************************************
716 
#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults
717 
#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable
718 
 
719 
//*****************************************************************************
720 
//
721 
// The following define the bit fields in the NVIC_MPU_NUMBER register.
722 
//
723 
//*****************************************************************************
724 
#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access
725 
#define NVIC_MPU_NUMBER_S       0
726 
 
727 
//*****************************************************************************
728 
//
729 
// The following define the bit fields in the NVIC_MPU_BASE register.
730 
//
731 
//*****************************************************************************
732 
#define NVIC_MPU_BASE_ADDR_M    0xFFFFFF00  // Base address
733 
#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid
734 
#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number
735 
#define NVIC_MPU_BASE_ADDR_S    8
736 
#define NVIC_MPU_BASE_REGION_S  0
737 
 
738 
//*****************************************************************************
739 
//
740 
// The following define the bit fields in the NVIC_MPU_ATTR register.
741 
//
742 
//*****************************************************************************
743 
#define NVIC_MPU_ATTR_ATTRS     0xFFFF0000  // Attributes
744 
#define NVIC_MPU_ATTR_SRD       0x0000FF00  // Sub-region disable
745 
#define NVIC_MPU_ATTR_SZENABLE  0x000000FF  // Region size
746 
 
747 
//*****************************************************************************
748 
//
749 
// The following define the bit fields in the NVIC_DBG_CTRL register.
750 
//
751 
//*****************************************************************************
752 
#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
753 
#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
754 
#define NVIC_DBG_CTRL_MON_PEND  0x00008000  // Pend the monitor
755 
#define NVIC_DBG_CTRL_MON_REQ   0x00004000  // Monitor request
756 
#define NVIC_DBG_CTRL_MON_EN    0x00002000  // Debug monitor enable
757 
#define NVIC_DBG_CTRL_MONSTEP   0x00001000  // Monitor step the core
758 
#define NVIC_DBG_CTRL_S_SLEEP   0x00000400  // Core is sleeping
759 
#define NVIC_DBG_CTRL_S_HALT    0x00000200  // Core status on halt
760 
#define NVIC_DBG_CTRL_S_REGRDY  0x00000100  // Register read/write available
761 
#define NVIC_DBG_CTRL_S_LOCKUP  0x00000080  // Core is locked up
762 
#define NVIC_DBG_CTRL_C_RESET   0x00000010  // Reset the core
763 
#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
764 
#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
765 
#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
766 
#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug
767 
 
768 
//*****************************************************************************
769 
//
770 
// The following define the bit fields in the NVIC_DBG_XFER register.
771 
//
772 
//*****************************************************************************
773 
#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
774 
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
775 
#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
776 
#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
777 
#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
778 
#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
779 
#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
780 
#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
781 
#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
782 
#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
783 
#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
784 
#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
785 
#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
786 
#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
787 
#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
788 
#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
789 
#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
790 
#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
791 
#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
792 
#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
793 
#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
794 
#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
795 
#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
796 
 
797 
//*****************************************************************************
798 
//
799 
// The following define the bit fields in the NVIC_DBG_DATA register.
800 
//
801 
//*****************************************************************************
802 
#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
803 
#define NVIC_DBG_DATA_S         0
804 
 
805 
//*****************************************************************************
806 
//
807 
// The following define the bit fields in the NVIC_DBG_INT register.
808 
//
809 
//*****************************************************************************
810 
#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
811 
#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
812 
#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
813 
#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
814 
#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
815 
#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
816 
#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
817 
#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
818 
#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
819 
#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
820 
#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch
821 
 
822 
//*****************************************************************************
823 
//
824 
// The following define the bit fields in the NVIC_SW_TRIG register.
825 
//
826 
//*****************************************************************************
827 
#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger
828 
#define NVIC_SW_TRIG_INTID_S    0
829 
 
830 
#endif // __HW_NVIC_H__

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