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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_KEIL/] [LuminaryCode/] [hw_pwm.h] - Blame information for rev 581

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1 581 jeremybenn
//*****************************************************************************
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//
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// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
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//
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// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's Stellaris Family of microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws.  All rights are reserved.  Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 816 of the Stellaris Driver Library.
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//
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//*****************************************************************************
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#ifndef __HW_PWM_H__
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#define __HW_PWM_H__
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//*****************************************************************************
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//
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// PWM Module Register Offsets.
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//
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//*****************************************************************************
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#define PWM_O_CTL               0x00000000  // PWM Master Control register
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#define PWM_O_SYNC              0x00000004  // PWM Time Base Sync register
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#define PWM_O_ENABLE            0x00000008  // PWM Output Enable register
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#define PWM_O_INVERT            0x0000000C  // PWM Output Inversion register
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#define PWM_O_FAULT             0x00000010  // PWM Output Fault register
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#define PWM_O_INTEN             0x00000014  // PWM Interrupt Enable register
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#define PWM_O_RIS               0x00000018  // PWM Interrupt Raw Status reg.
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#define PWM_O_ISC               0x0000001C  // PWM Interrupt Status register
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#define PWM_O_STATUS            0x00000020  // PWM Status register
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//*****************************************************************************
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//
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// The following define the bit fields in the PWM Master Control register.
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//
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//*****************************************************************************
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#define PWM_CTL_GLOBAL_SYNC2    0x00000004  // Global sync generator 2
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#define PWM_CTL_GLOBAL_SYNC1    0x00000002  // Global sync generator 1
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#define PWM_CTL_GLOBAL_SYNC0    0x00000001  // Global sync generator 0
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//*****************************************************************************
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//
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// The following define the bit fields in the PWM Time Base Sync register.
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//
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//*****************************************************************************
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#define PWM_SYNC_SYNC2          0x00000004  // Reset generator 2 counter
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#define PWM_SYNC_SYNC1          0x00000002  // Reset generator 1 counter
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#define PWM_SYNC_SYNC0          0x00000001  // Reset generator 0 counter
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//*****************************************************************************
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//
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// The following define the bit fields in the PWM Output Enable register.
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//
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//*****************************************************************************
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#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 pin enable
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#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 pin enable
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#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 pin enable
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#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 pin enable
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#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 pin enable
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#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 pin enable
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//*****************************************************************************
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//
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// The following define the bit fields in the PWM Inversion register.
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//
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//*****************************************************************************
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#define PWM_INVERT_PWM5INV      0x00000020  // PWM5 pin invert
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#define PWM_INVERT_PWM4INV      0x00000010  // PWM4 pin invert
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#define PWM_INVERT_PWM3INV      0x00000008  // PWM3 pin invert
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#define PWM_INVERT_PWM2INV      0x00000004  // PWM2 pin invert
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#define PWM_INVERT_PWM1INV      0x00000002  // PWM1 pin invert
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#define PWM_INVERT_PWM0INV      0x00000001  // PWM0 pin invert
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//*****************************************************************************
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//
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// The following define the bit fields in the PWM Fault register.
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//
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//*****************************************************************************
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#define PWM_FAULT_FAULT5        0x00000020  // PWM5 pin fault
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#define PWM_FAULT_FAULT4        0x00000010  // PWM5 pin fault
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#define PWM_FAULT_FAULT3        0x00000008  // PWM5 pin fault
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#define PWM_FAULT_FAULT2        0x00000004  // PWM5 pin fault
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#define PWM_FAULT_FAULT1        0x00000002  // PWM5 pin fault
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#define PWM_FAULT_FAULT0        0x00000001  // PWM5 pin fault
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//*****************************************************************************
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//
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// PWM Interrupt Register bit definitions.
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//
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//*****************************************************************************
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#define PWM_INT_INTFAULT        0x00010000  // Fault interrupt pending
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//*****************************************************************************
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//
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// The following define the bit fields in the PWM Status register.
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//
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//*****************************************************************************
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#define PWM_STATUS_FAULT        0x00000001  // Fault status
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//*****************************************************************************
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//
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// PWM Generator standard offsets.
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//
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//*****************************************************************************
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#define PWM_GEN_0_OFFSET        0x00000040  // PWM0 base
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#define PWM_GEN_1_OFFSET        0x00000080  // PWM1 base
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#define PWM_GEN_2_OFFSET        0x000000C0  // PWM2 base
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#define PWM_O_X_CTL             0x00000000  // Gen Control Reg
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#define PWM_O_X_INTEN           0x00000004  // Gen Int/Trig Enable Reg
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#define PWM_O_X_RIS             0x00000008  // Gen Raw Int Status Reg
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#define PWM_O_X_ISC             0x0000000C  // Gen Int Status Reg
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#define PWM_O_X_LOAD            0x00000010  // Gen Load Reg
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#define PWM_O_X_COUNT           0x00000014  // Gen Counter Reg
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#define PWM_O_X_CMPA            0x00000018  // Gen Compare A Reg
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#define PWM_O_X_CMPB            0x0000001C  // Gen Compare B Reg
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#define PWM_O_X_GENA            0x00000020  // Gen Generator A Ctrl Reg
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#define PWM_O_X_GENB            0x00000024  // Gen Generator B Ctrl Reg
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#define PWM_O_X_DBCTL           0x00000028  // Gen Dead Band Ctrl Reg
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#define PWM_O_X_DBRISE          0x0000002C  // Gen DB Rising Edge Delay Reg
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#define PWM_O_X_DBFALL          0x00000030  // Gen DB Falling Edge Delay Reg
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//*****************************************************************************
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//
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// PWM_X Control Register bit definitions.
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//
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//*****************************************************************************
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#define PWM_X_CTL_ENABLE        0x00000001  // Master enable for gen block
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#define PWM_X_CTL_MODE          0x00000002  // Counter mode, down or up/down
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#define PWM_X_CTL_DEBUG         0x00000004  // Debug mode
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#define PWM_X_CTL_LOADUPD       0x00000008  // Update mode for the load reg
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#define PWM_X_CTL_CMPAUPD       0x00000010  // Update mode for comp A reg
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#define PWM_X_CTL_CMPBUPD       0x00000020  // Update mode for comp B reg
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//*****************************************************************************
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//
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// PWM_X Interrupt/Trigger Enable Register bit definitions.
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//
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//*****************************************************************************
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#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Int if COUNT = 0
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#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Int if COUNT = LOAD
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#define PWM_X_INTEN_INTCMPAU    0x00000004  // Int if COUNT = CMPA U
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#define PWM_X_INTEN_INTCMPAD    0x00000008  // Int if COUNT = CMPA D
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#define PWM_X_INTEN_INTCMPBU    0x00000010  // Int if COUNT = CMPA U
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#define PWM_X_INTEN_INTCMPBD    0x00000020  // Int if COUNT = CMPA D
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#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trig if COUNT = 0
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#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trig if COUNT = LOAD
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#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trig if COUNT = CMPA U
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#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trig if COUNT = CMPA D
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#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trig if COUNT = CMPA U
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#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trig if COUNT = CMPA D
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//*****************************************************************************
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//
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// PWM_X Raw Interrupt Status Register bit definitions.
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//
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//*****************************************************************************
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#define PWM_X_RIS_INTCNTZERO    0x00000001  // PWM_X_COUNT = 0 int
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#define PWM_X_RIS_INTCNTLOAD    0x00000002  // PWM_X_COUNT = PWM_X_LOAD int
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#define PWM_X_RIS_INTCMPAU      0x00000004  // PWM_X_COUNT = PWM_X_CMPA U int
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#define PWM_X_RIS_INTCMPAD      0x00000008  // PWM_X_COUNT = PWM_X_CMPA D int
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#define PWM_X_RIS_INTCMPBU      0x00000010  // PWM_X_COUNT = PWM_X_CMPB U int
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#define PWM_X_RIS_INTCMPBD      0x00000020  // PWM_X_COUNT = PWM_X_CMPB D int
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//*****************************************************************************
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//
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// PWM_X Interrupt Status Register bit definitions.
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//
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//*****************************************************************************
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#define PWM_X_INT_INTCNTZERO    0x00000001  // PWM_X_COUNT = 0 received
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#define PWM_X_INT_INTCNTLOAD    0x00000002  // PWM_X_COUNT = PWM_X_LOAD rcvd
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#define PWM_X_INT_INTCMPAU      0x00000004  // PWM_X_COUNT = PWM_X_CMPA U rcvd
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#define PWM_X_INT_INTCMPAD      0x00000008  // PWM_X_COUNT = PWM_X_CMPA D rcvd
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#define PWM_X_INT_INTCMPBU      0x00000010  // PWM_X_COUNT = PWM_X_CMPB U rcvd
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#define PWM_X_INT_INTCMPBD      0x00000020  // PWM_X_COUNT = PWM_X_CMPB D rcvd
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//*****************************************************************************
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//
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// PWM_X Generator A/B Control Register bit definitions.
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//
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//*****************************************************************************
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#define PWM_X_GEN_Y_ACTZERO     0x00000003  // Act PWM_X_COUNT = 0
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#define PWM_X_GEN_Y_ACTLOAD     0x0000000C  // Act PWM_X_COUNT = PWM_X_LOAD
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#define PWM_X_GEN_Y_ACTCMPAU    0x00000030  // Act PWM_X_COUNT = PWM_X_CMPA U
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#define PWM_X_GEN_Y_ACTCMPAD    0x000000C0  // Act PWM_X_COUNT = PWM_X_CMPA D
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#define PWM_X_GEN_Y_ACTCMPBU    0x00000300  // Act PWM_X_COUNT = PWM_X_CMPB U
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#define PWM_X_GEN_Y_ACTCMPBD    0x00000C00  // Act PWM_X_COUNT = PWM_X_CMPB D
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//*****************************************************************************
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//
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// PWM_X Generator A/B Control Register action definitions.
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//
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//*****************************************************************************
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#define PWM_GEN_ACT_NONE        0x0         // Do nothing
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#define PWM_GEN_ACT_INV         0x1         // Invert the output signal
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#define PWM_GEN_ACT_ZERO        0x2         // Set the output signal to zero
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#define PWM_GEN_ACT_ONE         0x3         // Set the output signal to one
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#define PWM_GEN_ACT_ZERO_SHIFT  0           // Shift amount for the zero action
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#define PWM_GEN_ACT_LOAD_SHIFT  2           // Shift amount for the load action
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#define PWM_GEN_ACT_A_UP_SHIFT  4           // Shift amount for the A up action
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#define PWM_GEN_ACT_A_DN_SHIFT  6           // Shift amount for the A dn action
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#define PWM_GEN_ACT_B_UP_SHIFT  8           // Shift amount for the B up action
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#define PWM_GEN_ACT_B_DN_SHIFT  10          // Shift amount for the B dn action
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//*****************************************************************************
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//
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// PWM_X Dead Band Control Register bit definitions.
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//
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//*****************************************************************************
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#define PWM_DBCTL_ENABLE        0x00000001  // Enable dead band insertion
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//*****************************************************************************
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//
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// PWM Register reset values.
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//
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//*****************************************************************************
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#define PWM_RV_CTL              0x00000000  // Master control of the PWM module
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#define PWM_RV_SYNC             0x00000000  // Counter synch for PWM generators
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#define PWM_RV_ENABLE           0x00000000  // Master enable for the PWM
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                                            // output pins
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#define PWM_RV_INVERT           0x00000000  // Inversion control for
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                                            // PWM output pins
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#define PWM_RV_FAULT            0x00000000  // Fault handling for the PWM
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                                            // output pins
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#define PWM_RV_INTEN            0x00000000  // Interrupt enable
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#define PWM_RV_RIS              0x00000000  // Raw interrupt status
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#define PWM_RV_ISC              0x00000000  // Interrupt status and clearing
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#define PWM_RV_STATUS           0x00000000  // Status
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#define PWM_RV_X_CTL            0x00000000  // Master control of the PWM
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                                            // generator block
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#define PWM_RV_X_INTEN          0x00000000  // Interrupt and trigger enable
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#define PWM_RV_X_RIS            0x00000000  // Raw interrupt status
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#define PWM_RV_X_ISC            0x00000000  // Interrupt status and clearing
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#define PWM_RV_X_LOAD           0x00000000  // The load value for the counter
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#define PWM_RV_X_COUNT          0x00000000  // The current counter value
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#define PWM_RV_X_CMPA           0x00000000  // The comparator A value
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#define PWM_RV_X_CMPB           0x00000000  // The comparator B value
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#define PWM_RV_X_GENA           0x00000000  // Controls PWM generator A
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#define PWM_RV_X_GENB           0x00000000  // Controls PWM generator B
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#define PWM_RV_X_DBCTL          0x00000000  // Control the dead band generator
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#define PWM_RV_X_DBRISE         0x00000000  // The dead band rising edge delay
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                                            // count
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#define PWM_RV_X_DBFALL         0x00000000  // The dead band falling edge delay
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                                            // count
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#endif //  __HW_PWM_H__

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