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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S811_KEIL/] [LuminaryCode/] [hw_timer.h] - Blame information for rev 581

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1 581 jeremybenn
//*****************************************************************************
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//
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// hw_timer.h - Defines and macros used when accessing the timer.
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//
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// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's Stellaris Family of microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws.  All rights are reserved.  Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 816 of the Stellaris Driver Library.
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//
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//*****************************************************************************
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#ifndef __HW_TIMER_H__
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#define __HW_TIMER_H__
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//*****************************************************************************
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//
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// The following define the offsets of the timer registers.
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//
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//*****************************************************************************
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#define TIMER_O_CFG             0x00000000  // Configuration register
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#define TIMER_O_TAMR            0x00000004  // TimerA mode register
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#define TIMER_O_TBMR            0x00000008  // TimerB mode register
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#define TIMER_O_CTL             0x0000000C  // Control register
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#define TIMER_O_IMR             0x00000018  // Interrupt mask register
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#define TIMER_O_RIS             0x0000001C  // Interrupt status register
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#define TIMER_O_MIS             0x00000020  // Masked interrupt status reg.
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#define TIMER_O_ICR             0x00000024  // Interrupt clear register
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#define TIMER_O_TAILR           0x00000028  // TimerA interval load register
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#define TIMER_O_TBILR           0x0000002C  // TimerB interval load register
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#define TIMER_O_TAMATCHR        0x00000030  // TimerA match register
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#define TIMER_O_TBMATCHR        0x00000034  // TimerB match register
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#define TIMER_O_TAPR            0x00000038  // TimerA prescale register
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#define TIMER_O_TBPR            0x0000003C  // TimerB prescale register
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#define TIMER_O_TAPMR           0x00000040  // TimerA prescale match register
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#define TIMER_O_TBPMR           0x00000044  // TimerB prescale match register
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#define TIMER_O_TAR             0x00000048  // TimerA register
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#define TIMER_O_TBR             0x0000004C  // TimerB register
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//*****************************************************************************
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//
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// The following define the reset values of the timer registers.
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//
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//*****************************************************************************
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#define TIMER_RV_CFG            0x00000000  // Configuration register RV
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#define TIMER_RV_TAMR           0x00000000  // TimerA mode register RV
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#define TIMER_RV_TBMR           0x00000000  // TimerB mode register RV
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#define TIMER_RV_CTL            0x00000000  // Control register RV
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#define TIMER_RV_IMR            0x00000000  // Interrupt mask register RV
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#define TIMER_RV_RIS            0x00000000  // Interrupt status register RV
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#define TIMER_RV_MIS            0x00000000  // Masked interrupt status reg RV
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#define TIMER_RV_ICR            0x00000000  // Interrupt clear register RV
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#define TIMER_RV_TAILR          0xFFFFFFFF  // TimerA interval load reg RV
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#define TIMER_RV_TBILR          0x0000FFFF  // TimerB interval load reg RV
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#define TIMER_RV_TAMATCHR       0xFFFFFFFF  // TimerA match register RV
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#define TIMER_RV_TBMATCHR       0x0000FFFF  // TimerB match register RV
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#define TIMER_RV_TAPR           0x00000000  // TimerA prescale register RV
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#define TIMER_RV_TBPR           0x00000000  // TimerB prescale register RV
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#define TIMER_RV_TAPMR          0x00000000  // TimerA prescale match reg RV
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#define TIMER_RV_TBPMR          0x00000000  // TimerB prescale match regi RV
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#define TIMER_RV_TAR            0xFFFFFFFF  // TimerA register RV
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#define TIMER_RV_TBR            0x0000FFFF  // TimerB register RV
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_CFG register.
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//
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//*****************************************************************************
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#define TIMER_CFG_CFG_MSK       0x00000007  // Configuration options mask
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#define TIMER_CFG_16_BIT        0x00000004  // Two 16 bit timers
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#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32 bit RTC
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#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32 bit timer
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_TnMR register.
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//
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//*****************************************************************************
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#define TIMER_TNMR_TNAMS        0x00000008  // Alternate mode select
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#define TIMER_TNMR_TNCMR        0x00000004  // Capture mode - count or time
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#define TIMER_TNMR_TNTMR_MSK    0x00000003  // Timer mode mask
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#define TIMER_TNMR_TNTMR_CAP    0x00000003  // Mode - capture
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#define TIMER_TNMR_TNTMR_PERIOD 0x00000002  // Mode - periodic
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#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001  // Mode - one shot
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_CTL register.
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//
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//*****************************************************************************
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#define TIMER_CTL_TBPWML        0x00004000  // TimerB PWM output level invert
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#define TIMER_CTL_TBOTE         0x00002000  // TimerB output trigger enable
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#define TIMER_CTL_TBEVENT_MSK   0x00000C00  // TimerB event mode mask
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#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // TimerB event mode - both edges
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#define TIMER_CTL_TBEVENT_NEG   0x00000400  // TimerB event mode - neg edge
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#define TIMER_CTL_TBEVENT_POS   0x00000000  // TimerB event mode - pos edge
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#define TIMER_CTL_TBSTALL       0x00000200  // TimerB stall enable
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#define TIMER_CTL_TBEN          0x00000100  // TimerB enable
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#define TIMER_CTL_TAPWML        0x00000040  // TimerA PWM output level invert
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#define TIMER_CTL_TAOTE         0x00000020  // TimerA output trigger enable
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#define TIMER_CTL_RTCEN         0x00000010  // RTC counter enable
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#define TIMER_CTL_TAEVENT_MSK   0x0000000C  // TimerA event mode mask
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#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // TimerA event mode - both edges
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#define TIMER_CTL_TAEVENT_NEG   0x00000004  // TimerA event mode - neg edge
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#define TIMER_CTL_TAEVENT_POS   0x00000000  // TimerA event mode - pos edge
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#define TIMER_CTL_TASTALL       0x00000002  // TimerA stall enable
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#define TIMER_CTL_TAEN          0x00000001  // TimerA enable
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_IMR register.
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//
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//*****************************************************************************
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#define TIMER_IMR_CBEIM         0x00000400  // CaptureB event interrupt mask
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#define TIMER_IMR_CBMIM         0x00000200  // CaptureB match interrupt mask
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#define TIMER_IMR_TBTOIM        0x00000100  // TimerB time out interrupt mask
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#define TIMER_IMR_RTCIM         0x00000008  // RTC interrupt mask
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#define TIMER_IMR_CAEIM         0x00000004  // CaptureA event interrupt mask
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#define TIMER_IMR_CAMIM         0x00000002  // CaptureA match interrupt mask
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#define TIMER_IMR_TATOIM        0x00000001  // TimerA time out interrupt mask
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_RIS register.
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//
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//*****************************************************************************
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#define TIMER_RIS_CBERIS        0x00000400  // CaptureB event raw int status
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#define TIMER_RIS_CBMRIS        0x00000200  // CaptureB match raw int status
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#define TIMER_RIS_TBTORIS       0x00000100  // TimerB time out raw int status
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#define TIMER_RIS_RTCRIS        0x00000008  // RTC raw int status
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#define TIMER_RIS_CAERIS        0x00000004  // CaptureA event raw int status
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#define TIMER_RIS_CAMRIS        0x00000002  // CaptureA match raw int status
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#define TIMER_RIS_TATORIS       0x00000001  // TimerA time out raw int status
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_MIS register.
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//
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//*****************************************************************************
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#define TIMER_RIS_CBEMIS        0x00000400  // CaptureB event masked int status
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#define TIMER_RIS_CBMMIS        0x00000200  // CaptureB match masked int status
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#define TIMER_RIS_TBTOMIS       0x00000100  // TimerB time out masked int stat
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#define TIMER_RIS_RTCMIS        0x00000008  // RTC masked int status
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#define TIMER_RIS_CAEMIS        0x00000004  // CaptureA event masked int status
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#define TIMER_RIS_CAMMIS        0x00000002  // CaptureA match masked int status
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#define TIMER_RIS_TATOMIS       0x00000001  // TimerA time out masked int stat
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_ICR register.
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//
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//*****************************************************************************
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#define TIMER_ICR_CBECINT       0x00000400  // CaptureB event interrupt clear
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#define TIMER_ICR_CBMCINT       0x00000200  // CaptureB match interrupt clear
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#define TIMER_ICR_TBTOCINT      0x00000100  // TimerB time out interrupt clear
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#define TIMER_ICR_RTCCINT       0x00000008  // RTC interrupt clear
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#define TIMER_ICR_CAECINT       0x00000004  // CaptureA event interrupt clear
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#define TIMER_ICR_CAMCINT       0x00000002  // CaptureA match interrupt clear
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#define TIMER_ICR_TATOCINT      0x00000001  // TimerA time out interrupt clear
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_TAILR register.
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//
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//*****************************************************************************
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#define TIMER_TAILR_TAILRH      0xFFFF0000  // TimerB load val in 32 bit mode
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#define TIMER_TAILR_TAILRL      0x0000FFFF  // TimerA interval load value
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//*****************************************************************************
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//
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// The following defines the bit fields in the TIMER_TBILR register.
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//
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//*****************************************************************************
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#define TIMER_TBILR_TBILRL      0x0000FFFF  // TimerB interval load value
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_TAMATCHR register.
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//
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//*****************************************************************************
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#define TIMER_TAMATCHR_TAMRH    0xFFFF0000  // TimerB match val in 32 bit mode
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#define TIMER_TAMATCHR_TAMRL    0x0000FFFF  // TimerA match value
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//*****************************************************************************
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//
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// The following defines the bit fields in the TIMER_TBMATCHR register.
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//
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//*****************************************************************************
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#define TIMER_TBMATCHR_TBMRL    0x0000FFFF  // TimerB match load value
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//*****************************************************************************
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//
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// The following defines the bit fields in the TIMER_TnPR register.
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//
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//*****************************************************************************
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#define TIMER_TNPR_TNPSR        0x000000FF  // TimerN prescale value
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//*****************************************************************************
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//
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// The following defines the bit fields in the TIMER_TnPMR register.
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//
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//*****************************************************************************
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#define TIMER_TNPMR_TNPSMR      0x000000FF  // TimerN prescale match value
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//*****************************************************************************
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//
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// The following define the bit fields in the TIMER_TAR register.
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//
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//*****************************************************************************
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#define TIMER_TAR_TARH          0xFFFF0000  // TimerB val in 32 bit mode
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#define TIMER_TAR_TARL          0x0000FFFF  // TimerA value
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//*****************************************************************************
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//
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// The following defines the bit fields in the TIMER_TBR register.
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//
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//*****************************************************************************
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#define TIMER_TBR_TBRL          0x0000FFFF  // TimerB value
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#endif // __HW_TIMER_H__

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