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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3Sxxxx_IAR_Keil/] [LM3Sxxxx.icf] - Blame information for rev 581

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1 581 jeremybenn
//*****************************************************************************
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//
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// enet_lwip.icf - Linker configuration file for enet_lwip.
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//
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// Copyright (c) 2007 Luminary Micro, Inc.  All rights reserved.
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// Luminary Micro Confidential - For Use Under NDA Only
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//
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//*****************************************************************************
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//
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// Define a memory region that covers the entire 4 GB addressible space of the
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// processor.
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//
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define memory mem with size = 4G;
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//
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// Define a region for the on-chip flash.
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//
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define region FLASH = mem:[from 0x00000000 to 0x0003ffff];
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//
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// Define a region for the on-chip SRAM.
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//
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define region SRAM = mem:[from 0x20000000 to 0x2000ffff];
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//
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// Define a block for the heap.  The size should be set to something other
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// than zero if things in the C library that require the heap are used.
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//
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define block HEAP with alignment = 8, size = 0x00000000 { };
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//
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// Indicate that the read/write values should be initialized by copying from
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// flash.
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//
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initialize by copy { readwrite };
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//
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// Initicate that the noinit values should be left alone.  This includes the
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// stack, which if initialized will destroy the return address from the
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// initialization code, causing the processor to branch to zero and fault.
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//
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do not initialize { section .noinit };
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//
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// Place the interrupt vectors at the start of flash.
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//
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place at start of FLASH { readonly section .intvec };
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//
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// Place the remainder of the read-only items into flash.
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//
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place in FLASH { readonly };
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//
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// Place all read/write items into SRAM.
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//
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place in SRAM { readwrite, block HEAP };

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