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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3Sxxxx_IAR_Keil/] [webserver/] [emac.h] - Blame information for rev 581

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Line No. Rev Author Line
1 581 jeremybenn
/*----------------------------------------------------------------------------
2
 *      LPC2378 Ethernet Definitions
3
 *----------------------------------------------------------------------------
4
 *      Name:    EMAC.H
5
 *      Purpose: Philips LPC2378 EMAC hardware definitions
6
 *----------------------------------------------------------------------------
7
 *      Copyright (c) 2006 KEIL - An ARM Company. All rights reserved.
8
 *---------------------------------------------------------------------------*/
9
#ifndef __EMAC_H
10
#define __EMAC_H
11
 
12
/* MAC address definition.  The MAC address must be unique on the network. */
13
#define emacETHADDR0 0
14
#define emacETHADDR1 0xbd
15
#define emacETHADDR2 0x33
16
#define emacETHADDR3 0x02
17
#define emacETHADDR4 0x64
18
#define emacETHADDR5 0x24
19
 
20
 
21
/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
22
#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
23
#define NUM_TX_FRAG         2           /* Num.of TX Fragments 2*1536= 3.0kB */
24
#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
25
 
26
#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
27
 
28
/* EMAC variables located in 16K Ethernet SRAM */
29
#define RX_DESC_BASE        0x7FE00000
30
#define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)
31
#define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)
32
#define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)
33
#define RX_BUF_BASE         (TX_STAT_BASE + NUM_TX_FRAG*4)
34
#define TX_BUF_BASE         (RX_BUF_BASE  + NUM_RX_FRAG*ETH_FRAG_SIZE)
35
 
36
/* RX and TX descriptor and status definitions. */
37
#define RX_DESC_PACKET(i)   (*(unsigned int *)(RX_DESC_BASE   + 8*i))
38
#define RX_DESC_CTRL(i)     (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
39
#define RX_STAT_INFO(i)     (*(unsigned int *)(RX_STAT_BASE   + 8*i))
40
#define RX_STAT_HASHCRC(i)  (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
41
#define TX_DESC_PACKET(i)   (*(unsigned int *)(TX_DESC_BASE   + 8*i))
42
#define TX_DESC_CTRL(i)     (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
43
#define TX_STAT_INFO(i)     (*(unsigned int *)(TX_STAT_BASE   + 4*i))
44
#define RX_BUF(i)           (RX_BUF_BASE + ETH_FRAG_SIZE*i)
45
#define TX_BUF(i)           (TX_BUF_BASE + ETH_FRAG_SIZE*i)
46
 
47
/* MAC Configuration Register 1 */
48
#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
49
#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
50
#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
51
#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
52
#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
53
#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
54
#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
55
#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
56
#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
57
#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
58
#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
59
 
60
/* MAC Configuration Register 2 */
61
#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
62
#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
63
#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
64
#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
65
#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
66
#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
67
#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
68
#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
69
#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
70
#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
71
#undef  MAC2_NO_BACKOFF /* Remove compiler warning. */
72
#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
73
#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
74
#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
75
 
76
/* Back-to-Back Inter-Packet-Gap Register */
77
#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
78
#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
79
 
80
/* Non Back-to-Back Inter-Packet-Gap Register */
81
#define IPGR_DEF            0x00000012  /* Recommended value                 */
82
 
83
/* Collision Window/Retry Register */
84
#define CLRT_DEF            0x0000370F  /* Default value                     */
85
 
86
/* PHY Support Register */
87
#undef SUPP_SPEED   /* Remove compiler warning. */
88
#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
89
#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
90
 
91
/* Test Register */
92
#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
93
#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
94
#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
95
 
96
/* MII Management Configuration Register */
97
#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
98
#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
99
#define MCFG_CLK_SEL        0x0000001C  /* Clock Select Mask                 */
100
#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
101
 
102
/* MII Management Command Register */
103
#undef MCMD_READ   /* Remove compiler warning. */
104
#define MCMD_READ           0x00000001  /* MII Read                          */
105
#undef MCMD_SCAN /* Remove compiler warning. */
106
#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
107
 
108
#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
109
#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
110
 
111
/* MII Management Address Register */
112
#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
113
#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
114
 
115
/* MII Management Indicators Register */
116
#undef MIND_BUSY   /* Remove compiler warning. */
117
#define MIND_BUSY           0x00000001  /* MII is Busy                       */
118
#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
119
#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
120
#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
121
 
122
/* Command Register */
123
#define CR_RX_EN            0x00000001  /* Enable Receive                    */
124
#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
125
#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
126
#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
127
#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
128
#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
129
#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
130
#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
131
#define CR_RMII             0x00000200  /* Reduced MII Interface             */
132
#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
133
 
134
/* Status Register */
135
#define SR_RX_EN            0x00000001  /* Enable Receive                    */
136
#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
137
 
138
/* Transmit Status Vector 0 Register */
139
#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
140
#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
141
#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
142
#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
143
#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
144
#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
145
#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
146
#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
147
#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
148
#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
149
#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
150
#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
151
#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
152
#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
153
#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
154
#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
155
#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
156
 
157
/* Transmit Status Vector 1 Register */
158
#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
159
#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
160
 
161
/* Receive Status Vector Register */
162
#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
163
#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
164
#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
165
#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
166
#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
167
#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
168
#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
169
#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
170
#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
171
#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
172
#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
173
#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
174
#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
175
#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
176
#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
177
#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
178
 
179
/* Flow Control Counter Register */
180
#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
181
#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
182
 
183
/* Flow Control Status Register */
184
#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
185
 
186
/* Receive Filter Control Register */
187
#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
188
#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
189
#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
190
#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
191
#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
192
#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
193
#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
194
#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
195
 
196
/* Receive Filter WoL Status/Clear Registers */
197
#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
198
#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
199
#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
200
#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
201
#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
202
#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
203
#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
204
#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
205
 
206
/* Interrupt Status/Enable/Clear/Set Registers */
207
#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
208
#define INT_RX_ERR          0x00000002  /* Receive Error                     */
209
#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
210
#define INT_RX_DONE         0x00000008  /* Receive Done                      */
211
#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
212
#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
213
#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
214
#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
215
#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
216
#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
217
 
218
/* Power Down Register */
219
#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
220
 
221
/* RX Descriptor Control Word */
222
#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
223
#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
224
 
225
/* RX Status Hash CRC Word */
226
#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
227
#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
228
 
229
/* RX Status Information Word */
230
#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
231
#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
232
#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
233
#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
234
#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
235
#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
236
#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
237
#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
238
#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
239
#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
240
#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
241
#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
242
#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
243
#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
244
#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
245
 
246
#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | \
247
                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
248
 
249
/* TX Descriptor Control Word */
250
#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
251
#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
252
#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
253
#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
254
#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
255
#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
256
#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
257
 
258
/* TX Status Information Word */
259
#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
260
#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
261
#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
262
#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
263
#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
264
#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
265
#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
266
#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
267
 
268
/* DP83848C PHY Registers */
269
#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
270
#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
271
#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
272
#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
273
#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
274
#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
275
#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
276
#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
277
 
278
/* PHY Extended Registers */
279
#define PHY_REG_STS         0x10        /* Status Register                   */
280
#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
281
#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
282
#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
283
#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
284
#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
285
#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
286
#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
287
#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
288
#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
289
#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
290
#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
291
 
292
#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
293
#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
294
#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
295
#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
296
#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
297
 
298
#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
299
#define DP83848C_ID         0x20005C90  /* PHY Identifier                    */
300
 
301
// prototypes
302
portBASE_TYPE  vInitEMAC(void);
303
unsigned short ReadFrameBE_EMAC(void);
304
void           vIncrementTxLength(unsigned long ulLength);
305
void           CopyFromFrame_EMAC(void *Dest, unsigned short Size);
306
void           DummyReadFrame_EMAC(unsigned short Size);
307
unsigned short StartReadFrame(void);
308
void           EndReadFrame(void);
309
unsigned int   CheckFrameReceived(void);
310
void           vInitialiseSend(void);
311
unsigned int   Rdy4Tx(void);
312
void           vSendBufferToMAC(void);
313
void vEMACWaitForInput( void );
314
unsigned int uiGetEMACRxData( unsigned char *ucBuffer );
315
 
316
 
317
#endif
318
 
319
/*----------------------------------------------------------------------------
320
 * end of file
321
 *---------------------------------------------------------------------------*/
322
 

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