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581 |
jeremybenn |
/*
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* @file: EthDev_LPC17xx.h
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* @purpose: Ethernet Device Definitions for NXP LPC17xx
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* @version: V0.01
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* @date: 14. May 2009
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*----------------------------------------------------------------------------
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*
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* ARM Limited (ARM) is supplying this software for use with Cortex-M3
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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*/
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#ifndef __ETHDEV_LPC17XX_H
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#define __ETHDEV_LPC17XX_H
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#include <stdint.h>
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/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
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#define NUM_RX_FRAG 3 /* Num.of RX Fragments. */
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#define NUM_TX_FRAG 2 /* Num.of TX Fragments. */
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#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
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#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
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typedef struct { /* RX Descriptor struct */
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uint32_t Packet;
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uint32_t Ctrl;
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} RX_DESC_TypeDef;
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typedef struct { /* RX Status struct */
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uint32_t Info;
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uint32_t HashCRC;
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} RX_STAT_TypeDef;
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typedef struct { /* TX Descriptor struct */
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uint32_t Packet;
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uint32_t Ctrl;
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} TX_DESC_TypeDef;
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typedef struct { /* TX Status struct */
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uint32_t Info;
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} TX_STAT_TypeDef;
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/* EMAC variables located in AHB SRAM bank 1*/
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#define AHB_SRAM_BANK1_BASE 0x2007c000UL
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#define RX_DESC_BASE (AHB_SRAM_BANK1_BASE )
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#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*(2*4)) /* 2 * uint32_t, see RX_DESC_TypeDef */
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#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*(2*4)) /* 2 * uint32_t, see RX_STAT_TypeDef */
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#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*(2*4)) /* 2 * uint32_t, see TX_DESC_TypeDef */
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#define ETH_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*(1*4)) /* 1 * uint32_t, see TX_STAT_TypeDef */
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/* RX and TX descriptor and status definitions. */
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#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
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#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
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#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
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#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
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#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
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#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
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#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
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#define ETH_BUF(i) ( ETH_BUF_BASE + ETH_FRAG_SIZE*i )
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#define ETH_NUM_BUFFERS ( NUM_TX_FRAG + NUM_RX_FRAG + 1 ) /* There are in fact 2 more buffers than descriptors as the two Tx descriptors use the same buffer to speed up the uip Tx. */
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/* MAC Configuration Register 1 */
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#define MAC1_REC_EN 0x00000001 /* Receive Enable */
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#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
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#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
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#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
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#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
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#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
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#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
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#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
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#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
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#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
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#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
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/* MAC Configuration Register 2 */
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#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
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#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
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#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
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#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
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#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
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#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
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#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
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#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
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#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
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#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
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#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
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#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
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#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
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/* Back-to-Back Inter-Packet-Gap Register */
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#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
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#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
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/* Non Back-to-Back Inter-Packet-Gap Register */
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#define IPGR_DEF 0x00000012 /* Recommended value */
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/* Collision Window/Retry Register */
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#define CLRT_DEF 0x0000370F /* Default value */
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| 112 |
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/* PHY Support Register */
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#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
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#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
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/* Test Register */
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#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
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#define TEST_TST_PAUSE 0x00000002 /* Test Pause */
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#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
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| 121 |
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/* MII Management Configuration Register */
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#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
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#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
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#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
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#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
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/* MII Management Command Register */
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#define MCMD_READ 0x00000001 /* MII Read */
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#define MCMD_SCAN 0x00000002 /* MII Scan continuously */
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#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
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#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
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/* MII Management Address Register */
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#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
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#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
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/* MII Management Indicators Register */
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#define MIND_BUSY 0x00000001 /* MII is Busy */
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#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
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#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
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#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
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/* Command Register */
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#define CR_RX_EN 0x00000001 /* Enable Receive */
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#define CR_TX_EN 0x00000002 /* Enable Transmit */
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#define CR_REG_RES 0x00000008 /* Reset Host Registers */
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#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
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#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
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#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
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#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
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#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
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#define CR_RMII 0x00000200 /* Reduced MII Interface */
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#define CR_FULL_DUP 0x00000400 /* Full Duplex */
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/* Status Register */
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#define SR_RX_EN 0x00000001 /* Enable Receive */
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#define SR_TX_EN 0x00000002 /* Enable Transmit */
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/* Transmit Status Vector 0 Register */
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#define TSV0_CRC_ERR 0x00000001 /* CRC error */
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#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
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#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
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#define TSV0_DONE 0x00000008 /* Tramsmission Completed */
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#define TSV0_MCAST 0x00000010 /* Multicast Destination */
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#define TSV0_BCAST 0x00000020 /* Broadcast Destination */
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#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
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#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
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#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
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#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
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#define TSV0_GIANT 0x00000400 /* Giant Frame */
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#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
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#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
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#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
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#define TSV0_PAUSE 0x20000000 /* Pause Frame */
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#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
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#define TSV0_VLAN 0x80000000 /* VLAN Frame */
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/* Transmit Status Vector 1 Register */
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#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
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#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
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/* Receive Status Vector Register */
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#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
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#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
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#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
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#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
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#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
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#define RSV_CRC_ERR 0x00100000 /* CRC Error */
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#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
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#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
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#define RSV_REC_OK 0x00800000 /* Frame Received OK */
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#define RSV_MCAST 0x01000000 /* Multicast Frame */
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#define RSV_BCAST 0x02000000 /* Broadcast Frame */
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#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
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#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
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#define RSV_PAUSE 0x10000000 /* Pause Frame */
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| 198 |
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#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
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| 199 |
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#define RSV_VLAN 0x40000000 /* VLAN Frame */
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/* Flow Control Counter Register */
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| 202 |
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#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
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#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
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| 205 |
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/* Flow Control Status Register */
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#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
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| 208 |
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/* Receive Filter Control Register */
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| 209 |
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#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
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| 210 |
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#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
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| 211 |
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#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
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| 212 |
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#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
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| 213 |
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#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
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| 214 |
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#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
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| 215 |
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#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
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| 216 |
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#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
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| 217 |
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| 218 |
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/* Receive Filter WoL Status/Clear Registers */
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| 219 |
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#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
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| 220 |
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#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
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| 221 |
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#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
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| 222 |
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#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
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| 223 |
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#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
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| 224 |
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#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
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| 225 |
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#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
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| 226 |
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#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
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| 227 |
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| 228 |
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/* Interrupt Status/Enable/Clear/Set Registers */
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| 229 |
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#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
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| 230 |
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#define INT_RX_ERR 0x00000002 /* Receive Error */
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| 231 |
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#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
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| 232 |
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#define INT_RX_DONE 0x00000008 /* Receive Done */
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| 233 |
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#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
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| 234 |
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#define INT_TX_ERR 0x00000020 /* Transmit Error */
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| 235 |
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#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
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| 236 |
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#define INT_TX_DONE 0x00000080 /* Transmit Done */
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| 237 |
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#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
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| 238 |
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#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
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| 239 |
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| 240 |
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/* Power Down Register */
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| 241 |
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#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
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| 242 |
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| 243 |
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/* RX Descriptor Control Word */
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| 244 |
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#define RCTRL_SIZE 0x000007FF /* Buffer size mask */
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| 245 |
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#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
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| 246 |
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| 247 |
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/* RX Status Hash CRC Word */
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| 248 |
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#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
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| 249 |
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#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
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| 250 |
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| 251 |
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/* RX Status Information Word */
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| 252 |
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#define RINFO_SIZE 0x000007FF /* Data size in bytes */
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| 253 |
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#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
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| 254 |
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#define RINFO_VLAN 0x00080000 /* VLAN Frame */
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| 255 |
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#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
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| 256 |
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#define RINFO_MCAST 0x00200000 /* Multicast Frame */
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| 257 |
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#define RINFO_BCAST 0x00400000 /* Broadcast Frame */
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| 258 |
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#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
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| 259 |
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#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
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| 260 |
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#define RINFO_LEN_ERR 0x02000000 /* Length Error */
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| 261 |
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#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
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| 262 |
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#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
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| 263 |
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#define RINFO_OVERRUN 0x10000000 /* Receive overrun */
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| 264 |
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#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
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| 265 |
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#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
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| 266 |
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#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
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| 267 |
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| 268 |
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#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
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| 269 |
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RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
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| 270 |
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| 271 |
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/* TX Descriptor Control Word */
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| 272 |
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#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
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| 273 |
|
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#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
|
| 274 |
|
|
#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
|
| 275 |
|
|
#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
|
| 276 |
|
|
#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
|
| 277 |
|
|
#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
|
| 278 |
|
|
#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
|
| 279 |
|
|
|
| 280 |
|
|
/* TX Status Information Word */
|
| 281 |
|
|
#define TINFO_COL_CNT 0x01E00000 /* Collision Count */
|
| 282 |
|
|
#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
|
| 283 |
|
|
#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
|
| 284 |
|
|
#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
|
| 285 |
|
|
#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
|
| 286 |
|
|
#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
|
| 287 |
|
|
#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
|
| 288 |
|
|
#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
|
| 289 |
|
|
|
| 290 |
|
|
/* ENET Device Revision ID */
|
| 291 |
|
|
#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
|
| 292 |
|
|
|
| 293 |
|
|
/* KSZ8721BL PHY Registers */
|
| 294 |
|
|
#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
|
| 295 |
|
|
#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
|
| 296 |
|
|
#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
|
| 297 |
|
|
#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
|
| 298 |
|
|
#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
|
| 299 |
|
|
#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
|
| 300 |
|
|
#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
|
| 301 |
|
|
#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
|
| 302 |
|
|
|
| 303 |
|
|
/* PHY Extended Registers */
|
| 304 |
|
|
#define PHY_REG_RECR 0x15 /* Receive Error Counter */
|
| 305 |
|
|
#define PHY_CTRLER 0x1f /* 100BASE-TX-PHY Controller */
|
| 306 |
|
|
|
| 307 |
|
|
#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
|
| 308 |
|
|
#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
|
| 309 |
|
|
#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
|
| 310 |
|
|
#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
|
| 311 |
|
|
#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
|
| 312 |
|
|
#define PHY_AUTO_NEG_COMPLETE 0x0020 /* Auto negotiation have finished. */
|
| 313 |
|
|
|
| 314 |
|
|
#define KS8721_DEF_ADR 0x0100 /* Default PHY device address */
|
| 315 |
|
|
#define KS8721_ID 0x00221619 /* PHY Identifier */
|
| 316 |
|
|
|
| 317 |
|
|
#endif
|
| 318 |
|
|
|
| 319 |
|
|
/*----------------------------------------------------------------------------
|
| 320 |
|
|
* end of file
|
| 321 |
|
|
*---------------------------------------------------------------------------*/
|
