| 1 |
582 |
jeremybenn |
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
|
| 2 |
|
|
* File Name : stm32f10x_adc.h
|
| 3 |
|
|
* Author : MCD Application Team
|
| 4 |
|
|
* Version : V2.0.1
|
| 5 |
|
|
* Date : 06/13/2008
|
| 6 |
|
|
* Description : This file contains all the functions prototypes for the
|
| 7 |
|
|
* ADC firmware library.
|
| 8 |
|
|
********************************************************************************
|
| 9 |
|
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
| 10 |
|
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
| 11 |
|
|
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
| 12 |
|
|
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
| 13 |
|
|
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
| 14 |
|
|
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
| 15 |
|
|
*******************************************************************************/
|
| 16 |
|
|
|
| 17 |
|
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
| 18 |
|
|
#ifndef __STM32F10x_ADC_H
|
| 19 |
|
|
#define __STM32F10x_ADC_H
|
| 20 |
|
|
|
| 21 |
|
|
/* Includes ------------------------------------------------------------------*/
|
| 22 |
|
|
#include "stm32f10x_map.h"
|
| 23 |
|
|
|
| 24 |
|
|
/* Exported types ------------------------------------------------------------*/
|
| 25 |
|
|
/* ADC Init structure definition */
|
| 26 |
|
|
typedef struct
|
| 27 |
|
|
{
|
| 28 |
|
|
u32 ADC_Mode;
|
| 29 |
|
|
FunctionalState ADC_ScanConvMode;
|
| 30 |
|
|
FunctionalState ADC_ContinuousConvMode;
|
| 31 |
|
|
u32 ADC_ExternalTrigConv;
|
| 32 |
|
|
u32 ADC_DataAlign;
|
| 33 |
|
|
u8 ADC_NbrOfChannel;
|
| 34 |
|
|
}ADC_InitTypeDef;
|
| 35 |
|
|
|
| 36 |
|
|
/* Exported constants --------------------------------------------------------*/
|
| 37 |
|
|
#define IS_ADC_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
|
| 38 |
|
|
((*(u32*)&(PERIPH)) == ADC2_BASE) || \
|
| 39 |
|
|
((*(u32*)&(PERIPH)) == ADC3_BASE))
|
| 40 |
|
|
|
| 41 |
|
|
#define IS_ADC_DMA_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
|
| 42 |
|
|
((*(u32*)&(PERIPH)) == ADC3_BASE))
|
| 43 |
|
|
|
| 44 |
|
|
/* ADC dual mode -------------------------------------------------------------*/
|
| 45 |
|
|
#define ADC_Mode_Independent ((u32)0x00000000)
|
| 46 |
|
|
#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
|
| 47 |
|
|
#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
|
| 48 |
|
|
#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
|
| 49 |
|
|
#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
|
| 50 |
|
|
#define ADC_Mode_InjecSimult ((u32)0x00050000)
|
| 51 |
|
|
#define ADC_Mode_RegSimult ((u32)0x00060000)
|
| 52 |
|
|
#define ADC_Mode_FastInterl ((u32)0x00070000)
|
| 53 |
|
|
#define ADC_Mode_SlowInterl ((u32)0x00080000)
|
| 54 |
|
|
#define ADC_Mode_AlterTrig ((u32)0x00090000)
|
| 55 |
|
|
|
| 56 |
|
|
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
| 57 |
|
|
((MODE) == ADC_Mode_RegInjecSimult) || \
|
| 58 |
|
|
((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
|
| 59 |
|
|
((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
|
| 60 |
|
|
((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
|
| 61 |
|
|
((MODE) == ADC_Mode_InjecSimult) || \
|
| 62 |
|
|
((MODE) == ADC_Mode_RegSimult) || \
|
| 63 |
|
|
((MODE) == ADC_Mode_FastInterl) || \
|
| 64 |
|
|
((MODE) == ADC_Mode_SlowInterl) || \
|
| 65 |
|
|
((MODE) == ADC_Mode_AlterTrig))
|
| 66 |
|
|
|
| 67 |
|
|
/* ADC extrenal trigger sources for regular channels conversion --------------*/
|
| 68 |
|
|
/* for ADC1 and ADC2 */
|
| 69 |
|
|
#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
|
| 70 |
|
|
#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
|
| 71 |
|
|
#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
|
| 72 |
|
|
#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
|
| 73 |
|
|
#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
|
| 74 |
|
|
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((u32)0x000C0000)
|
| 75 |
|
|
/* for ADC1, ADC2 and ADC3 */
|
| 76 |
|
|
#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
|
| 77 |
|
|
#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
|
| 78 |
|
|
/* for ADC3 */
|
| 79 |
|
|
#define ADC_ExternalTrigConv_T3_CC1 ((u32)0x00000000)
|
| 80 |
|
|
#define ADC_ExternalTrigConv_T2_CC3 ((u32)0x00020000)
|
| 81 |
|
|
#define ADC_ExternalTrigConv_T8_CC1 ((u32)0x00060000)
|
| 82 |
|
|
#define ADC_ExternalTrigConv_T8_TRGO ((u32)0x00080000)
|
| 83 |
|
|
#define ADC_ExternalTrigConv_T5_CC1 ((u32)0x000A0000)
|
| 84 |
|
|
#define ADC_ExternalTrigConv_T5_CC3 ((u32)0x000C0000)
|
| 85 |
|
|
|
| 86 |
|
|
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
|
| 87 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
|
| 88 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
|
| 89 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
| 90 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
| 91 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
| 92 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
|
| 93 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_None) || \
|
| 94 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
| 95 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
| 96 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
|
| 97 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
|
| 98 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
|
| 99 |
|
|
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
|
| 100 |
|
|
|
| 101 |
|
|
/* ADC data align ------------------------------------------------------------*/
|
| 102 |
|
|
#define ADC_DataAlign_Right ((u32)0x00000000)
|
| 103 |
|
|
#define ADC_DataAlign_Left ((u32)0x00000800)
|
| 104 |
|
|
|
| 105 |
|
|
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
| 106 |
|
|
((ALIGN) == ADC_DataAlign_Left))
|
| 107 |
|
|
|
| 108 |
|
|
/* ADC channels --------------------------------------------------------------*/
|
| 109 |
|
|
#define ADC_Channel_0 ((u8)0x00)
|
| 110 |
|
|
#define ADC_Channel_1 ((u8)0x01)
|
| 111 |
|
|
#define ADC_Channel_2 ((u8)0x02)
|
| 112 |
|
|
#define ADC_Channel_3 ((u8)0x03)
|
| 113 |
|
|
#define ADC_Channel_4 ((u8)0x04)
|
| 114 |
|
|
#define ADC_Channel_5 ((u8)0x05)
|
| 115 |
|
|
#define ADC_Channel_6 ((u8)0x06)
|
| 116 |
|
|
#define ADC_Channel_7 ((u8)0x07)
|
| 117 |
|
|
#define ADC_Channel_8 ((u8)0x08)
|
| 118 |
|
|
#define ADC_Channel_9 ((u8)0x09)
|
| 119 |
|
|
#define ADC_Channel_10 ((u8)0x0A)
|
| 120 |
|
|
#define ADC_Channel_11 ((u8)0x0B)
|
| 121 |
|
|
#define ADC_Channel_12 ((u8)0x0C)
|
| 122 |
|
|
#define ADC_Channel_13 ((u8)0x0D)
|
| 123 |
|
|
#define ADC_Channel_14 ((u8)0x0E)
|
| 124 |
|
|
#define ADC_Channel_15 ((u8)0x0F)
|
| 125 |
|
|
#define ADC_Channel_16 ((u8)0x10)
|
| 126 |
|
|
#define ADC_Channel_17 ((u8)0x11)
|
| 127 |
|
|
|
| 128 |
|
|
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
|
| 129 |
|
|
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
|
| 130 |
|
|
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
|
| 131 |
|
|
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
|
| 132 |
|
|
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
|
| 133 |
|
|
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
|
| 134 |
|
|
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
|
| 135 |
|
|
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
|
| 136 |
|
|
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
|
| 137 |
|
|
|
| 138 |
|
|
/* ADC sampling times --------------------------------------------------------*/
|
| 139 |
|
|
#define ADC_SampleTime_1Cycles5 ((u8)0x00)
|
| 140 |
|
|
#define ADC_SampleTime_7Cycles5 ((u8)0x01)
|
| 141 |
|
|
#define ADC_SampleTime_13Cycles5 ((u8)0x02)
|
| 142 |
|
|
#define ADC_SampleTime_28Cycles5 ((u8)0x03)
|
| 143 |
|
|
#define ADC_SampleTime_41Cycles5 ((u8)0x04)
|
| 144 |
|
|
#define ADC_SampleTime_55Cycles5 ((u8)0x05)
|
| 145 |
|
|
#define ADC_SampleTime_71Cycles5 ((u8)0x06)
|
| 146 |
|
|
#define ADC_SampleTime_239Cycles5 ((u8)0x07)
|
| 147 |
|
|
|
| 148 |
|
|
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
|
| 149 |
|
|
((TIME) == ADC_SampleTime_7Cycles5) || \
|
| 150 |
|
|
((TIME) == ADC_SampleTime_13Cycles5) || \
|
| 151 |
|
|
((TIME) == ADC_SampleTime_28Cycles5) || \
|
| 152 |
|
|
((TIME) == ADC_SampleTime_41Cycles5) || \
|
| 153 |
|
|
((TIME) == ADC_SampleTime_55Cycles5) || \
|
| 154 |
|
|
((TIME) == ADC_SampleTime_71Cycles5) || \
|
| 155 |
|
|
((TIME) == ADC_SampleTime_239Cycles5))
|
| 156 |
|
|
|
| 157 |
|
|
/* ADC extrenal trigger sources for injected channels conversion -------------*/
|
| 158 |
|
|
/* For ADC1 and ADC2 */
|
| 159 |
|
|
#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
|
| 160 |
|
|
#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
|
| 161 |
|
|
#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
|
| 162 |
|
|
#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
|
| 163 |
|
|
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((u32)0x00006000)
|
| 164 |
|
|
/* For ADC1, ADC2 and ADC3 */
|
| 165 |
|
|
#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
|
| 166 |
|
|
#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
|
| 167 |
|
|
#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
|
| 168 |
|
|
/* For ADC3 */
|
| 169 |
|
|
#define ADC_ExternalTrigInjecConv_T4_CC3 ((u32)0x00002000)
|
| 170 |
|
|
#define ADC_ExternalTrigInjecConv_T8_CC2 ((u32)0x00003000)
|
| 171 |
|
|
#define ADC_ExternalTrigInjecConv_T8_CC4 ((u32)0x00004000)
|
| 172 |
|
|
#define ADC_ExternalTrigInjecConv_T5_TRGO ((u32)0x00005000)
|
| 173 |
|
|
#define ADC_ExternalTrigInjecConv_T5_CC4 ((u32)0x00006000)
|
| 174 |
|
|
|
| 175 |
|
|
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
|
| 176 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
|
| 177 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
| 178 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
| 179 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
| 180 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
| 181 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
|
| 182 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
|
| 183 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
| 184 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
|
| 185 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
|
| 186 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
|
| 187 |
|
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
|
| 188 |
|
|
|
| 189 |
|
|
/* ADC injected channel selection --------------------------------------------*/
|
| 190 |
|
|
#define ADC_InjectedChannel_1 ((u8)0x14)
|
| 191 |
|
|
#define ADC_InjectedChannel_2 ((u8)0x18)
|
| 192 |
|
|
#define ADC_InjectedChannel_3 ((u8)0x1C)
|
| 193 |
|
|
#define ADC_InjectedChannel_4 ((u8)0x20)
|
| 194 |
|
|
|
| 195 |
|
|
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
| 196 |
|
|
((CHANNEL) == ADC_InjectedChannel_2) || \
|
| 197 |
|
|
((CHANNEL) == ADC_InjectedChannel_3) || \
|
| 198 |
|
|
((CHANNEL) == ADC_InjectedChannel_4))
|
| 199 |
|
|
|
| 200 |
|
|
/* ADC analog watchdog selection ---------------------------------------------*/
|
| 201 |
|
|
#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
|
| 202 |
|
|
#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
|
| 203 |
|
|
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
|
| 204 |
|
|
#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
|
| 205 |
|
|
#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
|
| 206 |
|
|
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
|
| 207 |
|
|
#define ADC_AnalogWatchdog_None ((u32)0x00000000)
|
| 208 |
|
|
|
| 209 |
|
|
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
| 210 |
|
|
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
| 211 |
|
|
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
| 212 |
|
|
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
| 213 |
|
|
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
| 214 |
|
|
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
| 215 |
|
|
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
| 216 |
|
|
|
| 217 |
|
|
/* ADC interrupts definition -------------------------------------------------*/
|
| 218 |
|
|
#define ADC_IT_EOC ((u16)0x0220)
|
| 219 |
|
|
#define ADC_IT_AWD ((u16)0x0140)
|
| 220 |
|
|
#define ADC_IT_JEOC ((u16)0x0480)
|
| 221 |
|
|
|
| 222 |
|
|
#define IS_ADC_IT(IT) ((((IT) & (u16)0xF81F) == 0x00) && ((IT) != 0x00))
|
| 223 |
|
|
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
| 224 |
|
|
((IT) == ADC_IT_JEOC))
|
| 225 |
|
|
|
| 226 |
|
|
/* ADC flags definition ------------------------------------------------------*/
|
| 227 |
|
|
#define ADC_FLAG_AWD ((u8)0x01)
|
| 228 |
|
|
#define ADC_FLAG_EOC ((u8)0x02)
|
| 229 |
|
|
#define ADC_FLAG_JEOC ((u8)0x04)
|
| 230 |
|
|
#define ADC_FLAG_JSTRT ((u8)0x08)
|
| 231 |
|
|
#define ADC_FLAG_STRT ((u8)0x10)
|
| 232 |
|
|
|
| 233 |
|
|
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (u8)0xE0) == 0x00) && ((FLAG) != 0x00))
|
| 234 |
|
|
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
|
| 235 |
|
|
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
|
| 236 |
|
|
((FLAG) == ADC_FLAG_STRT))
|
| 237 |
|
|
|
| 238 |
|
|
/* ADC thresholds ------------------------------------------------------------*/
|
| 239 |
|
|
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
| 240 |
|
|
|
| 241 |
|
|
/* ADC injected offset -------------------------------------------------------*/
|
| 242 |
|
|
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
| 243 |
|
|
|
| 244 |
|
|
/* ADC injected length -------------------------------------------------------*/
|
| 245 |
|
|
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
| 246 |
|
|
|
| 247 |
|
|
/* ADC injected rank ---------------------------------------------------------*/
|
| 248 |
|
|
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
| 249 |
|
|
|
| 250 |
|
|
/* ADC regular length --------------------------------------------------------*/
|
| 251 |
|
|
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
| 252 |
|
|
|
| 253 |
|
|
/* ADC regular rank ----------------------------------------------------------*/
|
| 254 |
|
|
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
|
| 255 |
|
|
|
| 256 |
|
|
/* ADC regular discontinuous mode number -------------------------------------*/
|
| 257 |
|
|
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
| 258 |
|
|
|
| 259 |
|
|
/* Exported macro ------------------------------------------------------------*/
|
| 260 |
|
|
/* Exported functions ------------------------------------------------------- */
|
| 261 |
|
|
void ADC_DeInit(ADC_TypeDef* ADCx);
|
| 262 |
|
|
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
| 263 |
|
|
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
| 264 |
|
|
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
| 265 |
|
|
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
| 266 |
|
|
void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
|
| 267 |
|
|
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
|
| 268 |
|
|
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
|
| 269 |
|
|
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
| 270 |
|
|
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
| 271 |
|
|
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
| 272 |
|
|
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
| 273 |
|
|
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
|
| 274 |
|
|
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
| 275 |
|
|
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
|
| 276 |
|
|
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
| 277 |
|
|
u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
| 278 |
|
|
u32 ADC_GetDualModeConversionValue(void);
|
| 279 |
|
|
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
| 280 |
|
|
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
| 281 |
|
|
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
|
| 282 |
|
|
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
| 283 |
|
|
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
| 284 |
|
|
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
| 285 |
|
|
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
|
| 286 |
|
|
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
|
| 287 |
|
|
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
|
| 288 |
|
|
u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
|
| 289 |
|
|
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
|
| 290 |
|
|
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
|
| 291 |
|
|
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
|
| 292 |
|
|
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
| 293 |
|
|
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
|
| 294 |
|
|
void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
|
| 295 |
|
|
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
|
| 296 |
|
|
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
|
| 297 |
|
|
|
| 298 |
|
|
#endif /*__STM32F10x_ADC_H */
|
| 299 |
|
|
|
| 300 |
|
|
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
|
