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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name          : stm32f10x_fsmc.h
* Author             : MCD Application Team
* Version            : V2.0.1
* Date               : 06/13/2008
* Description        : This file contains all the functions prototypes for the
*                      FSMC firmware library.
********************************************************************************
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F10x_FSMC_H
#define __STM32F10x_FSMC_H
 
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_map.h"
 
/* Exported types ------------------------------------------------------------*/
/* Timing parameters For NOR/SRAM Banks */
typedef struct
{
  u32 FSMC_AddressSetupTime;
  u32 FSMC_AddressHoldTime;
  u32 FSMC_DataSetupTime;
  u32 FSMC_BusTurnAroundDuration;
  u32 FSMC_CLKDivision;
  u32 FSMC_DataLatency;
  u32 FSMC_AccessMode;
}FSMC_NORSRAMTimingInitTypeDef;
 
/* FSMC NOR/SRAM Init structure definition */
typedef struct
{
  u32 FSMC_Bank;
  u32 FSMC_DataAddressMux;
  u32 FSMC_MemoryType;
  u32 FSMC_MemoryDataWidth;
  u32 FSMC_BurstAccessMode;
  u32 FSMC_WaitSignalPolarity;
  u32 FSMC_WrapMode;
  u32 FSMC_WaitSignalActive;
  u32 FSMC_WriteOperation;
  u32 FSMC_WaitSignal;
  u32 FSMC_ExtendedMode;
  u32 FSMC_AsyncWait;
  u32 FSMC_WriteBurst;
  /* Timing Parameters for write and read access if the  ExtendedMode is not used*/
  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;
  /* Timing Parameters for write access if the  ExtendedMode is used*/
  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;
}FSMC_NORSRAMInitTypeDef;
 
/* Timing parameters For FSMC NAND and PCCARD Banks */
typedef struct
{
  u32 FSMC_SetupTime;
  u32 FSMC_WaitSetupTime;
  u32 FSMC_HoldSetupTime;
  u32 FSMC_HiZSetupTime;
}FSMC_NAND_PCCARDTimingInitTypeDef;
 
/* FSMC NAND Init structure definition */
typedef struct
{
  u32 FSMC_Bank;
  u32 FSMC_Waitfeature;
  u32 FSMC_MemoryDataWidth;
  u32 FSMC_ECC;
  u32 FSMC_ECCPageSize;
  u32 FSMC_AddressLowMapping;
  u32 FSMC_TCLRSetupTime;
  u32 FSMC_TARSetupTime;
  /* FSMC Common Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;
  /* FSMC Attribute Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;
}FSMC_NANDInitTypeDef;
 
/* FSMC PCCARD Init structure definition */
typedef struct
{
  u32 FSMC_Waitfeature;
  u32 FSMC_AddressLowMapping;
  u32 FSMC_TCLRSetupTime;
  u32 FSMC_TARSetupTime;
  /* FSMC Common Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;
  /* FSMC Attribute Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;
  /* FSMC IO Space Timing */
  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct;
}FSMC_PCCARDInitTypeDef;
 
/* Exported constants --------------------------------------------------------*/
/*-------------------------------FSMC Banks definitions ----------------------*/
#define FSMC_Bank1_NORSRAM1                             ((u32)0x00000000)
#define FSMC_Bank1_NORSRAM2                             ((u32)0x00000002)
#define FSMC_Bank1_NORSRAM3                             ((u32)0x00000004)
#define FSMC_Bank1_NORSRAM4                             ((u32)0x00000006)
#define FSMC_Bank2_NAND                                 ((u32)0x00000010)
#define FSMC_Bank3_NAND                                 ((u32)0x00000100)
#define FSMC_Bank4_PCCARD                               ((u32)0x00001000)
 
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
                                    ((BANK) == FSMC_Bank1_NORSRAM4))
 
 
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
                                 ((BANK) == FSMC_Bank3_NAND))
 
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
                                    ((BANK) == FSMC_Bank3_NAND) || \
                                    ((BANK) == FSMC_Bank4_PCCARD))
 
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
                               ((BANK) == FSMC_Bank3_NAND) || \
                               ((BANK) == FSMC_Bank4_PCCARD))
 
 
/*------------------------------- NOR/SRAM Banks -----------------------------*/
/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/
#define FSMC_DataAddressMux_Disable                       ((u32)0x00000000)
#define FSMC_DataAddressMux_Enable                        ((u32)0x00000002)
 
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
                          ((MUX) == FSMC_DataAddressMux_Enable))
 
/* FSMC Memory Type ----------------------------------------------------------*/
#define FSMC_MemoryType_SRAM                            ((u32)0x00000000)
#define FSMC_MemoryType_CRAM                            ((u32)0x00000004)
#define FSMC_MemoryType_NOR                             ((u32)0x00000008)
#define FSMC_MemoryType_COSMORAM                        ((u32)0x0000000C)
 
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
                                ((MEMORY) == FSMC_MemoryType_CRAM)|| \
                                ((MEMORY) == FSMC_MemoryType_NOR)|| \
                                ((MEMORY) == FSMC_MemoryType_COSMORAM))
 
/* FSMC  Data Width ----------------------------------------------------------*/
#define FSMC_MemoryDataWidth_8b                         ((u32)0x00000000)
#define FSMC_MemoryDataWidth_16b                        ((u32)0x00000010)
 
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
 
 
/* FSMC Burst Access Mode ----------------------------------------------------*/
#define FSMC_BurstAccessMode_Disable                    ((u32)0x00000000) 
#define FSMC_BurstAccessMode_Enable                     ((u32)0x00000100)
 
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
                                  ((STATE) == FSMC_BurstAccessMode_Enable))
 
/* FSMC Wait Signal Polarity -------------------------------------------------*/
#define FSMC_WaitSignalPolarity_Low                     ((u32)0x00000000)
#define FSMC_WaitSignalPolarity_High                    ((u32)0x00000200)
 
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))
 
/* FSMC Wrap Mode ------------------------------------------------------------*/
#define FSMC_WrapMode_Disable                           ((u32)0x00000000)
#define FSMC_WrapMode_Enable                            ((u32)0x00000400) 
 
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
                                 ((MODE) == FSMC_WrapMode_Enable))
 
/* FSMC Wait Timing ----------------------------------------------------------*/
#define FSMC_WaitSignalActive_BeforeWaitState           ((u32)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState           ((u32)0x00000800) 
 
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
 
/* FSMC Write Operation ------------------------------------------------------*/
#define FSMC_WriteOperation_Disable                     ((u32)0x00000000)
#define FSMC_WriteOperation_Enable                      ((u32)0x00001000)
 
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
                                            ((OPERATION) == FSMC_WriteOperation_Enable))
 
/* FSMC Wait Signal ----------------------------------------------------------*/
#define FSMC_WaitSignal_Disable                         ((u32)0x00000000)
#define FSMC_WaitSignal_Enable                          ((u32)0x00002000) 
 
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
 
/* FSMC Extended Mode --------------------------------------------------------*/
#define FSMC_ExtendedMode_Disable                       ((u32)0x00000000)
#define FSMC_ExtendedMode_Enable                        ((u32)0x00004000)                                  
 
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
                                     ((MODE) == FSMC_ExtendedMode_Enable))
 
/* FSMC Asynchronous Wait ----------------------------------------------------*/
#define FSMC_AsyncWait_Disable                          ((u32)0x00000000)
#define FSMC_AsyncWait_Enable                           ((u32)0x00008000)
 
#define IS_FSMC_ASYNC_WAIT(WAIT) (((WAIT) == FSMC_AsyncWait_Disable) || \
                                  ((WAIT) == FSMC_AsyncWait_Enable))
 
/* FSMC Write Burst ----------------------------------------------------------*/
#define FSMC_WriteBurst_Disable                         ((u32)0x00000000)
#define FSMC_WriteBurst_Enable                          ((u32)0x00080000) 
 
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
                                    ((BURST) == FSMC_WriteBurst_Enable))
 
/* FSMC Address Setup Time ---------------------------------------------------*/
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
 
/* FSMC Address Hold Time ----------------------------------------------------*/
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
 
/* FSMC Data Setup Time ------------------------------------------------------*/
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
 
/* FSMC Bus Turn around Duration ---------------------------------------------*/
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
 
/* FSMC CLK Division ---------------------------------------------------------*/
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
 
/* FSMC Data Latency ---------------------------------------------------------*/
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
 
/* FSMC Access Mode ----------------------------------------------------------*/
#define FSMC_AccessMode_A                               ((u32)0x00000000)
#define FSMC_AccessMode_B                               ((u32)0x10000000) 
#define FSMC_AccessMode_C                               ((u32)0x20000000)
#define FSMC_AccessMode_D                               ((u32)0x30000000)
 
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
                                   ((MODE) == FSMC_AccessMode_B) || \
                                   ((MODE) == FSMC_AccessMode_C) || \
                                   ((MODE) == FSMC_AccessMode_D))
 
/*----------------------------- NAND and PCCARD Banks ------------------------*/
/* FSMC Wait feature ---------------------------------------------------------*/
#define FSMC_Waitfeature_Disable                        ((u32)0x00000000)
#define FSMC_Waitfeature_Enable                         ((u32)0x00000002)
 
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
                                       ((FEATURE) == FSMC_Waitfeature_Enable))
 
/* FSMC Memory Data Width ----------------------------------------------------*/
#define FSMC_MemoryDataWidth_8b                         ((u32)0x00000000)
#define FSMC_MemoryDataWidth_16b                        ((u32)0x00000010)
 
#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
                                   ((WIDTH) == FSMC_MemoryDataWidth_16b))
 
/* FSMC ECC ------------------------------------------------------------------*/
#define FSMC_ECC_Disable                                ((u32)0x00000000)
#define FSMC_ECC_Enable                                 ((u32)0x00000040)
 
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
                                  ((STATE) == FSMC_ECC_Enable))
 
/* FSMC ECC Page Size --------------------------------------------------------*/
#define FSMC_ECCPageSize_256Bytes                       ((u32)0x00000000)
#define FSMC_ECCPageSize_512Bytes                       ((u32)0x00020000)
#define FSMC_ECCPageSize_1024Bytes                      ((u32)0x00040000)
#define FSMC_ECCPageSize_2048Bytes                      ((u32)0x00060000)
#define FSMC_ECCPageSize_4096Bytes                      ((u32)0x00080000)
#define FSMC_ECCPageSize_8192Bytes                      ((u32)0x000A0000)
 
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
 
/* FSMC Address Low Mapping --------------------------------------------------*/
#define FSMC_AddressLowMapping_Direct                   ((u32)0x00000000)
#define FSMC_AddressLowMapping_InDirect                 ((u32)0x00000100)
 
#define IS_FSMC_ADDRESS_LOW_MAPPING(MAPPING) (((MAPPING) == FSMC_AddressLowMapping_Direct) || \
                                              ((MAPPING) == FSMC_AddressLowMapping_InDirect))
/* FSMC TCLR Setup Time ------------------------------------------------------*/
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
 
/* FSMC TAR Setup Time -------------------------------------------------------*/
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
 
/* FSMC Setup Time ----------------------------------------------------*/
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
 
/* FSMC Wait Setup Time -----------------------------------------------*/
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
 
/* FSMC Hold Setup Time -----------------------------------------------*/
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
 
/* FSMC HiZ Setup Time ------------------------------------------------*/
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
 
/* FSMC Interrupt sources ----------------------------------------------------*/
#define FSMC_IT_RisingEdge                              ((u32)0x00000008)
#define FSMC_IT_Level                                   ((u32)0x00000010)
#define FSMC_IT_FallingEdge                             ((u32)0x00000020)
 
#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
 
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
                            ((IT) == FSMC_IT_Level) || \
                            ((IT) == FSMC_IT_FallingEdge))
 
/* FSMC Flags ----------------------------------------------------------------*/
#define FSMC_FLAG_RisingEdge                            ((u32)0x00000001)
#define FSMC_FLAG_Level                                 ((u32)0x00000002)
#define FSMC_FLAG_FallingEdge                           ((u32)0x00000004)
#define FSMC_FLAG_FEMPT                                 ((u32)0x00000040)
 
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
                                ((FLAG) == FSMC_FLAG_Level) || \
                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
                                ((FLAG) == FSMC_FLAG_FEMPT))
 
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))                                                                                                                                                                                                                                                                                                                                  
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void FSMC_NORSRAMDeInit(u32 FSMC_Bank);
void FSMC_NANDDeInit(u32 FSMC_Bank);
void FSMC_PCCARDDeInit(void);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState);
void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState);
void FSMC_PCCARDCmd(FunctionalState NewState);
void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState);
u32 FSMC_GetECC(u32 FSMC_Bank);
void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState);
FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG);
void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG);
ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT);
void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT);
 
#endif /*__STM32F10x_FSMC_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_STM32F103_GCC_Rowley/] [ST Library/] [inc/] [stm32f10x_fsmc.h] - Blame information for rev 582

Line No.	Rev	Author	Line
1	582	jeremybenn	`/****************** (C) COPYRIGHT 2008 STMicroelectronics ******************`
2			`* File Name : stm32f10x_fsmc.h`
3			`* Author : MCD Application Team`
4			`* Version : V2.0.1`
5			`* Date : 06/13/2008`
6			`* Description : This file contains all the functions prototypes for the`
7			`* FSMC firmware library.`
8			`********************************************************************************`
9			`* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS`
10			`* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.`
11			`* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,`
12			`* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE`
13			`* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING`
14			`* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.`
15			`*******************************************************************************/`
16
17			`/* Define to prevent recursive inclusion -------------------------------------*/`
18			`#ifndef __STM32F10x_FSMC_H`
19			`#define __STM32F10x_FSMC_H`
20
21			`/* Includes ------------------------------------------------------------------*/`
22			`#include "stm32f10x_map.h"`
23
24			`/* Exported types ------------------------------------------------------------*/`
25			`/* Timing parameters For NOR/SRAM Banks */`
26			`typedef struct`
27			`{`
28			`u32 FSMC_AddressSetupTime;`
29			`u32 FSMC_AddressHoldTime;`
30			`u32 FSMC_DataSetupTime;`
31			`u32 FSMC_BusTurnAroundDuration;`
32			`u32 FSMC_CLKDivision;`
33			`u32 FSMC_DataLatency;`
34			`u32 FSMC_AccessMode;`
35			`}FSMC_NORSRAMTimingInitTypeDef;`
36
37			`/* FSMC NOR/SRAM Init structure definition */`
38			`typedef struct`
39			`{`
40			`u32 FSMC_Bank;`
41			`u32 FSMC_DataAddressMux;`
42			`u32 FSMC_MemoryType;`
43			`u32 FSMC_MemoryDataWidth;`
44			`u32 FSMC_BurstAccessMode;`
45			`u32 FSMC_WaitSignalPolarity;`
46			`u32 FSMC_WrapMode;`
47			`u32 FSMC_WaitSignalActive;`
48			`u32 FSMC_WriteOperation;`
49			`u32 FSMC_WaitSignal;`
50			`u32 FSMC_ExtendedMode;`
51			`u32 FSMC_AsyncWait;`
52			`u32 FSMC_WriteBurst;`
53			`/* Timing Parameters for write and read access if the ExtendedMode is not used*/`
54			`FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;`
55			`/* Timing Parameters for write access if the ExtendedMode is used*/`
56			`FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;`
57			`}FSMC_NORSRAMInitTypeDef;`
58
59			`/* Timing parameters For FSMC NAND and PCCARD Banks */`
60			`typedef struct`
61			`{`
62			`u32 FSMC_SetupTime;`
63			`u32 FSMC_WaitSetupTime;`
64			`u32 FSMC_HoldSetupTime;`
65			`u32 FSMC_HiZSetupTime;`
66			`}FSMC_NAND_PCCARDTimingInitTypeDef;`
67
68			`/* FSMC NAND Init structure definition */`
69			`typedef struct`
70			`{`
71			`u32 FSMC_Bank;`
72			`u32 FSMC_Waitfeature;`
73			`u32 FSMC_MemoryDataWidth;`
74			`u32 FSMC_ECC;`
75			`u32 FSMC_ECCPageSize;`
76			`u32 FSMC_AddressLowMapping;`
77			`u32 FSMC_TCLRSetupTime;`
78			`u32 FSMC_TARSetupTime;`
79			`/* FSMC Common Space Timing */`
80			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;`
81			`/* FSMC Attribute Space Timing */`
82			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;`
83			`}FSMC_NANDInitTypeDef;`
84
85			`/* FSMC PCCARD Init structure definition */`
86			`typedef struct`
87			`{`
88			`u32 FSMC_Waitfeature;`
89			`u32 FSMC_AddressLowMapping;`
90			`u32 FSMC_TCLRSetupTime;`
91			`u32 FSMC_TARSetupTime;`
92			`/* FSMC Common Space Timing */`
93			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;`
94			`/* FSMC Attribute Space Timing */`
95			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;`
96			`/* FSMC IO Space Timing */`
97			`FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct;`
98			`}FSMC_PCCARDInitTypeDef;`
99
100			`/* Exported constants --------------------------------------------------------*/`
101			`/-------------------------------FSMC Banks definitions ----------------------/`
102			`#define FSMC_Bank1_NORSRAM1 ((u32)0x00000000)`
103			`#define FSMC_Bank1_NORSRAM2 ((u32)0x00000002)`
104			`#define FSMC_Bank1_NORSRAM3 ((u32)0x00000004)`
105			`#define FSMC_Bank1_NORSRAM4 ((u32)0x00000006)`
106			`#define FSMC_Bank2_NAND ((u32)0x00000010)`
107			`#define FSMC_Bank3_NAND ((u32)0x00000100)`
108			`#define FSMC_Bank4_PCCARD ((u32)0x00001000)`
109
110			`#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) \|\| \`
111			`((BANK) == FSMC_Bank1_NORSRAM2) \|\| \`
112			`((BANK) == FSMC_Bank1_NORSRAM3) \|\| \`
113			`((BANK) == FSMC_Bank1_NORSRAM4))`
114
115
116			`#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) \|\| \`
117			`((BANK) == FSMC_Bank3_NAND))`
118
119			`#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) \|\| \`
120			`((BANK) == FSMC_Bank3_NAND) \|\| \`
121			`((BANK) == FSMC_Bank4_PCCARD))`
122
123			`#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) \|\| \`
124			`((BANK) == FSMC_Bank3_NAND) \|\| \`
125			`((BANK) == FSMC_Bank4_PCCARD))`
126
127
128			`/------------------------------- NOR/SRAM Banks -----------------------------/`
129			`/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/`
130			`#define FSMC_DataAddressMux_Disable ((u32)0x00000000)`
131			`#define FSMC_DataAddressMux_Enable ((u32)0x00000002)`
132
133			`#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) \|\| \`
134			`((MUX) == FSMC_DataAddressMux_Enable))`
135
136			`/* FSMC Memory Type ----------------------------------------------------------*/`
137			`#define FSMC_MemoryType_SRAM ((u32)0x00000000)`
138			`#define FSMC_MemoryType_CRAM ((u32)0x00000004)`
139			`#define FSMC_MemoryType_NOR ((u32)0x00000008)`
140			`#define FSMC_MemoryType_COSMORAM ((u32)0x0000000C)`
141
142			`#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) \|\| \`
143			`((MEMORY) == FSMC_MemoryType_CRAM)\|\| \`
144			`((MEMORY) == FSMC_MemoryType_NOR)\|\| \`
145			`((MEMORY) == FSMC_MemoryType_COSMORAM))`
146
147			`/* FSMC Data Width ----------------------------------------------------------*/`
148			`#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)`
149			`#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)`
150
151			`#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) \|\| \`
152			`((WIDTH) == FSMC_MemoryDataWidth_16b))`
153
154
155			`/* FSMC Burst Access Mode ----------------------------------------------------*/`
156			`#define FSMC_BurstAccessMode_Disable ((u32)0x00000000)`
157			`#define FSMC_BurstAccessMode_Enable ((u32)0x00000100)`
158
159			`#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) \|\| \`
160			`((STATE) == FSMC_BurstAccessMode_Enable))`
161
162			`/* FSMC Wait Signal Polarity -------------------------------------------------*/`
163			`#define FSMC_WaitSignalPolarity_Low ((u32)0x00000000)`
164			`#define FSMC_WaitSignalPolarity_High ((u32)0x00000200)`
165
166			`#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) \|\| \`
167			`((POLARITY) == FSMC_WaitSignalPolarity_High))`
168
169			`/* FSMC Wrap Mode ------------------------------------------------------------*/`
170			`#define FSMC_WrapMode_Disable ((u32)0x00000000)`
171			`#define FSMC_WrapMode_Enable ((u32)0x00000400)`
172
173			`#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) \|\| \`
174			`((MODE) == FSMC_WrapMode_Enable))`
175
176			`/* FSMC Wait Timing ----------------------------------------------------------*/`
177			`#define FSMC_WaitSignalActive_BeforeWaitState ((u32)0x00000000)`
178			`#define FSMC_WaitSignalActive_DuringWaitState ((u32)0x00000800)`
179
180			`#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) \|\| \`
181			`((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))`
182
183			`/* FSMC Write Operation ------------------------------------------------------*/`
184			`#define FSMC_WriteOperation_Disable ((u32)0x00000000)`
185			`#define FSMC_WriteOperation_Enable ((u32)0x00001000)`
186
187			`#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) \|\| \`
188			`((OPERATION) == FSMC_WriteOperation_Enable))`
189
190			`/* FSMC Wait Signal ----------------------------------------------------------*/`
191			`#define FSMC_WaitSignal_Disable ((u32)0x00000000)`
192			`#define FSMC_WaitSignal_Enable ((u32)0x00002000)`
193
194			`#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) \|\| \`
195			`((SIGNAL) == FSMC_WaitSignal_Enable))`
196
197			`/* FSMC Extended Mode --------------------------------------------------------*/`
198			`#define FSMC_ExtendedMode_Disable ((u32)0x00000000)`
199			`#define FSMC_ExtendedMode_Enable ((u32)0x00004000)`
200
201			`#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) \|\| \`
202			`((MODE) == FSMC_ExtendedMode_Enable))`
203
204			`/* FSMC Asynchronous Wait ----------------------------------------------------*/`
205			`#define FSMC_AsyncWait_Disable ((u32)0x00000000)`
206			`#define FSMC_AsyncWait_Enable ((u32)0x00008000)`
207
208			`#define IS_FSMC_ASYNC_WAIT(WAIT) (((WAIT) == FSMC_AsyncWait_Disable) \|\| \`
209			`((WAIT) == FSMC_AsyncWait_Enable))`
210
211			`/* FSMC Write Burst ----------------------------------------------------------*/`
212			`#define FSMC_WriteBurst_Disable ((u32)0x00000000)`
213			`#define FSMC_WriteBurst_Enable ((u32)0x00080000)`
214
215			`#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) \|\| \`
216			`((BURST) == FSMC_WriteBurst_Enable))`
217
218			`/* FSMC Address Setup Time ---------------------------------------------------*/`
219			`#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)`
220
221			`/* FSMC Address Hold Time ----------------------------------------------------*/`
222			`#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)`
223
224			`/* FSMC Data Setup Time ------------------------------------------------------*/`
225			`#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))`
226
227			`/* FSMC Bus Turn around Duration ---------------------------------------------*/`
228			`#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)`
229
230			`/* FSMC CLK Division ---------------------------------------------------------*/`
231			`#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)`
232
233			`/* FSMC Data Latency ---------------------------------------------------------*/`
234			`#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)`
235
236			`/* FSMC Access Mode ----------------------------------------------------------*/`
237			`#define FSMC_AccessMode_A ((u32)0x00000000)`
238			`#define FSMC_AccessMode_B ((u32)0x10000000)`
239			`#define FSMC_AccessMode_C ((u32)0x20000000)`
240			`#define FSMC_AccessMode_D ((u32)0x30000000)`
241
242			`#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) \|\| \`
243			`((MODE) == FSMC_AccessMode_B) \|\| \`
244			`((MODE) == FSMC_AccessMode_C) \|\| \`
245			`((MODE) == FSMC_AccessMode_D))`
246
247			`/----------------------------- NAND and PCCARD Banks ------------------------/`
248			`/* FSMC Wait feature ---------------------------------------------------------*/`
249			`#define FSMC_Waitfeature_Disable ((u32)0x00000000)`
250			`#define FSMC_Waitfeature_Enable ((u32)0x00000002)`
251
252			`#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) \|\| \`
253			`((FEATURE) == FSMC_Waitfeature_Enable))`
254
255			`/* FSMC Memory Data Width ----------------------------------------------------*/`
256			`#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)`
257			`#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)`
258
259			`#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) \|\| \`
260			`((WIDTH) == FSMC_MemoryDataWidth_16b))`
261
262			`/* FSMC ECC ------------------------------------------------------------------*/`
263			`#define FSMC_ECC_Disable ((u32)0x00000000)`
264			`#define FSMC_ECC_Enable ((u32)0x00000040)`
265
266			`#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) \|\| \`
267			`((STATE) == FSMC_ECC_Enable))`
268
269			`/* FSMC ECC Page Size --------------------------------------------------------*/`
270			`#define FSMC_ECCPageSize_256Bytes ((u32)0x00000000)`
271			`#define FSMC_ECCPageSize_512Bytes ((u32)0x00020000)`
272			`#define FSMC_ECCPageSize_1024Bytes ((u32)0x00040000)`
273			`#define FSMC_ECCPageSize_2048Bytes ((u32)0x00060000)`
274			`#define FSMC_ECCPageSize_4096Bytes ((u32)0x00080000)`
275			`#define FSMC_ECCPageSize_8192Bytes ((u32)0x000A0000)`
276
277			`#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) \|\| \`
278			`((SIZE) == FSMC_ECCPageSize_512Bytes) \|\| \`
279			`((SIZE) == FSMC_ECCPageSize_1024Bytes) \|\| \`
280			`((SIZE) == FSMC_ECCPageSize_2048Bytes) \|\| \`
281			`((SIZE) == FSMC_ECCPageSize_4096Bytes) \|\| \`
282			`((SIZE) == FSMC_ECCPageSize_8192Bytes))`
283
284			`/* FSMC Address Low Mapping --------------------------------------------------*/`
285			`#define FSMC_AddressLowMapping_Direct ((u32)0x00000000)`
286			`#define FSMC_AddressLowMapping_InDirect ((u32)0x00000100)`
287
288			`#define IS_FSMC_ADDRESS_LOW_MAPPING(MAPPING) (((MAPPING) == FSMC_AddressLowMapping_Direct) \|\| \`
289			`((MAPPING) == FSMC_AddressLowMapping_InDirect))`
290			`/* FSMC TCLR Setup Time ------------------------------------------------------*/`
291			`#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)`
292
293			`/* FSMC TAR Setup Time -------------------------------------------------------*/`
294			`#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)`
295
296			`/* FSMC Setup Time ----------------------------------------------------*/`
297			`#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)`
298
299			`/* FSMC Wait Setup Time -----------------------------------------------*/`
300			`#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)`
301
302			`/* FSMC Hold Setup Time -----------------------------------------------*/`
303			`#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)`
304
305			`/* FSMC HiZ Setup Time ------------------------------------------------*/`
306			`#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)`
307
308			`/* FSMC Interrupt sources ----------------------------------------------------*/`
309			`#define FSMC_IT_RisingEdge ((u32)0x00000008)`
310			`#define FSMC_IT_Level ((u32)0x00000010)`
311			`#define FSMC_IT_FallingEdge ((u32)0x00000020)`
312
313			`#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))`
314
315			`#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) \|\| \`
316			`((IT) == FSMC_IT_Level) \|\| \`
317			`((IT) == FSMC_IT_FallingEdge))`
318
319			`/* FSMC Flags ----------------------------------------------------------------*/`
320			`#define FSMC_FLAG_RisingEdge ((u32)0x00000001)`
321			`#define FSMC_FLAG_Level ((u32)0x00000002)`
322			`#define FSMC_FLAG_FallingEdge ((u32)0x00000004)`
323			`#define FSMC_FLAG_FEMPT ((u32)0x00000040)`
324
325			`#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) \|\| \`
326			`((FLAG) == FSMC_FLAG_Level) \|\| \`
327			`((FLAG) == FSMC_FLAG_FallingEdge) \|\| \`
328			`((FLAG) == FSMC_FLAG_FEMPT))`
329
330			`#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))`
331			`/* Exported macro ------------------------------------------------------------*/`
332			`/* Exported functions ------------------------------------------------------- */`
333			`void FSMC_NORSRAMDeInit(u32 FSMC_Bank);`
334			`void FSMC_NANDDeInit(u32 FSMC_Bank);`
335			`void FSMC_PCCARDDeInit(void);`
336			`void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);`
337			`void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);`
338			`void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);`
339			`void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);`
340			`void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);`
341			`void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);`
342			`void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState);`
343			`void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState);`
344			`void FSMC_PCCARDCmd(FunctionalState NewState);`
345			`void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState);`
346			`u32 FSMC_GetECC(u32 FSMC_Bank);`
347			`void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState);`
348			`FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG);`
349			`void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG);`
350			`ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT);`
351			`void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT);`
352
353			`#endif /__STM32F10x_FSMC_H /`
354
355			`/***************** (C) COPYRIGHT 2008 STMicroelectronics *END OF FILE**/`