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jeremybenn |
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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* File Name : stm32f10x_rcc.h
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* Author : MCD Application Team
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* Version : V2.0.1
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* Date : 06/13/2008
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* Description : This file contains all the functions prototypes for the
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* RCC firmware library.
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********************************************************************************
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F10x_RCC_H
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#define __STM32F10x_RCC_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_map.h"
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/* Exported types ------------------------------------------------------------*/
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typedef struct
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{
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u32 SYSCLK_Frequency;
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u32 HCLK_Frequency;
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u32 PCLK1_Frequency;
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u32 PCLK2_Frequency;
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u32 ADCCLK_Frequency;
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}RCC_ClocksTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/* HSE configuration */
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#define RCC_HSE_OFF ((u32)0x00000000)
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#define RCC_HSE_ON ((u32)0x00010000)
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#define RCC_HSE_Bypass ((u32)0x00040000)
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#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
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((HSE) == RCC_HSE_Bypass))
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/* PLL entry clock source */
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#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000)
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#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000)
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#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000)
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#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
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((SOURCE) == RCC_PLLSource_HSE_Div1) || \
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((SOURCE) == RCC_PLLSource_HSE_Div2))
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/* PLL multiplication factor */
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#define RCC_PLLMul_2 ((u32)0x00000000)
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#define RCC_PLLMul_3 ((u32)0x00040000)
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#define RCC_PLLMul_4 ((u32)0x00080000)
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#define RCC_PLLMul_5 ((u32)0x000C0000)
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#define RCC_PLLMul_6 ((u32)0x00100000)
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#define RCC_PLLMul_7 ((u32)0x00140000)
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#define RCC_PLLMul_8 ((u32)0x00180000)
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#define RCC_PLLMul_9 ((u32)0x001C0000)
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#define RCC_PLLMul_10 ((u32)0x00200000)
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#define RCC_PLLMul_11 ((u32)0x00240000)
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#define RCC_PLLMul_12 ((u32)0x00280000)
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#define RCC_PLLMul_13 ((u32)0x002C0000)
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#define RCC_PLLMul_14 ((u32)0x00300000)
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#define RCC_PLLMul_15 ((u32)0x00340000)
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#define RCC_PLLMul_16 ((u32)0x00380000)
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#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
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((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
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((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
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((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
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((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
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((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
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((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
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((MUL) == RCC_PLLMul_16))
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/* System clock source */
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#define RCC_SYSCLKSource_HSI ((u32)0x00000000)
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#define RCC_SYSCLKSource_HSE ((u32)0x00000001)
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#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002)
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#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
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((SOURCE) == RCC_SYSCLKSource_HSE) || \
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((SOURCE) == RCC_SYSCLKSource_PLLCLK))
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/* AHB clock source */
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#define RCC_SYSCLK_Div1 ((u32)0x00000000)
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#define RCC_SYSCLK_Div2 ((u32)0x00000080)
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#define RCC_SYSCLK_Div4 ((u32)0x00000090)
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#define RCC_SYSCLK_Div8 ((u32)0x000000A0)
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#define RCC_SYSCLK_Div16 ((u32)0x000000B0)
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#define RCC_SYSCLK_Div64 ((u32)0x000000C0)
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#define RCC_SYSCLK_Div128 ((u32)0x000000D0)
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#define RCC_SYSCLK_Div256 ((u32)0x000000E0)
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#define RCC_SYSCLK_Div512 ((u32)0x000000F0)
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#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
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((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
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((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
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((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
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((HCLK) == RCC_SYSCLK_Div512))
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/* APB1/APB2 clock source */
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#define RCC_HCLK_Div1 ((u32)0x00000000)
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#define RCC_HCLK_Div2 ((u32)0x00000400)
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#define RCC_HCLK_Div4 ((u32)0x00000500)
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#define RCC_HCLK_Div8 ((u32)0x00000600)
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#define RCC_HCLK_Div16 ((u32)0x00000700)
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#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
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((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
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((PCLK) == RCC_HCLK_Div16))
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/* RCC Interrupt source */
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#define RCC_IT_LSIRDY ((u8)0x01)
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#define RCC_IT_LSERDY ((u8)0x02)
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#define RCC_IT_HSIRDY ((u8)0x04)
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#define RCC_IT_HSERDY ((u8)0x08)
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#define RCC_IT_PLLRDY ((u8)0x10)
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#define RCC_IT_CSS ((u8)0x80)
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#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00))
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#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
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((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
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((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
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#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00))
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/* USB clock source */
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#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00)
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#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01)
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#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
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((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
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/* ADC clock source */
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#define RCC_PCLK2_Div2 ((u32)0x00000000)
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#define RCC_PCLK2_Div4 ((u32)0x00004000)
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#define RCC_PCLK2_Div6 ((u32)0x00008000)
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#define RCC_PCLK2_Div8 ((u32)0x0000C000)
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#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
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((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
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/* LSE configuration */
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#define RCC_LSE_OFF ((u8)0x00)
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#define RCC_LSE_ON ((u8)0x01)
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#define RCC_LSE_Bypass ((u8)0x04)
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#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
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((LSE) == RCC_LSE_Bypass))
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/* RTC clock source */
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#define RCC_RTCCLKSource_LSE ((u32)0x00000100)
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#define RCC_RTCCLKSource_LSI ((u32)0x00000200)
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#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300)
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#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
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((SOURCE) == RCC_RTCCLKSource_LSI) || \
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((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
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/* AHB peripheral */
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#define RCC_AHBPeriph_DMA1 ((u32)0x00000001)
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#define RCC_AHBPeriph_DMA2 ((u32)0x00000002)
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#define RCC_AHBPeriph_SRAM ((u32)0x00000004)
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#define RCC_AHBPeriph_FLITF ((u32)0x00000010)
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#define RCC_AHBPeriph_CRC ((u32)0x00000040)
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#define RCC_AHBPeriph_FSMC ((u32)0x00000100)
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#define RCC_AHBPeriph_SDIO ((u32)0x00000400)
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#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
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/* APB2 peripheral */
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#define RCC_APB2Periph_AFIO ((u32)0x00000001)
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#define RCC_APB2Periph_GPIOA ((u32)0x00000004)
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#define RCC_APB2Periph_GPIOB ((u32)0x00000008)
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#define RCC_APB2Periph_GPIOC ((u32)0x00000010)
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#define RCC_APB2Periph_GPIOD ((u32)0x00000020)
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#define RCC_APB2Periph_GPIOE ((u32)0x00000040)
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#define RCC_APB2Periph_GPIOF ((u32)0x00000080)
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#define RCC_APB2Periph_GPIOG ((u32)0x00000100)
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#define RCC_APB2Periph_ADC1 ((u32)0x00000200)
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#define RCC_APB2Periph_ADC2 ((u32)0x00000400)
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#define RCC_APB2Periph_TIM1 ((u32)0x00000800)
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#define RCC_APB2Periph_SPI1 ((u32)0x00001000)
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#define RCC_APB2Periph_TIM8 ((u32)0x00002000)
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#define RCC_APB2Periph_USART1 ((u32)0x00004000)
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#define RCC_APB2Periph_ADC3 ((u32)0x00008000)
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#define RCC_APB2Periph_ALL ((u32)0x0000FFFD)
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#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))
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/* APB1 peripheral */
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#define RCC_APB1Periph_TIM2 ((u32)0x00000001)
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#define RCC_APB1Periph_TIM3 ((u32)0x00000002)
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#define RCC_APB1Periph_TIM4 ((u32)0x00000004)
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#define RCC_APB1Periph_TIM5 ((u32)0x00000008)
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#define RCC_APB1Periph_TIM6 ((u32)0x00000010)
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#define RCC_APB1Periph_TIM7 ((u32)0x00000020)
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#define RCC_APB1Periph_WWDG ((u32)0x00000800)
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#define RCC_APB1Periph_SPI2 ((u32)0x00004000)
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#define RCC_APB1Periph_SPI3 ((u32)0x00008000)
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#define RCC_APB1Periph_USART2 ((u32)0x00020000)
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#define RCC_APB1Periph_USART3 ((u32)0x00040000)
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#define RCC_APB1Periph_UART4 ((u32)0x00080000)
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#define RCC_APB1Periph_UART5 ((u32)0x00100000)
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#define RCC_APB1Periph_I2C1 ((u32)0x00200000)
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#define RCC_APB1Periph_I2C2 ((u32)0x00400000)
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#define RCC_APB1Periph_USB ((u32)0x00800000)
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#define RCC_APB1Periph_CAN ((u32)0x02000000)
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#define RCC_APB1Periph_BKP ((u32)0x08000000)
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#define RCC_APB1Periph_PWR ((u32)0x10000000)
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#define RCC_APB1Periph_DAC ((u32)0x20000000)
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#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F)
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#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))
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/* Clock source to output on MCO pin */
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#define RCC_MCO_NoClock ((u8)0x00)
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#define RCC_MCO_SYSCLK ((u8)0x04)
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#define RCC_MCO_HSI ((u8)0x05)
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#define RCC_MCO_HSE ((u8)0x06)
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#define RCC_MCO_PLLCLK_Div2 ((u8)0x07)
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#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
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((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
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((MCO) == RCC_MCO_PLLCLK_Div2))
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/* RCC Flag */
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#define RCC_FLAG_HSIRDY ((u8)0x20)
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#define RCC_FLAG_HSERDY ((u8)0x31)
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#define RCC_FLAG_PLLRDY ((u8)0x39)
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#define RCC_FLAG_LSERDY ((u8)0x41)
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#define RCC_FLAG_LSIRDY ((u8)0x61)
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#define RCC_FLAG_PINRST ((u8)0x7A)
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#define RCC_FLAG_PORRST ((u8)0x7B)
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#define RCC_FLAG_SFTRST ((u8)0x7C)
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#define RCC_FLAG_IWDGRST ((u8)0x7D)
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#define RCC_FLAG_WWDGRST ((u8)0x7E)
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#define RCC_FLAG_LPWRRST ((u8)0x7F)
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#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
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((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
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((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
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((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
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((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
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((FLAG) == RCC_FLAG_LPWRRST))
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#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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void RCC_DeInit(void);
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void RCC_HSEConfig(u32 RCC_HSE);
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ErrorStatus RCC_WaitForHSEStartUp(void);
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void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue);
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| 257 |
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void RCC_HSICmd(FunctionalState NewState);
|
| 258 |
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void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul);
|
| 259 |
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void RCC_PLLCmd(FunctionalState NewState);
|
| 260 |
|
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void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource);
|
| 261 |
|
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u8 RCC_GetSYSCLKSource(void);
|
| 262 |
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void RCC_HCLKConfig(u32 RCC_SYSCLK);
|
| 263 |
|
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void RCC_PCLK1Config(u32 RCC_HCLK);
|
| 264 |
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void RCC_PCLK2Config(u32 RCC_HCLK);
|
| 265 |
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void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState);
|
| 266 |
|
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void RCC_USBCLKConfig(u32 RCC_USBCLKSource);
|
| 267 |
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void RCC_ADCCLKConfig(u32 RCC_PCLK2);
|
| 268 |
|
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void RCC_LSEConfig(u8 RCC_LSE);
|
| 269 |
|
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void RCC_LSICmd(FunctionalState NewState);
|
| 270 |
|
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void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource);
|
| 271 |
|
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void RCC_RTCCLKCmd(FunctionalState NewState);
|
| 272 |
|
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void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
| 273 |
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void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState);
|
| 274 |
|
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void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState);
|
| 275 |
|
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void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState);
|
| 276 |
|
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void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState);
|
| 277 |
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void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState);
|
| 278 |
|
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void RCC_BackupResetCmd(FunctionalState NewState);
|
| 279 |
|
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void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
| 280 |
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void RCC_MCOConfig(u8 RCC_MCO);
|
| 281 |
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FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG);
|
| 282 |
|
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void RCC_ClearFlag(void);
|
| 283 |
|
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ITStatus RCC_GetITStatus(u8 RCC_IT);
|
| 284 |
|
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void RCC_ClearITPendingBit(u8 RCC_IT);
|
| 285 |
|
|
|
| 286 |
|
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#endif /* __STM32F10x_RCC_H */
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| 287 |
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|
|
| 288 |
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/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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