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/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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* File Name : stm32f10x_sdio.h
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* Author : MCD Application Team
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* Version : V2.0.1
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* Date : 06/13/2008
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* Description : This file contains all the functions prototypes for the
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* SDIO firmware library.
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********************************************************************************
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F10x_SDIO_H
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#define __STM32F10x_SDIO_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_map.h"
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/* Exported types ------------------------------------------------------------*/
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typedef struct
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{
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u8 SDIO_ClockDiv;
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u32 SDIO_ClockEdge;
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u32 SDIO_ClockBypass;
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u32 SDIO_ClockPowerSave;
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u32 SDIO_BusWide;
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u32 SDIO_HardwareFlowControl;
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} SDIO_InitTypeDef;
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typedef struct
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{
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u32 SDIO_Argument;
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u32 SDIO_CmdIndex;
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u32 SDIO_Response;
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u32 SDIO_Wait;
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u32 SDIO_CPSM;
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} SDIO_CmdInitTypeDef;
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typedef struct
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{
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u32 SDIO_DataTimeOut;
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u32 SDIO_DataLength;
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u32 SDIO_DataBlockSize;
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u32 SDIO_TransferDir;
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u32 SDIO_TransferMode;
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u32 SDIO_DPSM;
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} SDIO_DataInitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/* SDIO Clock Edge -----------------------------------------------------------*/
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#define SDIO_ClockEdge_Rising ((u32)0x00000000)
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#define SDIO_ClockEdge_Falling ((u32)0x00002000)
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#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
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((EDGE) == SDIO_ClockEdge_Falling))
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/* SDIO Clock Bypass ----------------------------------------------------------*/
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#define SDIO_ClockBypass_Disable ((u32)0x00000000)
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#define SDIO_ClockBypass_Enable ((u32)0x00000400)
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#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
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((BYPASS) == SDIO_ClockBypass_Enable))
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/* SDIO Clock Power Save ----------------------------------------------------*/
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#define SDIO_ClockPowerSave_Disable ((u32)0x00000000)
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#define SDIO_ClockPowerSave_Enable ((u32)0x00000200)
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#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
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((SAVE) == SDIO_ClockPowerSave_Enable))
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/* SDIO Bus Wide -------------------------------------------------------------*/
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#define SDIO_BusWide_1b ((u32)0x00000000)
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#define SDIO_BusWide_4b ((u32)0x00000800)
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#define SDIO_BusWide_8b ((u32)0x00001000)
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#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
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((WIDE) == SDIO_BusWide_8b))
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/* SDIO Hardware Flow Control -----------------------------------------------*/
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#define SDIO_HardwareFlowControl_Disable ((u32)0x00000000)
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#define SDIO_HardwareFlowControl_Enable ((u32)0x00004000)
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#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
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((CONTROL) == SDIO_HardwareFlowControl_Enable))
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/* SDIO Power State ----------------------------------------------------------*/
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#define SDIO_PowerState_OFF ((u32)0x00000000)
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#define SDIO_PowerState_ON ((u32)0x00000003)
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#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
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/* SDIO Interrupt soucres ----------------------------------------------------*/
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#define SDIO_IT_CCRCFAIL ((u32)0x00000001)
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#define SDIO_IT_DCRCFAIL ((u32)0x00000002)
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#define SDIO_IT_CTIMEOUT ((u32)0x00000004)
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#define SDIO_IT_DTIMEOUT ((u32)0x00000008)
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#define SDIO_IT_TXUNDERR ((u32)0x00000010)
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#define SDIO_IT_RXOVERR ((u32)0x00000020)
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#define SDIO_IT_CMDREND ((u32)0x00000040)
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#define SDIO_IT_CMDSENT ((u32)0x00000080)
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#define SDIO_IT_DATAEND ((u32)0x00000100)
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#define SDIO_IT_STBITERR ((u32)0x00000200)
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#define SDIO_IT_DBCKEND ((u32)0x00000400)
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#define SDIO_IT_CMDACT ((u32)0x00000800)
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#define SDIO_IT_TXACT ((u32)0x00001000)
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#define SDIO_IT_RXACT ((u32)0x00002000)
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#define SDIO_IT_TXFIFOHE ((u32)0x00004000)
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#define SDIO_IT_RXFIFOHF ((u32)0x00008000)
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#define SDIO_IT_TXFIFOF ((u32)0x00010000)
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#define SDIO_IT_RXFIFOF ((u32)0x00020000)
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#define SDIO_IT_TXFIFOE ((u32)0x00040000)
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#define SDIO_IT_RXFIFOE ((u32)0x00080000)
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#define SDIO_IT_TXDAVL ((u32)0x00100000)
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#define SDIO_IT_RXDAVL ((u32)0x00200000)
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#define SDIO_IT_SDIOIT ((u32)0x00400000)
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#define SDIO_IT_CEATAEND ((u32)0x00800000)
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#define IS_SDIO_IT(IT) ((((IT) & (u32)0xFF000000) == 0x00) && ((IT) != (u32)0x00))
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/* SDIO Command Index -------------------------------------------------------*/
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#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
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/* SDIO Response Type --------------------------------------------------------*/
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#define SDIO_Response_No ((u32)0x00000000)
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#define SDIO_Response_Short ((u32)0x00000040)
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#define SDIO_Response_Long ((u32)0x000000C0)
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#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
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((RESPONSE) == SDIO_Response_Short) || \
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((RESPONSE) == SDIO_Response_Long))
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/* SDIO Wait Interrupt State -------------------------------------------------*/
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#define SDIO_Wait_No ((u32)0x00000000) /* SDIO No Wait, TimeOut is enabled */
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#define SDIO_Wait_IT ((u32)0x00000100) /* SDIO Wait Interrupt Request */
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#define SDIO_Wait_Pend ((u32)0x00000200) /* SDIO Wait End of transfer */
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#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
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((WAIT) == SDIO_Wait_Pend))
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/* SDIO CPSM State -----------------------------------------------------------*/
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#define SDIO_CPSM_Disable ((u32)0x00000000)
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#define SDIO_CPSM_Enable ((u32)0x00000400)
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#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
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/* SDIO Response Registers ---------------------------------------------------*/
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#define SDIO_RESP1 ((u32)0x00000000)
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#define SDIO_RESP2 ((u32)0x00000004)
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#define SDIO_RESP3 ((u32)0x00000008)
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#define SDIO_RESP4 ((u32)0x0000000C)
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#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
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((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
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/* SDIO Data Length ----------------------------------------------------------*/
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#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
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/* SDIO Data Block Size ------------------------------------------------------*/
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#define SDIO_DataBlockSize_1b ((u32)0x00000000)
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#define SDIO_DataBlockSize_2b ((u32)0x00000010)
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#define SDIO_DataBlockSize_4b ((u32)0x00000020)
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#define SDIO_DataBlockSize_8b ((u32)0x00000030)
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#define SDIO_DataBlockSize_16b ((u32)0x00000040)
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#define SDIO_DataBlockSize_32b ((u32)0x00000050)
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#define SDIO_DataBlockSize_64b ((u32)0x00000060)
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#define SDIO_DataBlockSize_128b ((u32)0x00000070)
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#define SDIO_DataBlockSize_256b ((u32)0x00000080)
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#define SDIO_DataBlockSize_512b ((u32)0x00000090)
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#define SDIO_DataBlockSize_1024b ((u32)0x000000A0)
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#define SDIO_DataBlockSize_2048b ((u32)0x000000B0)
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#define SDIO_DataBlockSize_4096b ((u32)0x000000C0)
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#define SDIO_DataBlockSize_8192b ((u32)0x000000D0)
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#define SDIO_DataBlockSize_16384b ((u32)0x000000E0)
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#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
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((SIZE) == SDIO_DataBlockSize_2b) || \
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((SIZE) == SDIO_DataBlockSize_4b) || \
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((SIZE) == SDIO_DataBlockSize_8b) || \
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((SIZE) == SDIO_DataBlockSize_16b) || \
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((SIZE) == SDIO_DataBlockSize_32b) || \
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((SIZE) == SDIO_DataBlockSize_64b) || \
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((SIZE) == SDIO_DataBlockSize_128b) || \
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((SIZE) == SDIO_DataBlockSize_256b) || \
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((SIZE) == SDIO_DataBlockSize_512b) || \
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((SIZE) == SDIO_DataBlockSize_1024b) || \
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((SIZE) == SDIO_DataBlockSize_2048b) || \
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((SIZE) == SDIO_DataBlockSize_4096b) || \
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((SIZE) == SDIO_DataBlockSize_8192b) || \
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((SIZE) == SDIO_DataBlockSize_16384b))
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/* SDIO Transfer Direction ---------------------------------------------------*/
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#define SDIO_TransferDir_ToCard ((u32)0x00000000)
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#define SDIO_TransferDir_ToSDIO ((u32)0x00000002)
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#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
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((DIR) == SDIO_TransferDir_ToSDIO))
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/* SDIO Transfer Type --------------------------------------------------------*/
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#define SDIO_TransferMode_Block ((u32)0x00000000)
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#define SDIO_TransferMode_Stream ((u32)0x00000004)
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#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
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((MODE) == SDIO_TransferMode_Block))
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/* SDIO DPSM State -----------------------------------------------------------*/
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#define SDIO_DPSM_Disable ((u32)0x00000000)
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#define SDIO_DPSM_Enable ((u32)0x00000001)
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#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
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/* SDIO Flags ----------------------------------------------------------------*/
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#define SDIO_FLAG_CCRCFAIL ((u32)0x00000001)
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#define SDIO_FLAG_DCRCFAIL ((u32)0x00000002)
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#define SDIO_FLAG_CTIMEOUT ((u32)0x00000004)
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#define SDIO_FLAG_DTIMEOUT ((u32)0x00000008)
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#define SDIO_FLAG_TXUNDERR ((u32)0x00000010)
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#define SDIO_FLAG_RXOVERR ((u32)0x00000020)
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#define SDIO_FLAG_CMDREND ((u32)0x00000040)
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#define SDIO_FLAG_CMDSENT ((u32)0x00000080)
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#define SDIO_FLAG_DATAEND ((u32)0x00000100)
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#define SDIO_FLAG_STBITERR ((u32)0x00000200)
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#define SDIO_FLAG_DBCKEND ((u32)0x00000400)
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#define SDIO_FLAG_CMDACT ((u32)0x00000800)
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#define SDIO_FLAG_TXACT ((u32)0x00001000)
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#define SDIO_FLAG_RXACT ((u32)0x00002000)
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#define SDIO_FLAG_TXFIFOHE ((u32)0x00004000)
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#define SDIO_FLAG_RXFIFOHF ((u32)0x00008000)
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#define SDIO_FLAG_TXFIFOF ((u32)0x00010000)
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#define SDIO_FLAG_RXFIFOF ((u32)0x00020000)
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#define SDIO_FLAG_TXFIFOE ((u32)0x00040000)
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#define SDIO_FLAG_RXFIFOE ((u32)0x00080000)
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#define SDIO_FLAG_TXDAVL ((u32)0x00100000)
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#define SDIO_FLAG_RXDAVL ((u32)0x00200000)
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#define SDIO_FLAG_SDIOIT ((u32)0x00400000)
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#define SDIO_FLAG_CEATAEND ((u32)0x00800000)
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#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
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((FLAG) == SDIO_FLAG_DCRCFAIL) || \
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((FLAG) == SDIO_FLAG_CTIMEOUT) || \
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((FLAG) == SDIO_FLAG_DTIMEOUT) || \
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((FLAG) == SDIO_FLAG_TXUNDERR) || \
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((FLAG) == SDIO_FLAG_RXOVERR) || \
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((FLAG) == SDIO_FLAG_CMDREND) || \
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((FLAG) == SDIO_FLAG_CMDSENT) || \
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((FLAG) == SDIO_FLAG_DATAEND) || \
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((FLAG) == SDIO_FLAG_STBITERR) || \
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((FLAG) == SDIO_FLAG_DBCKEND) || \
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((FLAG) == SDIO_FLAG_CMDACT) || \
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((FLAG) == SDIO_FLAG_TXACT) || \
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((FLAG) == SDIO_FLAG_RXACT) || \
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((FLAG) == SDIO_FLAG_TXFIFOHE) || \
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((FLAG) == SDIO_FLAG_RXFIFOHF) || \
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((FLAG) == SDIO_FLAG_TXFIFOF) || \
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((FLAG) == SDIO_FLAG_RXFIFOF) || \
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((FLAG) == SDIO_FLAG_TXFIFOE) || \
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((FLAG) == SDIO_FLAG_RXFIFOE) || \
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((FLAG) == SDIO_FLAG_TXDAVL) || \
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((FLAG) == SDIO_FLAG_RXDAVL) || \
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((FLAG) == SDIO_FLAG_SDIOIT) || \
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((FLAG) == SDIO_FLAG_CEATAEND))
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#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFF3FF800) == 0x00) && ((FLAG) != (u32)0x00))
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#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
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((IT) == SDIO_IT_DCRCFAIL) || \
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((IT) == SDIO_IT_CTIMEOUT) || \
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((IT) == SDIO_IT_DTIMEOUT) || \
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((IT) == SDIO_IT_TXUNDERR) || \
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((IT) == SDIO_IT_RXOVERR) || \
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((IT) == SDIO_IT_CMDREND) || \
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((IT) == SDIO_IT_CMDSENT) || \
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((IT) == SDIO_IT_DATAEND) || \
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((IT) == SDIO_IT_STBITERR) || \
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((IT) == SDIO_IT_DBCKEND) || \
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((IT) == SDIO_IT_CMDACT) || \
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((IT) == SDIO_IT_TXACT) || \
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((IT) == SDIO_IT_RXACT) || \
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((IT) == SDIO_IT_TXFIFOHE) || \
|
283 |
|
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((IT) == SDIO_IT_RXFIFOHF) || \
|
284 |
|
|
((IT) == SDIO_IT_TXFIFOF) || \
|
285 |
|
|
((IT) == SDIO_IT_RXFIFOF) || \
|
286 |
|
|
((IT) == SDIO_IT_TXFIFOE) || \
|
287 |
|
|
((IT) == SDIO_IT_RXFIFOE) || \
|
288 |
|
|
((IT) == SDIO_IT_TXDAVL) || \
|
289 |
|
|
((IT) == SDIO_IT_RXDAVL) || \
|
290 |
|
|
((IT) == SDIO_IT_SDIOIT) || \
|
291 |
|
|
((IT) == SDIO_IT_CEATAEND))
|
292 |
|
|
|
293 |
|
|
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (u32)0xFF3FF800) == 0x00) && ((IT) != (u32)0x00))
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294 |
|
|
|
295 |
|
|
/* SDIO Read Wait Mode -------------------------------------------------------*/
|
296 |
|
|
#define SDIO_ReadWaitMode_CLK ((u32)0x00000000)
|
297 |
|
|
#define SDIO_ReadWaitMode_DATA2 ((u32)0x00000001)
|
298 |
|
|
|
299 |
|
|
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
|
300 |
|
|
((MODE) == SDIO_ReadWaitMode_DATA2))
|
301 |
|
|
|
302 |
|
|
/* Exported macro ------------------------------------------------------------*/
|
303 |
|
|
/* Exported functions ------------------------------------------------------- */
|
304 |
|
|
void SDIO_DeInit(void);
|
305 |
|
|
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
306 |
|
|
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
307 |
|
|
void SDIO_ClockCmd(FunctionalState NewState);
|
308 |
|
|
void SDIO_SetPowerState(u32 SDIO_PowerState);
|
309 |
|
|
u32 SDIO_GetPowerState(void);
|
310 |
|
|
void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState);
|
311 |
|
|
void SDIO_DMACmd(FunctionalState NewState);
|
312 |
|
|
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
|
313 |
|
|
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
|
314 |
|
|
u8 SDIO_GetCommandResponse(void);
|
315 |
|
|
u32 SDIO_GetResponse(u32 SDIO_RESP);
|
316 |
|
|
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
317 |
|
|
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
318 |
|
|
u32 SDIO_GetDataCounter(void);
|
319 |
|
|
u32 SDIO_ReadData(void);
|
320 |
|
|
void SDIO_WriteData(u32 Data);
|
321 |
|
|
u32 SDIO_GetFIFOCount(void);
|
322 |
|
|
void SDIO_StartSDIOReadWait(FunctionalState NewState);
|
323 |
|
|
void SDIO_StopSDIOReadWait(FunctionalState NewState);
|
324 |
|
|
void SDIO_SetSDIOReadWaitMode(u32 SDIO_ReadWaitMode);
|
325 |
|
|
void SDIO_SetSDIOOperation(FunctionalState NewState);
|
326 |
|
|
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
|
327 |
|
|
void SDIO_CommandCompletionCmd(FunctionalState NewState);
|
328 |
|
|
void SDIO_CEATAITCmd(FunctionalState NewState);
|
329 |
|
|
void SDIO_SendCEATACmd(FunctionalState NewState);
|
330 |
|
|
FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
|
331 |
|
|
void SDIO_ClearFlag(u32 SDIO_FLAG);
|
332 |
|
|
ITStatus SDIO_GetITStatus(u32 SDIO_IT);
|
333 |
|
|
void SDIO_ClearITPendingBit(u32 SDIO_IT);
|
334 |
|
|
|
335 |
|
|
#endif /* __STM32F10x_SDIO_H */
|
336 |
|
|
|
337 |
|
|
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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