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jeremybenn |
/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
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* File Name : stm32f10x_dma.c
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* Author : MCD Application Team
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* Date First Issued : 09/29/2006
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* Description : This file provides all the DMA firmware functions.
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********************************************************************************
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* History:
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* 04/02/2007: V0.2
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* 02/05/2007: V0.1
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* 09/29/2006: V0.01
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_dma.h"
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#include "stm32f10x_rcc.h"
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* DMA ENABLE mask */
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#define CCR_ENABLE_Set ((u32)0x00000001)
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#define CCR_ENABLE_Reset ((u32)0xFFFFFFFE)
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/* DMA Channelx interrupt pending bit masks */
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#define DMA_Channel1_IT_Mask ((u32)0x0000000F)
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#define DMA_Channel2_IT_Mask ((u32)0x000000F0)
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#define DMA_Channel3_IT_Mask ((u32)0x00000F00)
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#define DMA_Channel4_IT_Mask ((u32)0x0000F000)
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#define DMA_Channel5_IT_Mask ((u32)0x000F0000)
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#define DMA_Channel6_IT_Mask ((u32)0x00F00000)
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#define DMA_Channel7_IT_Mask ((u32)0x0F000000)
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/* DMA registers Masks */
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#define CCR_CLEAR_Mask ((u32)0xFFFF800F)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/*******************************************************************************
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* Function Name : DMA_DeInit
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* Description : Deinitializes the DMA Channelx registers to their default reset
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* values.
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* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
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* Channel.
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* Output : None
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* Return : None
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*******************************************************************************/
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void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
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{
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/* DMA Channelx disable */
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DMA_Cmd(DMA_Channelx, DISABLE);
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/* Reset Channelx control register */
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DMA_Channelx->CCR = 0;
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/* Reset Channelx remaining bytes register */
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DMA_Channelx->CNDTR = 0;
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/* Reset Channelx peripheral address register */
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DMA_Channelx->CPAR = 0;
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/* Reset Channelx memory address register */
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DMA_Channelx->CMAR = 0;
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switch (*(u32*)&DMA_Channelx)
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{
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case DMA_Channel1_BASE:
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/* Reset interrupt pending bits for Channel1 */
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DMA->IFCR |= DMA_Channel1_IT_Mask;
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break;
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case DMA_Channel2_BASE:
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/* Reset interrupt pending bits for Channel2 */
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DMA->IFCR |= DMA_Channel2_IT_Mask;
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break;
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case DMA_Channel3_BASE:
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/* Reset interrupt pending bits for Channel3 */
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DMA->IFCR |= DMA_Channel3_IT_Mask;
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break;
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case DMA_Channel4_BASE:
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/* Reset interrupt pending bits for Channel4 */
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DMA->IFCR |= DMA_Channel4_IT_Mask;
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break;
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case DMA_Channel5_BASE:
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/* Reset interrupt pending bits for Channel5 */
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DMA->IFCR |= DMA_Channel5_IT_Mask;
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break;
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case DMA_Channel6_BASE:
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/* Reset interrupt pending bits for Channel6 */
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DMA->IFCR |= DMA_Channel6_IT_Mask;
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break;
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case DMA_Channel7_BASE:
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/* Reset interrupt pending bits for Channel7 */
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DMA->IFCR |= DMA_Channel7_IT_Mask;
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break;
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default:
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break;
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}
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}
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/*******************************************************************************
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* Function Name : DMA_Init
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* Description : Initializes the DMA Channelx according to the specified
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* parameters in the DMA_InitStruct.
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* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
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* Channel.
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* - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
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* contains the configuration information for the specified
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* DMA Channel.
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* Output : None
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* Return : None
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******************************************************************************/
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void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct)
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{
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u32 tmpreg = 0;
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/* Check the parameters */
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assert(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
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assert(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
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assert(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
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assert(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
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assert(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
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assert(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
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assert(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
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assert(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
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assert(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
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/*--------------------------- DMA Channelx CCR Configuration -----------------*/
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/* Get the DMA_Channelx CCR value */
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tmpreg = DMA_Channelx->CCR;
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/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRCULAR and DIR bits */
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tmpreg &= CCR_CLEAR_Mask;
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/* Configure DMA Channelx: data transfer, data size, priority level and mode */
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/* Set DIR bit according to DMA_DIR value */
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/* Set CIRCULAR bit according to DMA_Mode value */
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/* Set PINC bit according to DMA_PeripheralInc value */
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/* Set MINC bit according to DMA_MemoryInc value */
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/* Set PSIZE bits according to DMA_PeripheralDataSize value */
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/* Set MSIZE bits according to DMA_MemoryDataSize value */
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/* Set PL bits according to DMA_Priority value */
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/* Set the MEM2MEM bit according to DMA_M2M value */
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tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
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DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
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DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
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DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
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/* Write to DMA Channelx CCR */
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DMA_Channelx->CCR = tmpreg;
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/*--------------------------- DMA Channelx CNBTR Configuration ---------------*/
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/* Write to DMA Channelx CNBTR */
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DMA_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
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/*--------------------------- DMA Channelx CPAR Configuration ----------------*/
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/* Write to DMA Channelx CPAR */
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DMA_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
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/*--------------------------- DMA Channelx CMAR Configuration ----------------*/
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/* Write to DMA Channelx CMAR */
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DMA_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
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}
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/*******************************************************************************
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* Function Name : DMA_StructInit
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* Description : Fills each DMA_InitStruct member with its default value.
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* Input : - DMA_InitStruct : pointer to a DMA_InitTypeDef structure
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* which will be initialized.
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* Output : None
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* Return : None
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*******************************************************************************/
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void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
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{
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/*-------------- Reset DMA init structure parameters values ------------------*/
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/* Initialize the DMA_PeripheralBaseAddr member */
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DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
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/* Initialize the DMA_MemoryBaseAddr member */
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DMA_InitStruct->DMA_MemoryBaseAddr = 0;
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/* Initialize the DMA_DIR member */
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DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
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/* Initialize the DMA_BufferSize member */
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DMA_InitStruct->DMA_BufferSize = 0;
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/* Initialize the DMA_PeripheralInc member */
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DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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/* Initialize the DMA_MemoryInc member */
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DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
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/* Initialize the DMA_PeripheralDataSize member */
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DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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/* Initialize the DMA_MemoryDataSize member */
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DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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/* Initialize the DMA_Mode member */
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DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
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/* Initialize the DMA_Priority member */
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DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
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/* Initialize the DMA_M2M member */
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DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
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}
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/*******************************************************************************
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* Function Name : DMA_Cmd
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* Description : Enables or disables the specified DMA Channel.
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* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
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* Channel.
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* - NewState: new state of the DMAx Channel.
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* This parameter can be: ENABLE or DISABLE.
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* Output : None
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* Return : None
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*******************************************************************************/
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void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState)
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{
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/* Check the parameters */
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assert(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the selected DMA Channelx */
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DMA_Channelx->CCR |= CCR_ENABLE_Set;
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}
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else
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{
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/* Disable the selected DMA Channelx */
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DMA_Channelx->CCR &= CCR_ENABLE_Reset;
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}
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}
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/*******************************************************************************
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* Function Name : DMA_ITConfig
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* Description : Enables or disables the specified DMA interrupts.
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* Input : - DMA_IT: specifies the DMA interrupts sources to be enabled
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* or disabled.
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* This parameter can be any combination of the following values:
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* - DMA_IT_TC: Transfer complete interrupt mask
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* - DMA_IT_HT: Half transfer interrupt mask
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* - DMA_IT_TE: Transfer error interrupt mask
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* - NewState: new state of the specified DMA interrupts.
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* This parameter can be: ENABLE or DISABLE.
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* Output : None
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* Return : None
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*******************************************************************************/
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void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, u32 DMA_IT, FunctionalState NewState)
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{
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/* Check the parameters */
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assert(IS_DMA_CONFIG_IT(DMA_IT));
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assert(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the selected DMA interrupts */
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DMA_Channelx->CCR |= DMA_IT;
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}
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else
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{
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/* Disable the selected DMA interrupts */
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DMA_Channelx->CCR &= ~DMA_IT;
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}
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}
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/*******************************************************************************
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* Function Name : DMA_GetCurrDataCounter
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* Description : Returns the number of remaining data units in the current
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* DMA Channel transfer.
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* Input : - DMA_Channelx: where x can be 1, 2 to 7 to select the DMA
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* Channel.
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* Output : None
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* Return : The number of remaining data units in the current DMA Channel
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* transfer..
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*******************************************************************************/
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u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx)
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{
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| 292 |
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/* Return the current memory address value for Channelx */
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return ((u16)(DMA_Channelx->CNDTR));
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}
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| 296 |
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/*******************************************************************************
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| 297 |
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* Function Name : DMA_GetFlagStatus
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| 298 |
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* Description : Checks whether the specified DMA flag is set or not.
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* Input : - DMA_FLAG: specifies the flag to check.
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* This parameter can be one of the following values:
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* - DMA_FLAG_GL1: Channel1 global flag.
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* - DMA_FLAG_TC1: Channel1 transfer complete flag.
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* - DMA_FLAG_HT1: Channel1 half transfer flag.
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* - DMA_FLAG_TE1: Channel1 transfer error flag.
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* - DMA_FLAG_GL2: Channel2 global flag.
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* - DMA_FLAG_TC2: Channel2 transfer complete flag.
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* - DMA_FLAG_HT2: Channel2 half transfer flag.
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* - DMA_FLAG_TE2: Channel2 transfer error flag.
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* - DMA_FLAG_GL3: Channel3 global flag.
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* - DMA_FLAG_TC3: Channel3 transfer complete flag.
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* - DMA_FLAG_HT3: Channel3 half transfer flag.
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* - DMA_FLAG_TE3: Channel3 transfer error flag.
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* - DMA_FLAG_GL4: Channel4 global flag.
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* - DMA_FLAG_TC4: Channel4 transfer complete flag.
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* - DMA_FLAG_HT4: Channel4 half transfer flag.
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* - DMA_FLAG_TE4: Channel4 transfer error flag.
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* - DMA_FLAG_GL5: Channel5 global flag.
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* - DMA_FLAG_TC5: Channel5 transfer complete flag.
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* - DMA_FLAG_HT5: Channel5 half transfer flag.
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* - DMA_FLAG_TE5: Channel5 transfer error flag.
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* - DMA_FLAG_GL6: Channel6 global flag.
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* - DMA_FLAG_TC6: Channel6 transfer complete flag.
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* - DMA_FLAG_HT6: Channel6 half transfer flag.
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* - DMA_FLAG_TE6: Channel6 transfer error flag.
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* - DMA_FLAG_GL7: Channel7 global flag.
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* - DMA_FLAG_TC7: Channel7 transfer complete flag.
|
| 327 |
|
|
* - DMA_FLAG_HT7: Channel7 half transfer flag.
|
| 328 |
|
|
* - DMA_FLAG_TE7: Channel7 transfer error flag.
|
| 329 |
|
|
* Output : None
|
| 330 |
|
|
* Return : The new state of DMA_FLAG (SET or RESET).
|
| 331 |
|
|
*******************************************************************************/
|
| 332 |
|
|
FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG)
|
| 333 |
|
|
{
|
| 334 |
|
|
FlagStatus bitstatus = RESET;
|
| 335 |
|
|
|
| 336 |
|
|
/* Check the parameters */
|
| 337 |
|
|
assert(IS_DMA_GET_FLAG(DMA_FLAG));
|
| 338 |
|
|
|
| 339 |
|
|
/* Check the status of the specified DMA flag */
|
| 340 |
|
|
if ((DMA->ISR & DMA_FLAG) != (u32)RESET)
|
| 341 |
|
|
{
|
| 342 |
|
|
/* DMA_FLAG is set */
|
| 343 |
|
|
bitstatus = SET;
|
| 344 |
|
|
}
|
| 345 |
|
|
else
|
| 346 |
|
|
{
|
| 347 |
|
|
/* DMA_FLAG is reset */
|
| 348 |
|
|
bitstatus = RESET;
|
| 349 |
|
|
}
|
| 350 |
|
|
/* Return the DMA_FLAG status */
|
| 351 |
|
|
return bitstatus;
|
| 352 |
|
|
}
|
| 353 |
|
|
|
| 354 |
|
|
/*******************************************************************************
|
| 355 |
|
|
* Function Name : DMA_ClearFlag
|
| 356 |
|
|
* Description : Clears the DMA's pending flags.
|
| 357 |
|
|
* Input : - DMA_FLAG: specifies the flag to clear.
|
| 358 |
|
|
* This parameter can be any combination of the following values:
|
| 359 |
|
|
* - DMA_FLAG_GL1: Channel1 global flag.
|
| 360 |
|
|
* - DMA_FLAG_TC1: Channel1 transfer complete flag.
|
| 361 |
|
|
* - DMA_FLAG_HT1: Channel1 half transfer flag.
|
| 362 |
|
|
* - DMA_FLAG_TE1: Channel1 transfer error flag.
|
| 363 |
|
|
* - DMA_FLAG_GL2: Channel2 global flag.
|
| 364 |
|
|
* - DMA_FLAG_TC2: Channel2 transfer complete flag.
|
| 365 |
|
|
* - DMA_FLAG_HT2: Channel2 half transfer flag.
|
| 366 |
|
|
* - DMA_FLAG_TE2: Channel2 transfer error flag.
|
| 367 |
|
|
* - DMA_FLAG_GL3: Channel3 global flag.
|
| 368 |
|
|
* - DMA_FLAG_TC3: Channel3 transfer complete flag.
|
| 369 |
|
|
* - DMA_FLAG_HT3: Channel3 half transfer flag.
|
| 370 |
|
|
* - DMA_FLAG_TE3: Channel3 transfer error flag.
|
| 371 |
|
|
* - DMA_FLAG_GL4: Channel4 global flag.
|
| 372 |
|
|
* - DMA_FLAG_TC4: Channel4 transfer complete flag.
|
| 373 |
|
|
* - DMA_FLAG_HT4: Channel4 half transfer flag.
|
| 374 |
|
|
* - DMA_FLAG_TE4: Channel4 transfer error flag.
|
| 375 |
|
|
* - DMA_FLAG_GL5: Channel5 global flag.
|
| 376 |
|
|
* - DMA_FLAG_TC5: Channel5 transfer complete flag.
|
| 377 |
|
|
* - DMA_FLAG_HT5: Channel5 half transfer flag.
|
| 378 |
|
|
* - DMA_FLAG_TE5: Channel5 transfer error flag.
|
| 379 |
|
|
* - DMA_FLAG_GL6: Channel6 global flag.
|
| 380 |
|
|
* - DMA_FLAG_TC6: Channel6 transfer complete flag.
|
| 381 |
|
|
* - DMA_FLAG_HT6: Channel6 half transfer flag.
|
| 382 |
|
|
* - DMA_FLAG_TE6: Channel6 transfer error flag.
|
| 383 |
|
|
* - DMA_FLAG_GL7: Channel7 global flag.
|
| 384 |
|
|
* - DMA_FLAG_TC7: Channel7 transfer complete flag.
|
| 385 |
|
|
* - DMA_FLAG_HT7: Channel7 half transfer flag.
|
| 386 |
|
|
* - DMA_FLAG_TE7: Channel7 transfer error flag.
|
| 387 |
|
|
* Output : None
|
| 388 |
|
|
* Return : None
|
| 389 |
|
|
*******************************************************************************/
|
| 390 |
|
|
void DMA_ClearFlag(u32 DMA_FLAG)
|
| 391 |
|
|
{
|
| 392 |
|
|
/* Check the parameters */
|
| 393 |
|
|
assert(IS_DMA_CLEAR_FLAG(DMA_FLAG));
|
| 394 |
|
|
|
| 395 |
|
|
/* Clear the selected DMA flags */
|
| 396 |
|
|
DMA->IFCR = DMA_FLAG;
|
| 397 |
|
|
}
|
| 398 |
|
|
|
| 399 |
|
|
/*******************************************************************************
|
| 400 |
|
|
* Function Name : DMA_GetITStatus
|
| 401 |
|
|
* Description : Checks whether the specified DMA interrupt has occurred or not.
|
| 402 |
|
|
* Input : - DMA_IT: specifies the DMA interrupt source to check.
|
| 403 |
|
|
* This parameter can be one of the following values:
|
| 404 |
|
|
* - DMA_IT_GL1: Channel1 global interrupt.
|
| 405 |
|
|
* - DMA_IT_TC1: Channel1 transfer complete interrupt.
|
| 406 |
|
|
* - DMA_IT_HT1: Channel1 half transfer interrupt.
|
| 407 |
|
|
* - DMA_IT_TE1: Channel1 transfer error interrupt.
|
| 408 |
|
|
* - DMA_IT_GL2: Channel2 global interrupt.
|
| 409 |
|
|
* - DMA_IT_TC2: Channel2 transfer complete interrupt.
|
| 410 |
|
|
* - DMA_IT_HT2: Channel2 half transfer interrupt.
|
| 411 |
|
|
* - DMA_IT_TE2: Channel2 transfer error interrupt.
|
| 412 |
|
|
* - DMA_IT_GL3: Channel3 global interrupt.
|
| 413 |
|
|
* - DMA_IT_TC3: Channel3 transfer complete interrupt.
|
| 414 |
|
|
* - DMA_IT_HT3: Channel3 half transfer interrupt.
|
| 415 |
|
|
* - DMA_IT_TE3: Channel3 transfer error interrupt.
|
| 416 |
|
|
* - DMA_IT_GL4: Channel4 global interrupt.
|
| 417 |
|
|
* - DMA_IT_TC4: Channel4 transfer complete interrupt.
|
| 418 |
|
|
* - DMA_IT_HT4: Channel4 half transfer interrupt.
|
| 419 |
|
|
* - DMA_IT_TE4: Channel4 transfer error interrupt.
|
| 420 |
|
|
* - DMA_IT_GL5: Channel5 global interrupt.
|
| 421 |
|
|
* - DMA_IT_TC5: Channel5 transfer complete interrupt.
|
| 422 |
|
|
* - DMA_IT_HT5: Channel5 half transfer interrupt.
|
| 423 |
|
|
* - DMA_IT_TE5: Channel5 transfer error interrupt.
|
| 424 |
|
|
* - DMA_IT_GL6: Channel6 global interrupt.
|
| 425 |
|
|
* - DMA_IT_TC6: Channel6 transfer complete interrupt.
|
| 426 |
|
|
* - DMA_IT_HT6: Channel6 half transfer interrupt.
|
| 427 |
|
|
* - DMA_IT_TE6: Channel6 transfer error interrupt.
|
| 428 |
|
|
* - DMA_IT_GL7: Channel7 global interrupt.
|
| 429 |
|
|
* - DMA_IT_TC7: Channel7 transfer complete interrupt.
|
| 430 |
|
|
* - DMA_IT_HT7: Channel7 half transfer interrupt.
|
| 431 |
|
|
* - DMA_IT_TE7: Channel7 transfer error interrupt.
|
| 432 |
|
|
* Output : None
|
| 433 |
|
|
* Return : The new state of DMA_IT (SET or RESET).
|
| 434 |
|
|
*******************************************************************************/
|
| 435 |
|
|
ITStatus DMA_GetITStatus(u32 DMA_IT)
|
| 436 |
|
|
{
|
| 437 |
|
|
ITStatus bitstatus = RESET;
|
| 438 |
|
|
|
| 439 |
|
|
/* Check the parameters */
|
| 440 |
|
|
assert(IS_DMA_GET_IT(DMA_IT));
|
| 441 |
|
|
|
| 442 |
|
|
/* Check the status of the specified DMA interrupt */
|
| 443 |
|
|
if ((DMA->ISR & DMA_IT) != (u32)RESET)
|
| 444 |
|
|
{
|
| 445 |
|
|
/* DMA_IT is set */
|
| 446 |
|
|
bitstatus = SET;
|
| 447 |
|
|
}
|
| 448 |
|
|
else
|
| 449 |
|
|
{
|
| 450 |
|
|
/* DMA_IT is reset */
|
| 451 |
|
|
bitstatus = RESET;
|
| 452 |
|
|
}
|
| 453 |
|
|
/* Return the DMA_IT status */
|
| 454 |
|
|
return bitstatus;
|
| 455 |
|
|
}
|
| 456 |
|
|
|
| 457 |
|
|
/*******************************************************************************
|
| 458 |
|
|
* Function Name : DMA_ClearITPendingBit
|
| 459 |
|
|
* Description : Clears the DMA’s interrupt pending bits.
|
| 460 |
|
|
* Input : - DMA_IT: specifies the DMA interrupt pending bit to clear.
|
| 461 |
|
|
* This parameter can be any combination of the following values:
|
| 462 |
|
|
* - DMA_IT_GL1: Channel1 global interrupt.
|
| 463 |
|
|
* - DMA_IT_TC1: Channel1 transfer complete interrupt.
|
| 464 |
|
|
* - DMA_IT_HT1: Channel1 half transfer interrupt.
|
| 465 |
|
|
* - DMA_IT_TE1: Channel1 transfer error interrupt.
|
| 466 |
|
|
* - DMA_IT_GL2: Channel2 global interrupt.
|
| 467 |
|
|
* - DMA_IT_TC2: Channel2 transfer complete interrupt.
|
| 468 |
|
|
* - DMA_IT_HT2: Channel2 half transfer interrupt.
|
| 469 |
|
|
* - DMA_IT_TE2: Channel2 transfer error interrupt.
|
| 470 |
|
|
* - DMA_IT_GL3: Channel3 global interrupt.
|
| 471 |
|
|
* - DMA_IT_TC3: Channel3 transfer complete interrupt.
|
| 472 |
|
|
* - DMA_IT_HT3: Channel3 half transfer interrupt.
|
| 473 |
|
|
* - DMA_IT_TE3: Channel3 transfer error interrupt.
|
| 474 |
|
|
* - DMA_IT_GL4: Channel4 global interrupt.
|
| 475 |
|
|
* - DMA_IT_TC4: Channel4 transfer complete interrupt.
|
| 476 |
|
|
* - DMA_IT_HT4: Channel4 half transfer interrupt.
|
| 477 |
|
|
* - DMA_IT_TE4: Channel4 transfer error interrupt.
|
| 478 |
|
|
* - DMA_IT_GL5: Channel5 global interrupt.
|
| 479 |
|
|
* - DMA_IT_TC5: Channel5 transfer complete interrupt.
|
| 480 |
|
|
* - DMA_IT_HT5: Channel5 half transfer interrupt.
|
| 481 |
|
|
* - DMA_IT_TE5: Channel5 transfer error interrupt.
|
| 482 |
|
|
* - DMA_IT_GL6: Channel6 global interrupt.
|
| 483 |
|
|
* - DMA_IT_TC6: Channel6 transfer complete interrupt.
|
| 484 |
|
|
* - DMA_IT_HT6: Channel6 half transfer interrupt.
|
| 485 |
|
|
* - DMA_IT_TE6: Channel6 transfer error interrupt.
|
| 486 |
|
|
* - DMA_IT_GL7: Channel7 global interrupt.
|
| 487 |
|
|
* - DMA_IT_TC7: Channel7 transfer complete interrupt.
|
| 488 |
|
|
* - DMA_IT_HT7: Channel7 half transfer interrupt.
|
| 489 |
|
|
* - DMA_IT_TE7: Channel7 transfer error interrupt.
|
| 490 |
|
|
* Output : None
|
| 491 |
|
|
* Return : None
|
| 492 |
|
|
*******************************************************************************/
|
| 493 |
|
|
void DMA_ClearITPendingBit(u32 DMA_IT)
|
| 494 |
|
|
{
|
| 495 |
|
|
/* Check the parameters */
|
| 496 |
|
|
assert(IS_DMA_CLEAR_IT(DMA_IT));
|
| 497 |
|
|
|
| 498 |
|
|
/* Clear the selected DMA interrupt pending bits */
|
| 499 |
|
|
DMA->IFCR = DMA_IT;
|
| 500 |
|
|
}
|
| 501 |
|
|
|
| 502 |
|
|
/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/
|
| 503 |
|
|
|
