OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_STM32F107_GCC_Rowley/] [STM32F10x_Startup.s] - Blame information for rev 615

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 582 jeremybenn
/*****************************************************************************
2
 * Copyright (c) 2007 Rowley Associates Limited.                             *
3
 *                                                                           *
4
 * This file may be distributed under the terms of the License Agreement     *
5
 * provided with this software.                                              *
6
 *                                                                           *
7
 * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE   *
8
 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
9
 *****************************************************************************/
10
 
11
/*****************************************************************************
12
 *                           Preprocessor Definitions
13
 *                           ------------------------
14
 *
15
 * STARTUP_FROM_RESET
16
 *
17
 *   If defined, the program will startup from power-on/reset. If not defined
18
 *   the program will just loop endlessly from power-on/reset.
19
 *
20
 *   This definition is not defined by default on this target because the
21
 *   debugger is unable to reset this target and maintain control of it over the
22
 *   JTAG interface. The advantage of doing this is that it allows the debugger
23
 *   to reset the CPU and run programs from a known reset CPU state on each run.
24
 *   It also acts as a safety net if you accidently download a program in FLASH
25
 *   that crashes and prevents the debugger from taking control over JTAG
26
 *   rendering the target unusable over JTAG. The obvious disadvantage of doing
27
 *   this is that your application will not startup without the debugger.
28
 *
29
 *   We advise that on this target you keep STARTUP_FROM_RESET undefined whilst
30
 *   you are developing and only define STARTUP_FROM_RESET when development is
31
 *   complete.
32
 *
33
 *****************************************************************************/
34
 
35
  .global reset_handler
36
 
37
  .section .vectors, "ax"
38
  .code 16
39
  .align 0
40
  .global _vectors
41
 
42
.macro DEFAULT_ISR_HANDLER name=
43
  .thumb_func
44
  .weak \name
45
\name:
46
1: b 1b /* endless loop */
47
.endm
48
 
49
.extern xPortPendSVHandler
50
.extern xPortSysTickHandler
51
.extern vPortSVCHandler
52
.extern vMAC_ISR;
53
 
54
_vectors:
55
  .word __stack_end__
56
#ifdef STARTUP_FROM_RESET
57
  .word reset_handler
58
#else
59
  .word reset_wait
60
#endif /* STARTUP_FROM_RESET */
61
  .word NMIException
62
  .word HardFaultException
63
  .word MemManageException
64
  .word BusFaultException
65
  .word UsageFaultException
66
  .word 0 // Reserved
67
  .word 0 // Reserved
68
  .word 0 // Reserved
69
  .word 0 // Reserved
70
  .word vPortSVCHandler
71
  .word DebugMonitor
72
  .word 0 // Reserved
73
  .word xPortPendSVHandler
74
  .word xPortSysTickHandler
75
  .word WWDG_IRQHandler
76
  .word PVD_IRQHandler
77
  .word TAMPER_IRQHandler
78
  .word RTC_IRQHandler
79
  .word FLASH_IRQHandler
80
  .word RCC_IRQHandler
81
  .word EXTI0_IRQHandler
82
  .word EXTI1_IRQHandler
83
  .word EXTI2_IRQHandler
84
  .word EXTI3_IRQHandler
85
  .word EXTI4_IRQHandler
86
  .word DMAChannel1_IRQHandler
87
  .word DMAChannel2_IRQHandler
88
  .word DMAChannel3_IRQHandler
89
  .word DMAChannel4_IRQHandler
90
  .word DMAChannel5_IRQHandler
91
  .word DMAChannel6_IRQHandler
92
  .word DMAChannel7_IRQHandler
93
  .word ADC_IRQHandler
94
  .word USB_HP_CAN_TX_IRQHandler
95
  .word USB_LP_CAN_RX0_IRQHandler
96
  .word CAN_RX1_IRQHandler
97
  .word CAN_SCE_IRQHandler
98
  .word EXTI9_5_IRQHandler
99
  .word TIM1_BRK_IRQHandler
100
  .word TIM1_UP_IRQHandler
101
  .word TIM1_TRG_COM_IRQHandler
102
  .word TIM1_CC_IRQHandler
103
  .word TIM2_IRQHandler
104
  .word TIM3_IRQHandler
105
  .word TIM4_IRQHandler
106
  .word I2C1_EV_IRQHandler
107
  .word I2C1_ER_IRQHandler
108
  .word I2C2_EV_IRQHandler
109
  .word I2C2_ER_IRQHandler
110
  .word SPI1_IRQHandler
111
  .word SPI2_IRQHandler
112
  .word USART1_IRQHandler
113
  .word USART2_IRQHandler
114
  .word USART3_IRQHandler
115
  .word EXTI15_10_IRQHandler
116
  .word RTCAlarm_IRQHandler
117
  .word USBWakeUp_IRQHandler
118
  .word TIM8_BRK_IRQHandler
119
  .word TIM8_UP_IRQHandler
120
  .word TIM8_TRG_COM_IRQHandler
121
  .word TIM8_CC_IRQHandler
122
  .word ADC3_IRQHandler
123
  .word FSMC_IRQHandler
124
  .word SDIO_IRQHandler
125
  .word TIM5_IRQHandler
126
  .word SPI3_IRQHandler
127
  .word UART4_IRQHandler
128
  .word UART5_IRQHandler
129
  .word TIM6_IRQHandler
130
  .word TIM7_IRQHandler
131
  .word DMA2_Channel1_IRQHandler
132
  .word DMA2_Channel2_IRQHandler
133
  .word DMA2_Channel3_IRQHandler
134
  .word DMA2_Channel4_5_IRQHandler
135
  .word vMAC_ISR
136
  .word vMAC_ISR
137
 
138
  .section .init, "ax"
139
  .thumb_func
140
 
141
  reset_handler:
142
#ifndef __FLASH_BUILD
143
  /* If this is a RAM build, configure vector table offset register to point
144
     to the RAM vector table. */
145
  ldr r0, =0xE000ED08
146
  ldr r1, =_vectors
147
  str r1, [r0]
148
#endif
149
  b _start
150
 
151
DEFAULT_ISR_HANDLER HardFaultException
152
DEFAULT_ISR_HANDLER NMIException
153
DEFAULT_ISR_HANDLER MemManageException
154
DEFAULT_ISR_HANDLER BusFaultException
155
DEFAULT_ISR_HANDLER UsageFaultException
156
DEFAULT_ISR_HANDLER SVCHandler
157
DEFAULT_ISR_HANDLER DebugMonitor
158
DEFAULT_ISR_HANDLER PendSV
159
DEFAULT_ISR_HANDLER SysTickHandler
160
DEFAULT_ISR_HANDLER WWDG_IRQHandler
161
DEFAULT_ISR_HANDLER PVD_IRQHandler
162
DEFAULT_ISR_HANDLER TAMPER_IRQHandler
163
DEFAULT_ISR_HANDLER RTC_IRQHandler
164
DEFAULT_ISR_HANDLER FLASH_IRQHandler
165
DEFAULT_ISR_HANDLER RCC_IRQHandler
166
DEFAULT_ISR_HANDLER EXTI0_IRQHandler
167
DEFAULT_ISR_HANDLER EXTI1_IRQHandler
168
DEFAULT_ISR_HANDLER EXTI2_IRQHandler
169
DEFAULT_ISR_HANDLER EXTI3_IRQHandler
170
DEFAULT_ISR_HANDLER EXTI4_IRQHandler
171
DEFAULT_ISR_HANDLER DMAChannel1_IRQHandler
172
DEFAULT_ISR_HANDLER DMAChannel2_IRQHandler
173
DEFAULT_ISR_HANDLER DMAChannel3_IRQHandler
174
DEFAULT_ISR_HANDLER DMAChannel4_IRQHandler
175
DEFAULT_ISR_HANDLER DMAChannel5_IRQHandler
176
DEFAULT_ISR_HANDLER DMAChannel6_IRQHandler
177
DEFAULT_ISR_HANDLER DMAChannel7_IRQHandler
178
DEFAULT_ISR_HANDLER ADC_IRQHandler
179
DEFAULT_ISR_HANDLER USB_HP_CAN_TX_IRQHandler
180
DEFAULT_ISR_HANDLER USB_LP_CAN_RX0_IRQHandler
181
DEFAULT_ISR_HANDLER CAN_RX1_IRQHandler
182
DEFAULT_ISR_HANDLER CAN_SCE_IRQHandler
183
DEFAULT_ISR_HANDLER EXTI9_5_IRQHandler
184
DEFAULT_ISR_HANDLER TIM1_BRK_IRQHandler
185
DEFAULT_ISR_HANDLER TIM1_UP_IRQHandler
186
DEFAULT_ISR_HANDLER TIM1_TRG_COM_IRQHandler
187
DEFAULT_ISR_HANDLER TIM1_CC_IRQHandler
188
DEFAULT_ISR_HANDLER TIM2_IRQHandler
189
DEFAULT_ISR_HANDLER TIM3_IRQHandler
190
DEFAULT_ISR_HANDLER TIM4_IRQHandler
191
DEFAULT_ISR_HANDLER I2C1_EV_IRQHandler
192
DEFAULT_ISR_HANDLER I2C1_ER_IRQHandler
193
DEFAULT_ISR_HANDLER I2C2_EV_IRQHandler
194
DEFAULT_ISR_HANDLER I2C2_ER_IRQHandler
195
DEFAULT_ISR_HANDLER SPI1_IRQHandler
196
DEFAULT_ISR_HANDLER SPI2_IRQHandler
197
DEFAULT_ISR_HANDLER USART1_IRQHandler
198
DEFAULT_ISR_HANDLER USART2_IRQHandler
199
DEFAULT_ISR_HANDLER USART3_IRQHandler
200
DEFAULT_ISR_HANDLER EXTI15_10_IRQHandler
201
DEFAULT_ISR_HANDLER RTCAlarm_IRQHandler
202
DEFAULT_ISR_HANDLER USBWakeUp_IRQHandler
203
DEFAULT_ISR_HANDLER TIM8_BRK_IRQHandler
204
DEFAULT_ISR_HANDLER TIM8_UP_IRQHandler
205
DEFAULT_ISR_HANDLER TIM8_TRG_COM_IRQHandler
206
DEFAULT_ISR_HANDLER TIM8_CC_IRQHandler
207
DEFAULT_ISR_HANDLER ADC3_IRQHandler
208
DEFAULT_ISR_HANDLER FSMC_IRQHandler
209
DEFAULT_ISR_HANDLER SDIO_IRQHandler
210
DEFAULT_ISR_HANDLER TIM5_IRQHandler
211
DEFAULT_ISR_HANDLER SPI3_IRQHandler
212
DEFAULT_ISR_HANDLER UART4_IRQHandler
213
DEFAULT_ISR_HANDLER UART5_IRQHandler
214
DEFAULT_ISR_HANDLER TIM6_IRQHandler
215
DEFAULT_ISR_HANDLER TIM7_IRQHandler
216
DEFAULT_ISR_HANDLER DMA2_Channel1_IRQHandler
217
DEFAULT_ISR_HANDLER DMA2_Channel2_IRQHandler
218
DEFAULT_ISR_HANDLER DMA2_Channel3_IRQHandler
219
DEFAULT_ISR_HANDLER DMA2_Channel4_5_IRQHandler
220
 
221
#ifndef STARTUP_FROM_RESET
222
DEFAULT_ISR_HANDLER reset_wait
223
#endif /* STARTUP_FROM_RESET */
224
 
225
  // STM32 library requires these
226
  .global __WFI
227
  .global __WFE
228
  .global __SEV
229
  .global __ISB
230
  .global __DSB
231
  .global __DMB
232
  .global __SVC
233
  .global __MRS_CONTROL
234
  .global __MSR_CONTROL
235
  .global __MRS_PSP
236
  .global __MSR_PSP
237
  .global __MRS_MSP
238
  .global __MSR_MSP
239
  .global __SETPRIMASK
240
  .global __RESETPRIMASK
241
  .global __SETFAULTMASK
242
  .global __RESETFAULTMASK
243
  .global __BASEPRICONFIG
244
  .global __GetBASEPRI
245
  .global __REV_HalfWord
246
  .global __REV_Word
247
 
248
.thumb_func
249
__WFI:
250
  wfi
251
  bx r14
252
.thumb_func
253
__WFE:
254
  wfe
255
  bx r14
256
.thumb_func
257
__SEV:
258
  sev
259
  bx r14
260
.thumb_func
261
__ISB:
262
  isb
263
  bx r14
264
.thumb_func
265
__DSB:
266
  dsb
267
  bx r14
268
.thumb_func
269
__DMB:
270
  dmb
271
  bx r14
272
.thumb_func
273
__SVC:
274
  svc 0x01
275
  bx r14
276
.thumb_func
277
__MRS_CONTROL:
278
  mrs r0, control
279
  bx r14
280
.thumb_func
281
__MSR_CONTROL:
282
  msr control, r0
283
  isb
284
  bx r14
285
.thumb_func
286
__MRS_PSP:
287
  mrs r0, psp
288
  bx r14
289
.thumb_func
290
__MSR_PSP:
291
  msr psp, r0
292
  bx r14
293
.thumb_func
294
__MRS_MSP:
295
  mrs r0, msp
296
  bx r14
297
.thumb_func
298
__MSR_MSP:
299
  msr msp, r0
300
  bx r14
301
.thumb_func
302
__SETPRIMASK:
303
  cpsid i
304
  bx r14
305
.thumb_func
306
__RESETPRIMASK:
307
  cpsie i
308
  bx r14
309
.thumb_func
310
__SETFAULTMASK:
311
  cpsid f
312
  bx r14
313
.thumb_func
314
__RESETFAULTMASK:
315
  cpsie f
316
  bx r14
317
.thumb_func
318
__BASEPRICONFIG:
319
  msr basepri, r0
320
  bx r14
321
.thumb_func
322
__GetBASEPRI:
323
  mrs r0, basepri_max
324
  bx r14
325
.thumb_func
326
__REV_HalfWord:
327
  rev16 r0, r0
328
  bx r14
329
.thumb_func
330
__REV_Word:
331
  rev r0, r0
332
  bx r14
333
 
334
 
335
 
336
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.