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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_STM32F107_GCC_Rowley/] [scsc.tmp] - Blame information for rev 592

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1 582 jeremybenn
/*
2
        FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.
3
 
4
        This file is part of the FreeRTOS distribution.
5
 
6
        FreeRTOS is free software; you can redistribute it and/or modify it     under
7
        the terms of the GNU General Public License (version 2) as published by the
8
        Free Software Foundation and modified by the FreeRTOS exception.
9
        **NOTE** The exception to the GPL is included to allow you to distribute a
10
        combined work that includes FreeRTOS without being obliged to provide the
11
        source code for proprietary components outside of the FreeRTOS kernel.
12
        Alternative commercial license and support terms are also available upon
13
        request.  See the licensing section of http://www.FreeRTOS.org for full
14
        license details.
15
 
16
        FreeRTOS is distributed in the hope that it will be useful,     but WITHOUT
17
        ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
        FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
        more details.
20
 
21
        You should have received a copy of the GNU General Public License along
22
        with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
23
        Temple Place, Suite 330, Boston, MA  02111-1307  USA.
24
 
25
 
26
        ***************************************************************************
27
        *                                                                         *
28
        * Looking for a quick start?  Then check out the FreeRTOS eBook!          *
29
        * See http://www.FreeRTOS.org/Documentation for details                   *
30
        *                                                                         *
31
        ***************************************************************************
32
 
33
        1 tab == 4 spaces!
34
 
35
        Please ensure to read the configuration and relevant port sections of the
36
        online documentation.
37
 
38
        http://www.FreeRTOS.org - Documentation, latest information, license and
39
        contact details.
40
 
41
        http://www.SafeRTOS.com - A version that is certified for use in safety
42
        critical systems.
43
 
44
        http://www.OpenRTOS.com - Commercial support, development, porting,
45
        licensing and training services.
46
*/
47
 
48
/* FreeRTOS includes. */
49
#include "FreeRTOS.h"
50
#include "semphr.h"
51
#include "task.h"
52
#include "emac.h"
53
 
54
/* Library includes. */
55
#include "stm32fxxx_eth.h"
56
#include "stm32f10x_gpio.h"
57
#include "stm32f10x_rcc.h"
58
#include "stm32f10x_nvic.h"
59
 
60
/*-----------------------------------------------------------*/
61
 
62
/* Hardware specifics. */
63
#define uipRCC_MAC_CLOCK                        ( 1UL << 14UL )
64
#define uipRCC_MAC_TX_CLOCK                     ( 1UL << 15UL )
65
#define uipRCC_MAC_RX_CLOCK                     ( 1UL << 16UL )
66
#define uipPHY_ADDRESS                          ( 1 )
67
#define uipENET_IRQ_NUM                         ( 61 )
68
#define uipMODE_MII                                     ( 1UL << 23UL )
69
#define uipREMAP_MAC_IO                         ( 1UL << 21UL )
70
 
71
/* The number of descriptors to chain together for use by the Rx DMA. */
72
#define uipNUM_RX_DESCRIPTORS           4
73
 
74
/* The total number of buffers to be available.  At most (?) there should be
75
one available for each Rx descriptor, one for current use, and one that is
76
in the process of being transmitted. */
77
#define uipNUM_BUFFERS                          ( uipNUM_RX_DESCRIPTORS + 2 )
78
 
79
/* Each buffer is sized to fit an entire Ethernet packet.  This is for
80
simplicity and speed, but could waste RAM. */
81
#define uipMAX_PACKET_SIZE                      1520
82
 
83
/* The field in the descriptor that is unused by this configuration is used to
84
hold the send count.  This is just #defined to a meaningful name. */
85
#define SendCount Buffer2NextDescAddr
86
 
87
/* If no buffers are available, then wait this long before looking again.... */
88
#define uipBUFFER_WAIT_DELAY    ( 3 / portTICK_RATE_MS )
89
 
90
/* ...and don't look more than this many times. */
91
#define uipBUFFER_WAIT_ATTEMPTS ( 30 )
92
 
93
/* Let the DMA know that a new descriptor has been made available to it. */
94
#define prvRxDescriptorAvailable()              ETH_DMA->DMARPDR = 0
95
 
96
/*-----------------------------------------------------------*/
97
 
98
/*
99
 * Configure the IO for Ethernet use.
100
 */
101
static void prvSetupEthGPIO( void );
102
 
103
/*
104
 * Return a pointer to an unused buffer, marking the returned buffer as now
105
 * in use.
106
 */
107
static unsigned char *prvGetNextBuffer( void );
108
 
109
/*-----------------------------------------------------------*/
110
 
111
/* Allocate the Rx descriptors used by the DMA. */
112
static ETH_DMADESCTypeDef  xRxDescriptors[ uipNUM_RX_DESCRIPTORS ] __attribute__((aligned(4)));
113
 
114
/* Allocate the descriptor used for transmitting.  It might be that better
115
performance could be achieved by having more than one Tx descriptor, but
116
in this simple case only one is used. */
117
static volatile ETH_DMADESCTypeDef  xTxDescriptor __attribute__((aligned(4)));
118
 
119
/* Buffers used for receiving and transmitting data. */
120
static unsigned char ucMACBuffers[ uipNUM_BUFFERS ][ uipMAX_PACKET_SIZE ] __attribute__((aligned(4)));
121
 
122
/* Each ucBufferInUse index corresponds to a position in the same index in the
123
ucMACBuffers array.  If the index contains a 1 then the buffer within
124
ucMACBuffers is in use, if it contains a 0 then the buffer is free. */
125
static unsigned char ucBufferInUse[ uipNUM_BUFFERS ] = { 0 };
126
 
127
/* Index to the Rx descriptor to inspect next when looking for a received
128
packet. */
129
static unsigned long ulNextDescriptor;
130
 
131
/* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
132
allocated within this file. */
133
extern unsigned char * uip_buf;
134
 
135
/*-----------------------------------------------------------*/
136
 
137
portBASE_TYPE xEthInitialise( void )
138
{
139
static ETH_InitTypeDef xEthInit; /* Static so as not to take up too much stack space. */
140
NVIC_InitTypeDef xNVICInit;
141
const unsigned char ucMACAddress[] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 };
142
portBASE_TYPE xReturn;
143
unsigned long ul;
144
 
145
        /* Start with things in a safe known state. */
146
        ETH_DeInit();
147
        for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )
148
        {
149
                ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), DISABLE );
150
        }
151
 
152
        /* Route clock to the peripheral. */
153
    RCC->AHBENR |= ( uipRCC_MAC_CLOCK | uipRCC_MAC_TX_CLOCK | uipRCC_MAC_RX_CLOCK );
154
 
155
        /* Set the MAC address. */
156
        ETH_MACAddressConfig( ETH_MAC_Address0, ( unsigned char * ) ucMACAddress );
157
 
158
        /* Use MII mode. */
159
    AFIO->MAPR &= ~( uipMODE_MII );
160
 
161
        /* Configure all the GPIO as required for MAC/PHY interfacing. */
162
        prvSetupEthGPIO();
163
 
164
        /* Reset the peripheral. */
165
        ETH_SoftwareReset();
166
        while( ETH_GetSoftwareResetStatus() == SET );
167
 
168
        /* Initialise using the whopping big structure.  Code space could be saved
169
        by making this a const struct, however that would mean changes to the
170
        structure within the library header files could break the code, so for now
171
        just set everything manually at run time. */
172
        xEthInit.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
173
        xEthInit.ETH_Watchdog = ETH_Watchdog_Disable;
174
        xEthInit.ETH_Jabber = ETH_Jabber_Disable;
175
        xEthInit.ETH_JumboFrame = ETH_JumboFrame_Disable;
176
        xEthInit.ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
177
        xEthInit.ETH_CarrierSense = ETH_CarrierSense_Enable;
178
        xEthInit.ETH_Speed = ETH_Speed_10M;
179
        xEthInit.ETH_ReceiveOwn = ETH_ReceiveOwn_Disable;
180
        xEthInit.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
181
        xEthInit.ETH_Mode = ETH_Mode_HalfDuplex;
182
        xEthInit.ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
183
        xEthInit.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
184
        xEthInit.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
185
        xEthInit.ETH_BackOffLimit = ETH_BackOffLimit_10;
186
        xEthInit.ETH_DeferralCheck = ETH_DeferralCheck_Disable;
187
        xEthInit.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
188
        xEthInit.ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
189
        xEthInit.ETH_PassControlFrames = ETH_PassControlFrames_ForwardPassedAddrFilter;
190
        xEthInit.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
191
        xEthInit.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
192
        xEthInit.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
193
        xEthInit.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
194
        xEthInit.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
195
        xEthInit.ETH_HashTableHigh = 0x0;
196
        xEthInit.ETH_HashTableLow = 0x0;
197
        xEthInit.ETH_PauseTime = 0x0;
198
        xEthInit.ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
199
        xEthInit.ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
200
        xEthInit.ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
201
        xEthInit.ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
202
        xEthInit.ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
203
        xEthInit.ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
204
        xEthInit.ETH_VLANTagIdentifier = 0x0;
205
        xEthInit.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
206
        xEthInit.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
207
        xEthInit.ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
208
        xEthInit.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
209
        xEthInit.ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
210
        xEthInit.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
211
        xEthInit.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
212
        xEthInit.ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
213
        xEthInit.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
214
        xEthInit.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
215
        xEthInit.ETH_FixedBurst = ETH_FixedBurst_Disable;
216
        xEthInit.ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
217
        xEthInit.ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
218
        xEthInit.ETH_DescriptorSkipLength = 0x0;
219
        xEthInit.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
220
 
221
        xReturn = ETH_Init( &xEthInit, uipPHY_ADDRESS );
222
 
223
        /* Check a link was established. */
224
        if( xReturn != pdFAIL )
225
        {
226
                /* Rx and Tx interrupts are used. */
227
                ETH_DMAITConfig( ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE );
228
 
229
                /* Only a single Tx descriptor is used.  For now it is set to use an Rx
230
                buffer, but will get updated to point to where ever uip_buf is
231
                pointing prior to its use. */
232
                ETH_DMATxDescChainInit( ( void * ) &xTxDescriptor, ( void * ) ucMACBuffers, 1 );
233
                ETH_DMARxDescChainInit( xRxDescriptors, ( void * ) ucMACBuffers, uipNUM_RX_DESCRIPTORS );
234
                for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )
235
                {
236
                        /* Ensure received data generates an interrupt. */
237
                        ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), ENABLE );
238
 
239
                        /* Fix up the addresses used by the descriptors.
240
                        The way ETH_DMARxDescChainInit() is not compatible with the buffer
241
                        declarations in this file. */
242
                        xRxDescriptors[ ul ].Buffer1Addr = ( unsigned long ) &( ucMACBuffers[ ul ][ 0 ] );
243
 
244
                        /* Mark the buffer used by this descriptor as in use. */
245
            ucBufferInUse[ ul ] = pdTRUE;
246
                }
247
 
248
                /* When receiving data, start at the first descriptor. */
249
                ulNextDescriptor = 0;
250
 
251
                /* Initialise uip_buf to ensure it points somewhere valid. */
252
                uip_buf = prvGetNextBuffer();
253
 
254
                /* SendCount must be initialised to 2 to ensure the Tx descriptor looks
255
                as if its available (as if it has already been sent twice. */
256
        xTxDescriptor.SendCount = 2;
257
 
258
                /* Switch on the interrupts in the NVIC. */
259
                xNVICInit.NVIC_IRQChannel = uipENET_IRQ_NUM;
260
                xNVICInit.NVIC_IRQChannelPreemptionPriority = configLIBRARY_KERNEL_INTERRUPT_PRIORITY;
261
                xNVICInit.NVIC_IRQChannelSubPriority = 0;
262
                xNVICInit.NVIC_IRQChannelCmd = ENABLE;
263
                NVIC_Init( &xNVICInit );
264
 
265
                /* Buffers and descriptors are all set up, now enable the MAC. */
266
                ETH_Start();
267
 
268
                /* Let the DMA know there are Rx descriptors available. */
269
                prvRxDescriptorAvailable();
270
        }
271
 
272
        return xReturn;
273
}
274
/*-----------------------------------------------------------*/
275
 
276
static unsigned char *prvGetNextBuffer( void )
277
{
278
portBASE_TYPE x;
279
unsigned char *ucReturn = NULL;
280
unsigned long ulAttempts = 0;
281
 
282
        while( ucReturn == NULL )
283
        {
284
                /* Look through the buffers to find one that is not in use by
285
                anything else. */
286
                for( x = 0; x < uipNUM_BUFFERS; x++ )
287
                {
288
                        if( ucBufferInUse[ x ] == pdFALSE )
289
                        {
290
                                ucBufferInUse[ x ] = pdTRUE;
291
                                ucReturn = &( ucMACBuffers[ x ][ 0 ] );
292
                                break;
293
                        }
294
                }
295
 
296
                /* Was a buffer found? */
297
                if( ucReturn == NULL )
298
                {
299
                        ulAttempts++;
300
 
301
                        if( ulAttempts >= uipBUFFER_WAIT_ATTEMPTS )
302
                        {
303
                                break;
304
                        }
305
 
306
                        /* Wait then look again. */
307
                        vTaskDelay( uipBUFFER_WAIT_DELAY );
308
                }
309
        }
310
 
311
        return ucReturn;
312
}
313
/*-----------------------------------------------------------*/
314
 
315
unsigned short usGetMACRxData( void )
316
{
317
unsigned short usReturn;
318
 
319
        if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_ES ) != 0 )
320
        {
321
                /* Error in Rx.  Discard the frame and give it back to the DMA. */
322
                xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;
323
                prvRxDescriptorAvailable();
324
 
325
                /* No data to return. */
326
                usReturn = 0UL;
327
 
328
                /* Start from the next descriptor the next time this function is called. */
329
                ulNextDescriptor++;
330
                if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )
331
                {
332
                        ulNextDescriptor = 0UL;
333
                }
334
        }
335
        else if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_OWN ) == 0 )
336
        {
337
                /* Mark the current buffer as free as uip_buf is going to be set to
338
                the buffer that contains the received data. */
339
                vReturnBuffer( uip_buf );
340
 
341
                /* Get the received data length from the top 2 bytes of the Status
342
                word and the data itself. */
343
                usReturn = ( unsigned short ) ( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_FL ) >> 16UL );
344
                uip_buf = ( unsigned char * ) ( xRxDescriptors[ ulNextDescriptor ].Buffer1Addr );
345
 
346
                /* Allocate a new buffer to the descriptor. */
347
                xRxDescriptors[ ulNextDescriptor ].Buffer1Addr = ( unsigned long ) prvGetNextBuffer();
348
 
349
                /* Give the descriptor back to the DMA. */
350
                xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;
351
                prvRxDescriptorAvailable();
352
 
353
                /* Start from the next descriptor the next time this function is called. */
354
                ulNextDescriptor++;
355
                if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )
356
                {
357
                        ulNextDescriptor = 0UL;
358
                }
359
        }
360
        else
361
        {
362
                /* No received data at all. */
363
                usReturn = 0UL;
364
        }
365
 
366
        return usReturn;
367
}
368
/*-----------------------------------------------------------*/
369
 
370
void vSendMACData( unsigned short usDataLen )
371
{
372
unsigned long ulAttempts = 0UL;
373
 
374
        /* Check to see if the Tx descriptor is free.  The check against <2 is to
375
        ensure the buffer has been sent twice and in so doing preventing a race
376
        condition with the DMA on the ETH_DMATxDesc_OWN bit. */
377
        while( ( xTxDescriptor.SendCount < 2 ) && ( xTxDescriptor.Status & ETH_DMATxDesc_OWN ) == ETH_DMATxDesc_OWN )
378
        {
379
                /* Wait for the Tx descriptor to become available. */
380
                vTaskDelay( uipBUFFER_WAIT_DELAY );
381
 
382
                ulAttempts++;
383
                if( ulAttempts > uipBUFFER_WAIT_ATTEMPTS )
384
                {
385
                        /* Something has gone wrong as the Tx descriptor is still in use.
386
                        Clear it down manually, the data it was sending will probably be
387
                        lost. */
388
                        xTxDescriptor.Status &= ~ETH_DMATxDesc_OWN;
389
                        vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );
390
                        break;
391
                }
392
        }
393
 
394
        /* Setup the Tx descriptor for transmission. */
395
        xTxDescriptor.SendCount = 0;
396
        xTxDescriptor.Buffer1Addr = ( unsigned long ) uip_buf;
397
        xTxDescriptor.ControlBufferSize = ( unsigned long ) usDataLen;
398
        xTxDescriptor.Status = ETH_DMATxDesc_OWN | ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_TER | ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC;
399
        ETH_DMA->DMASR = ETH_DMASR_TBUS;
400
        ETH_DMA->DMATPDR = 0;
401
 
402
        /* uip_buf is being sent by the Tx descriptor.  Allocate a new buffer. */
403
        uip_buf = prvGetNextBuffer();
404
}
405
/*-----------------------------------------------------------*/
406
 
407
static void prvSetupEthGPIO( void )
408
{
409
GPIO_InitTypeDef xEthInit;
410
 
411
        /* Remap MAC IO. */
412
        AFIO->MAPR |=  ( uipREMAP_MAC_IO );
413
 
414
        /* Set PA2, PA8, PB5, PB8, PB11, PB12, PB13, PC1 and PC2 for Ethernet
415
        interfacing. */
416
        xEthInit.GPIO_Pin = GPIO_Pin_2;/* | GPIO_Pin_8; This should be set when the 25MHz is generated by MCO. */
417
        xEthInit.GPIO_Speed = GPIO_Speed_50MHz;
418
        xEthInit.GPIO_Mode = GPIO_Mode_AF_PP;
419
        GPIO_Init( GPIOA, &xEthInit );
420
 
421
        xEthInit.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; /*5*/
422
        GPIO_Init( GPIOB, &xEthInit );
423
 
424
        xEthInit.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
425
        GPIO_Init( GPIOC, &xEthInit );
426
 
427
 
428
        /* Configure PA0, PA1, PA3, PB10, PC3, PD8, PD9, PD10, PD11 and PD12 as
429
        inputs. */
430
        xEthInit.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
431
        xEthInit.GPIO_Mode = GPIO_Mode_IN_FLOATING;
432
        GPIO_Init( GPIOA, &xEthInit );
433
 
434
        xEthInit.GPIO_Pin = GPIO_Pin_10;
435
        GPIO_Init( GPIOB, &xEthInit );
436
 
437
        xEthInit.GPIO_Pin = GPIO_Pin_3;
438
        GPIO_Init( GPIOC, &xEthInit );
439
 
440
        xEthInit.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
441
        GPIO_Init( GPIOD, &xEthInit );
442
}
443
/*-----------------------------------------------------------*/
444
 
445
void vReturnBuffer( unsigned char *pucBuffer )
446
{
447
unsigned long ul;
448
 
449
        /* Mark a buffer as free for use. */
450
        for( ul = 0; ul < uipNUM_BUFFERS; ul++ )
451
        {
452
                if( ucMACBuffers[ ul ] == pucBuffer )
453
                {
454
                        ucBufferInUse[ ul ] = pdFALSE;
455
                        break;
456
                }
457
        }
458
}
459
/*-----------------------------------------------------------*/
460
 
461
void vMAC_ISR( void )
462
{
463
unsigned long ulStatus;
464
extern xSemaphoreHandle xEMACSemaphore;
465
long xHigherPriorityTaskWoken = pdFALSE;
466
 
467
        /* What caused the interrupt? */
468
        ulStatus = ETH_DMA->DMASR;
469
 
470
        /* Clear everything before leaving. */
471
    ETH_DMA->DMASR = ulStatus;
472
 
473
        if( ulStatus & ETH_DMA_IT_R )
474
        {
475
                /* Data was received.  Ensure the uIP task is not blocked as data has
476
                arrived. */
477
                xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
478
        }
479
 
480
        if( ulStatus & ETH_DMA_IT_T )
481
        {
482
                /* Data was transmitted. */
483
                if( xTxDescriptor.SendCount == 0 )
484
                {
485
                        /* Send again! */
486
                        ( xTxDescriptor.SendCount )++;
487
 
488
                        xTxDescriptor.Status = ETH_DMATxDesc_OWN | ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_TER | ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC;
489
                        ETH_DMA->DMASR = ETH_DMASR_TBUS;
490
                        ETH_DMA->DMATPDR = 0;
491
                }
492
                else
493
                {
494
                        /* The Tx buffer is no longer required. */
495
                        vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );
496
                }
497
        }
498
 
499
        /* If xSemaphoreGiveFromISR() unblocked a task, and the unblocked task has
500
        a higher priority than the currently executing task, then
501
        xHigherPriorityTaskWoken will have been set to pdTRUE and this ISR should
502
        return directly to the higher priority unblocked task. */
503
        portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
504
}
505
 

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