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582 |
jeremybenn |
/**
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******************************************************************************
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* @file stm32f10x.h
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32F10x Connectivity line, High
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* density, Medium density and Low density devices.
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* @author STMicroelectronics - MCD Application Team
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* @version V3.1.0RC1
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* @date 05/07/2009
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******************************************************************************
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f10x
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* @{
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*/
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#ifndef __STM32F10x_H
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#define __STM32F10x_H
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/* Uncomment the line below according to the target STM32 device used in your
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application
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*/
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#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL)
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/* #define STM32F10X_LD */ /*!< STM32 Low density devices */
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/* #define STM32F10X_MD */ /*!< STM32 Medium density devices */
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/* #define STM32F10X_HD */ /*!< STM32 High density devices */
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#define STM32F10X_CL /*!< STM32 Connectivity line devices */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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- Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
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where the Flash memory density ranges between 16 and 32 Kbytes.
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- Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
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where the Flash memory density ranges between 64 and 128 Kbytes.
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- High density devices are STM32F101xx and STM32F103xx microcontrollers where
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the Flash memory density ranges between 256 and 512 Kbytes.
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- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
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*/
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#if !defined USE_STDPERIPH_DRIVER
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_STDPERIPH_DRIVER*/
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#endif
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/**
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* @brief In the following line adjust the value of External High Speed oscillator (HSE)
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used in your application
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*/
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#ifdef STM32F10X_CL
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#define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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#else
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#define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
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#endif /* STM32F10X_CL */
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/**
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
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Timeout value
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*/
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#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */
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#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
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/*!< [31:16] STM32F10x Standard Peripheral Library main version */
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#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03)
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/*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01)
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/*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00)
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/*!< STM32F10x Standard Peripheral Library version number */
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#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
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| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
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| __STM32F10X_STDPERIPH_VERSION_SUB2)
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/**
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* @}
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*/
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/** @addtogroup Configuration_section_for_CMSIS
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* @{
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*/
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/**
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* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
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*/
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#define __MPU_PRESENT 0 /*!< STM32 does not provide a MPU present or not */
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#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/*!< Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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/****** STM32 specific Interrupt Numbers *********************************************************/
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WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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TAMPER_IRQn = 2, /*!< Tamper Interrupt */
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RTC_IRQn = 3, /*!< RTC global Interrupt */
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FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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RCC_IRQn = 5, /*!< RCC global Interrupt */
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EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
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DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
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DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
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DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
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DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
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DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
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DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
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ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
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#ifdef STM32F10X_LD
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USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
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USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
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TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
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TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
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TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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USART1_IRQn = 37, /*!< USART1 global Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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#endif /* STM32F10X_LD */
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#ifdef STM32F10X_MD
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USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
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USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
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TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
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TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
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TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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USART1_IRQn = 37, /*!< USART1 global Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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USART3_IRQn = 39, /*!< USART3 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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#endif /* STM32F10X_MD */
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#ifdef STM32F10X_HD
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USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
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USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
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TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
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TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
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TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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USART1_IRQn = 37, /*!< USART1 global Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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USART3_IRQn = 39, /*!< USART3 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
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TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
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TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
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TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
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ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
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FSMC_IRQn = 48, /*!< FSMC global Interrupt */
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SDIO_IRQn = 49, /*!< SDIO global Interrupt */
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TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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UART4_IRQn = 52, /*!< UART4 global Interrupt */
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UART5_IRQn = 53, /*!< UART5 global Interrupt */
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TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
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TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
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DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
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DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
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DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
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DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
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#endif /* STM32F10X_HD */
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#ifdef STM32F10X_CL
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CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
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CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
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TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
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TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
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TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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USART1_IRQn = 37, /*!< USART1 global Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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USART3_IRQn = 39, /*!< USART3 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
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TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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| 268 |
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SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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UART4_IRQn = 52, /*!< UART4 global Interrupt */
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UART5_IRQn = 53, /*!< UART5 global Interrupt */
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TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
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TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
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| 273 |
|
|
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
|
| 274 |
|
|
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
|
| 275 |
|
|
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
|
| 276 |
|
|
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
|
| 277 |
|
|
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
|
| 278 |
|
|
ETH_IRQn = 61, /*!< Ethernet global Interrupt */
|
| 279 |
|
|
ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
|
| 280 |
|
|
CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
|
| 281 |
|
|
CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
|
| 282 |
|
|
CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
|
| 283 |
|
|
CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
|
| 284 |
|
|
OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
|
| 285 |
|
|
#endif /* STM32F10X_CL */
|
| 286 |
|
|
} IRQn_Type;
|
| 287 |
|
|
|
| 288 |
|
|
/**
|
| 289 |
|
|
* @}
|
| 290 |
|
|
*/
|
| 291 |
|
|
|
| 292 |
|
|
#include "core_cm3.h"
|
| 293 |
|
|
#include "system_stm32f10x.h"
|
| 294 |
|
|
#include <stdint.h>
|
| 295 |
|
|
|
| 296 |
|
|
/** @addtogroup Exported_types
|
| 297 |
|
|
* @{
|
| 298 |
|
|
*/
|
| 299 |
|
|
|
| 300 |
|
|
/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy prupose) */
|
| 301 |
|
|
typedef int32_t s32;
|
| 302 |
|
|
typedef int16_t s16;
|
| 303 |
|
|
typedef int8_t s8;
|
| 304 |
|
|
|
| 305 |
|
|
typedef const int32_t sc32; /*!< Read Only */
|
| 306 |
|
|
typedef const int16_t sc16; /*!< Read Only */
|
| 307 |
|
|
typedef const int8_t sc8; /*!< Read Only */
|
| 308 |
|
|
|
| 309 |
|
|
typedef __IO int32_t vs32;
|
| 310 |
|
|
typedef __IO int16_t vs16;
|
| 311 |
|
|
typedef __IO int8_t vs8;
|
| 312 |
|
|
|
| 313 |
|
|
typedef __I int32_t vsc32; /*!< Read Only */
|
| 314 |
|
|
typedef __I int16_t vsc16; /*!< Read Only */
|
| 315 |
|
|
typedef __I int8_t vsc8; /*!< Read Only */
|
| 316 |
|
|
|
| 317 |
|
|
typedef uint32_t u32;
|
| 318 |
|
|
typedef uint16_t u16;
|
| 319 |
|
|
typedef uint8_t u8;
|
| 320 |
|
|
|
| 321 |
|
|
typedef const uint32_t uc32; /*!< Read Only */
|
| 322 |
|
|
typedef const uint16_t uc16; /*!< Read Only */
|
| 323 |
|
|
typedef const uint8_t uc8; /*!< Read Only */
|
| 324 |
|
|
|
| 325 |
|
|
typedef __IO uint32_t vu32;
|
| 326 |
|
|
typedef __IO uint16_t vu16;
|
| 327 |
|
|
typedef __IO uint8_t vu8;
|
| 328 |
|
|
|
| 329 |
|
|
typedef __I uint32_t vuc32; /*!< Read Only */
|
| 330 |
|
|
typedef __I uint16_t vuc16; /*!< Read Only */
|
| 331 |
|
|
typedef __I uint8_t vuc8; /*!< Read Only */
|
| 332 |
|
|
|
| 333 |
|
|
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
|
| 334 |
|
|
|
| 335 |
|
|
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
| 336 |
|
|
|
| 337 |
|
|
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
| 338 |
|
|
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
| 339 |
|
|
|
| 340 |
|
|
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
|
| 341 |
|
|
|
| 342 |
|
|
/**
|
| 343 |
|
|
* @}
|
| 344 |
|
|
*/
|
| 345 |
|
|
|
| 346 |
|
|
/** @addtogroup Peripheral_registers_structures
|
| 347 |
|
|
* @{
|
| 348 |
|
|
*/
|
| 349 |
|
|
|
| 350 |
|
|
/**
|
| 351 |
|
|
* @brief Analog to Digital Converter
|
| 352 |
|
|
*/
|
| 353 |
|
|
|
| 354 |
|
|
typedef struct
|
| 355 |
|
|
{
|
| 356 |
|
|
__IO uint32_t SR;
|
| 357 |
|
|
__IO uint32_t CR1;
|
| 358 |
|
|
__IO uint32_t CR2;
|
| 359 |
|
|
__IO uint32_t SMPR1;
|
| 360 |
|
|
__IO uint32_t SMPR2;
|
| 361 |
|
|
__IO uint32_t JOFR1;
|
| 362 |
|
|
__IO uint32_t JOFR2;
|
| 363 |
|
|
__IO uint32_t JOFR3;
|
| 364 |
|
|
__IO uint32_t JOFR4;
|
| 365 |
|
|
__IO uint32_t HTR;
|
| 366 |
|
|
__IO uint32_t LTR;
|
| 367 |
|
|
__IO uint32_t SQR1;
|
| 368 |
|
|
__IO uint32_t SQR2;
|
| 369 |
|
|
__IO uint32_t SQR3;
|
| 370 |
|
|
__IO uint32_t JSQR;
|
| 371 |
|
|
__IO uint32_t JDR1;
|
| 372 |
|
|
__IO uint32_t JDR2;
|
| 373 |
|
|
__IO uint32_t JDR3;
|
| 374 |
|
|
__IO uint32_t JDR4;
|
| 375 |
|
|
__IO uint32_t DR;
|
| 376 |
|
|
} ADC_TypeDef;
|
| 377 |
|
|
|
| 378 |
|
|
/**
|
| 379 |
|
|
* @brief Backup Registers
|
| 380 |
|
|
*/
|
| 381 |
|
|
|
| 382 |
|
|
typedef struct
|
| 383 |
|
|
{
|
| 384 |
|
|
uint32_t RESERVED0;
|
| 385 |
|
|
__IO uint16_t DR1;
|
| 386 |
|
|
uint16_t RESERVED1;
|
| 387 |
|
|
__IO uint16_t DR2;
|
| 388 |
|
|
uint16_t RESERVED2;
|
| 389 |
|
|
__IO uint16_t DR3;
|
| 390 |
|
|
uint16_t RESERVED3;
|
| 391 |
|
|
__IO uint16_t DR4;
|
| 392 |
|
|
uint16_t RESERVED4;
|
| 393 |
|
|
__IO uint16_t DR5;
|
| 394 |
|
|
uint16_t RESERVED5;
|
| 395 |
|
|
__IO uint16_t DR6;
|
| 396 |
|
|
uint16_t RESERVED6;
|
| 397 |
|
|
__IO uint16_t DR7;
|
| 398 |
|
|
uint16_t RESERVED7;
|
| 399 |
|
|
__IO uint16_t DR8;
|
| 400 |
|
|
uint16_t RESERVED8;
|
| 401 |
|
|
__IO uint16_t DR9;
|
| 402 |
|
|
uint16_t RESERVED9;
|
| 403 |
|
|
__IO uint16_t DR10;
|
| 404 |
|
|
uint16_t RESERVED10;
|
| 405 |
|
|
__IO uint16_t RTCCR;
|
| 406 |
|
|
uint16_t RESERVED11;
|
| 407 |
|
|
__IO uint16_t CR;
|
| 408 |
|
|
uint16_t RESERVED12;
|
| 409 |
|
|
__IO uint16_t CSR;
|
| 410 |
|
|
uint16_t RESERVED13[5];
|
| 411 |
|
|
__IO uint16_t DR11;
|
| 412 |
|
|
uint16_t RESERVED14;
|
| 413 |
|
|
__IO uint16_t DR12;
|
| 414 |
|
|
uint16_t RESERVED15;
|
| 415 |
|
|
__IO uint16_t DR13;
|
| 416 |
|
|
uint16_t RESERVED16;
|
| 417 |
|
|
__IO uint16_t DR14;
|
| 418 |
|
|
uint16_t RESERVED17;
|
| 419 |
|
|
__IO uint16_t DR15;
|
| 420 |
|
|
uint16_t RESERVED18;
|
| 421 |
|
|
__IO uint16_t DR16;
|
| 422 |
|
|
uint16_t RESERVED19;
|
| 423 |
|
|
__IO uint16_t DR17;
|
| 424 |
|
|
uint16_t RESERVED20;
|
| 425 |
|
|
__IO uint16_t DR18;
|
| 426 |
|
|
uint16_t RESERVED21;
|
| 427 |
|
|
__IO uint16_t DR19;
|
| 428 |
|
|
uint16_t RESERVED22;
|
| 429 |
|
|
__IO uint16_t DR20;
|
| 430 |
|
|
uint16_t RESERVED23;
|
| 431 |
|
|
__IO uint16_t DR21;
|
| 432 |
|
|
uint16_t RESERVED24;
|
| 433 |
|
|
__IO uint16_t DR22;
|
| 434 |
|
|
uint16_t RESERVED25;
|
| 435 |
|
|
__IO uint16_t DR23;
|
| 436 |
|
|
uint16_t RESERVED26;
|
| 437 |
|
|
__IO uint16_t DR24;
|
| 438 |
|
|
uint16_t RESERVED27;
|
| 439 |
|
|
__IO uint16_t DR25;
|
| 440 |
|
|
uint16_t RESERVED28;
|
| 441 |
|
|
__IO uint16_t DR26;
|
| 442 |
|
|
uint16_t RESERVED29;
|
| 443 |
|
|
__IO uint16_t DR27;
|
| 444 |
|
|
uint16_t RESERVED30;
|
| 445 |
|
|
__IO uint16_t DR28;
|
| 446 |
|
|
uint16_t RESERVED31;
|
| 447 |
|
|
__IO uint16_t DR29;
|
| 448 |
|
|
uint16_t RESERVED32;
|
| 449 |
|
|
__IO uint16_t DR30;
|
| 450 |
|
|
uint16_t RESERVED33;
|
| 451 |
|
|
__IO uint16_t DR31;
|
| 452 |
|
|
uint16_t RESERVED34;
|
| 453 |
|
|
__IO uint16_t DR32;
|
| 454 |
|
|
uint16_t RESERVED35;
|
| 455 |
|
|
__IO uint16_t DR33;
|
| 456 |
|
|
uint16_t RESERVED36;
|
| 457 |
|
|
__IO uint16_t DR34;
|
| 458 |
|
|
uint16_t RESERVED37;
|
| 459 |
|
|
__IO uint16_t DR35;
|
| 460 |
|
|
uint16_t RESERVED38;
|
| 461 |
|
|
__IO uint16_t DR36;
|
| 462 |
|
|
uint16_t RESERVED39;
|
| 463 |
|
|
__IO uint16_t DR37;
|
| 464 |
|
|
uint16_t RESERVED40;
|
| 465 |
|
|
__IO uint16_t DR38;
|
| 466 |
|
|
uint16_t RESERVED41;
|
| 467 |
|
|
__IO uint16_t DR39;
|
| 468 |
|
|
uint16_t RESERVED42;
|
| 469 |
|
|
__IO uint16_t DR40;
|
| 470 |
|
|
uint16_t RESERVED43;
|
| 471 |
|
|
__IO uint16_t DR41;
|
| 472 |
|
|
uint16_t RESERVED44;
|
| 473 |
|
|
__IO uint16_t DR42;
|
| 474 |
|
|
uint16_t RESERVED45;
|
| 475 |
|
|
} BKP_TypeDef;
|
| 476 |
|
|
|
| 477 |
|
|
/**
|
| 478 |
|
|
* @brief Controller Area Network TxMailBox
|
| 479 |
|
|
*/
|
| 480 |
|
|
|
| 481 |
|
|
typedef struct
|
| 482 |
|
|
{
|
| 483 |
|
|
__IO uint32_t TIR;
|
| 484 |
|
|
__IO uint32_t TDTR;
|
| 485 |
|
|
__IO uint32_t TDLR;
|
| 486 |
|
|
__IO uint32_t TDHR;
|
| 487 |
|
|
} CAN_TxMailBox_TypeDef;
|
| 488 |
|
|
|
| 489 |
|
|
/**
|
| 490 |
|
|
* @brief Controller Area Network FIFOMailBox
|
| 491 |
|
|
*/
|
| 492 |
|
|
|
| 493 |
|
|
typedef struct
|
| 494 |
|
|
{
|
| 495 |
|
|
__IO uint32_t RIR;
|
| 496 |
|
|
__IO uint32_t RDTR;
|
| 497 |
|
|
__IO uint32_t RDLR;
|
| 498 |
|
|
__IO uint32_t RDHR;
|
| 499 |
|
|
} CAN_FIFOMailBox_TypeDef;
|
| 500 |
|
|
|
| 501 |
|
|
/**
|
| 502 |
|
|
* @brief Controller Area Network FilterRegister
|
| 503 |
|
|
*/
|
| 504 |
|
|
|
| 505 |
|
|
typedef struct
|
| 506 |
|
|
{
|
| 507 |
|
|
__IO uint32_t FR1;
|
| 508 |
|
|
__IO uint32_t FR2;
|
| 509 |
|
|
} CAN_FilterRegister_TypeDef;
|
| 510 |
|
|
|
| 511 |
|
|
/**
|
| 512 |
|
|
* @brief Controller Area Network
|
| 513 |
|
|
*/
|
| 514 |
|
|
|
| 515 |
|
|
typedef struct
|
| 516 |
|
|
{
|
| 517 |
|
|
__IO uint32_t MCR;
|
| 518 |
|
|
__IO uint32_t MSR;
|
| 519 |
|
|
__IO uint32_t TSR;
|
| 520 |
|
|
__IO uint32_t RF0R;
|
| 521 |
|
|
__IO uint32_t RF1R;
|
| 522 |
|
|
__IO uint32_t IER;
|
| 523 |
|
|
__IO uint32_t ESR;
|
| 524 |
|
|
__IO uint32_t BTR;
|
| 525 |
|
|
uint32_t RESERVED0[88];
|
| 526 |
|
|
CAN_TxMailBox_TypeDef sTxMailBox[3];
|
| 527 |
|
|
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
|
| 528 |
|
|
uint32_t RESERVED1[12];
|
| 529 |
|
|
__IO uint32_t FMR;
|
| 530 |
|
|
__IO uint32_t FM1R;
|
| 531 |
|
|
uint32_t RESERVED2;
|
| 532 |
|
|
__IO uint32_t FS1R;
|
| 533 |
|
|
uint32_t RESERVED3;
|
| 534 |
|
|
__IO uint32_t FFA1R;
|
| 535 |
|
|
uint32_t RESERVED4;
|
| 536 |
|
|
__IO uint32_t FA1R;
|
| 537 |
|
|
uint32_t RESERVED5[8];
|
| 538 |
|
|
#ifndef STM32F10X_CL
|
| 539 |
|
|
CAN_FilterRegister_TypeDef sFilterRegister[14];
|
| 540 |
|
|
#else
|
| 541 |
|
|
CAN_FilterRegister_TypeDef sFilterRegister[28];
|
| 542 |
|
|
#endif /* STM32F10X_CL */
|
| 543 |
|
|
} CAN_TypeDef;
|
| 544 |
|
|
|
| 545 |
|
|
/**
|
| 546 |
|
|
* @brief CRC calculation unit
|
| 547 |
|
|
*/
|
| 548 |
|
|
|
| 549 |
|
|
typedef struct
|
| 550 |
|
|
{
|
| 551 |
|
|
__IO uint32_t DR;
|
| 552 |
|
|
__IO uint8_t IDR;
|
| 553 |
|
|
uint8_t RESERVED0;
|
| 554 |
|
|
uint16_t RESERVED1;
|
| 555 |
|
|
__IO uint32_t CR;
|
| 556 |
|
|
} CRC_TypeDef;
|
| 557 |
|
|
|
| 558 |
|
|
/**
|
| 559 |
|
|
* @brief Digital to Analog Converter
|
| 560 |
|
|
*/
|
| 561 |
|
|
|
| 562 |
|
|
typedef struct
|
| 563 |
|
|
{
|
| 564 |
|
|
__IO uint32_t CR;
|
| 565 |
|
|
__IO uint32_t SWTRIGR;
|
| 566 |
|
|
__IO uint32_t DHR12R1;
|
| 567 |
|
|
__IO uint32_t DHR12L1;
|
| 568 |
|
|
__IO uint32_t DHR8R1;
|
| 569 |
|
|
__IO uint32_t DHR12R2;
|
| 570 |
|
|
__IO uint32_t DHR12L2;
|
| 571 |
|
|
__IO uint32_t DHR8R2;
|
| 572 |
|
|
__IO uint32_t DHR12RD;
|
| 573 |
|
|
__IO uint32_t DHR12LD;
|
| 574 |
|
|
__IO uint32_t DHR8RD;
|
| 575 |
|
|
__IO uint32_t DOR1;
|
| 576 |
|
|
__IO uint32_t DOR2;
|
| 577 |
|
|
} DAC_TypeDef;
|
| 578 |
|
|
|
| 579 |
|
|
/**
|
| 580 |
|
|
* @brief Debug MCU
|
| 581 |
|
|
*/
|
| 582 |
|
|
|
| 583 |
|
|
typedef struct
|
| 584 |
|
|
{
|
| 585 |
|
|
__IO uint32_t IDCODE;
|
| 586 |
|
|
__IO uint32_t CR;
|
| 587 |
|
|
}DBGMCU_TypeDef;
|
| 588 |
|
|
|
| 589 |
|
|
/**
|
| 590 |
|
|
* @brief DMA Controller
|
| 591 |
|
|
*/
|
| 592 |
|
|
|
| 593 |
|
|
typedef struct
|
| 594 |
|
|
{
|
| 595 |
|
|
__IO uint32_t CCR;
|
| 596 |
|
|
__IO uint32_t CNDTR;
|
| 597 |
|
|
__IO uint32_t CPAR;
|
| 598 |
|
|
__IO uint32_t CMAR;
|
| 599 |
|
|
} DMA_Channel_TypeDef;
|
| 600 |
|
|
|
| 601 |
|
|
typedef struct
|
| 602 |
|
|
{
|
| 603 |
|
|
__IO uint32_t ISR;
|
| 604 |
|
|
__IO uint32_t IFCR;
|
| 605 |
|
|
} DMA_TypeDef;
|
| 606 |
|
|
|
| 607 |
|
|
/**
|
| 608 |
|
|
* @brief Ethernet MAC
|
| 609 |
|
|
*/
|
| 610 |
|
|
|
| 611 |
|
|
typedef struct
|
| 612 |
|
|
{
|
| 613 |
|
|
__IO uint32_t MACCR;
|
| 614 |
|
|
__IO uint32_t MACFFR;
|
| 615 |
|
|
__IO uint32_t MACHTHR;
|
| 616 |
|
|
__IO uint32_t MACHTLR;
|
| 617 |
|
|
__IO uint32_t MACMIIAR;
|
| 618 |
|
|
__IO uint32_t MACMIIDR;
|
| 619 |
|
|
__IO uint32_t MACFCR;
|
| 620 |
|
|
__IO uint32_t MACVLANTR; /* 8 */
|
| 621 |
|
|
uint32_t RESERVED0[2];
|
| 622 |
|
|
__IO uint32_t MACRWUFFR; /* 11 */
|
| 623 |
|
|
__IO uint32_t MACPMTCSR;
|
| 624 |
|
|
uint32_t RESERVED1[2];
|
| 625 |
|
|
__IO uint32_t MACSR; /* 15 */
|
| 626 |
|
|
__IO uint32_t MACIMR;
|
| 627 |
|
|
__IO uint32_t MACA0HR;
|
| 628 |
|
|
__IO uint32_t MACA0LR;
|
| 629 |
|
|
__IO uint32_t MACA1HR;
|
| 630 |
|
|
__IO uint32_t MACA1LR;
|
| 631 |
|
|
__IO uint32_t MACA2HR;
|
| 632 |
|
|
__IO uint32_t MACA2LR;
|
| 633 |
|
|
__IO uint32_t MACA3HR;
|
| 634 |
|
|
__IO uint32_t MACA3LR; /* 24 */
|
| 635 |
|
|
uint32_t RESERVED2[40];
|
| 636 |
|
|
__IO uint32_t MMCCR; /* 65 */
|
| 637 |
|
|
__IO uint32_t MMCRIR;
|
| 638 |
|
|
__IO uint32_t MMCTIR;
|
| 639 |
|
|
__IO uint32_t MMCRIMR;
|
| 640 |
|
|
__IO uint32_t MMCTIMR; /* 69 */
|
| 641 |
|
|
uint32_t RESERVED3[14];
|
| 642 |
|
|
__IO uint32_t MMCTGFSCCR; /* 84 */
|
| 643 |
|
|
__IO uint32_t MMCTGFMSCCR;
|
| 644 |
|
|
uint32_t RESERVED4[5];
|
| 645 |
|
|
__IO uint32_t MMCTGFCR;
|
| 646 |
|
|
uint32_t RESERVED5[10];
|
| 647 |
|
|
__IO uint32_t MMCRFCECR;
|
| 648 |
|
|
__IO uint32_t MMCRFAECR;
|
| 649 |
|
|
uint32_t RESERVED6[10];
|
| 650 |
|
|
__IO uint32_t MMCRGUFCR;
|
| 651 |
|
|
uint32_t RESERVED7[334];
|
| 652 |
|
|
__IO uint32_t PTPTSCR;
|
| 653 |
|
|
__IO uint32_t PTPSSIR;
|
| 654 |
|
|
__IO uint32_t PTPTSHR;
|
| 655 |
|
|
__IO uint32_t PTPTSLR;
|
| 656 |
|
|
__IO uint32_t PTPTSHUR;
|
| 657 |
|
|
__IO uint32_t PTPTSLUR;
|
| 658 |
|
|
__IO uint32_t PTPTSAR;
|
| 659 |
|
|
__IO uint32_t PTPTTHR;
|
| 660 |
|
|
__IO uint32_t PTPTTLR;
|
| 661 |
|
|
uint32_t RESERVED8[567];
|
| 662 |
|
|
__IO uint32_t DMABMR;
|
| 663 |
|
|
__IO uint32_t DMATPDR;
|
| 664 |
|
|
__IO uint32_t DMARPDR;
|
| 665 |
|
|
__IO uint32_t DMARDLAR;
|
| 666 |
|
|
__IO uint32_t DMATDLAR;
|
| 667 |
|
|
__IO uint32_t DMASR;
|
| 668 |
|
|
__IO uint32_t DMAOMR;
|
| 669 |
|
|
__IO uint32_t DMAIER;
|
| 670 |
|
|
__IO uint32_t DMAMFBOCR;
|
| 671 |
|
|
uint32_t RESERVED9[9];
|
| 672 |
|
|
__IO uint32_t DMACHTDR;
|
| 673 |
|
|
__IO uint32_t DMACHRDR;
|
| 674 |
|
|
__IO uint32_t DMACHTBAR;
|
| 675 |
|
|
__IO uint32_t DMACHRBAR;
|
| 676 |
|
|
} ETH_TypeDef;
|
| 677 |
|
|
|
| 678 |
|
|
/**
|
| 679 |
|
|
* @brief External Interrupt/Event Controller
|
| 680 |
|
|
*/
|
| 681 |
|
|
|
| 682 |
|
|
typedef struct
|
| 683 |
|
|
{
|
| 684 |
|
|
__IO uint32_t IMR;
|
| 685 |
|
|
__IO uint32_t EMR;
|
| 686 |
|
|
__IO uint32_t RTSR;
|
| 687 |
|
|
__IO uint32_t FTSR;
|
| 688 |
|
|
__IO uint32_t SWIER;
|
| 689 |
|
|
__IO uint32_t PR;
|
| 690 |
|
|
} EXTI_TypeDef;
|
| 691 |
|
|
|
| 692 |
|
|
/**
|
| 693 |
|
|
* @brief FLASH Registers
|
| 694 |
|
|
*/
|
| 695 |
|
|
|
| 696 |
|
|
typedef struct
|
| 697 |
|
|
{
|
| 698 |
|
|
__IO uint32_t ACR;
|
| 699 |
|
|
__IO uint32_t KEYR;
|
| 700 |
|
|
__IO uint32_t OPTKEYR;
|
| 701 |
|
|
__IO uint32_t SR;
|
| 702 |
|
|
__IO uint32_t CR;
|
| 703 |
|
|
__IO uint32_t AR;
|
| 704 |
|
|
__IO uint32_t RESERVED;
|
| 705 |
|
|
__IO uint32_t OBR;
|
| 706 |
|
|
__IO uint32_t WRPR;
|
| 707 |
|
|
} FLASH_TypeDef;
|
| 708 |
|
|
|
| 709 |
|
|
/**
|
| 710 |
|
|
* @brief Option Bytes Registers
|
| 711 |
|
|
*/
|
| 712 |
|
|
|
| 713 |
|
|
typedef struct
|
| 714 |
|
|
{
|
| 715 |
|
|
__IO uint16_t RDP;
|
| 716 |
|
|
__IO uint16_t USER;
|
| 717 |
|
|
__IO uint16_t Data0;
|
| 718 |
|
|
__IO uint16_t Data1;
|
| 719 |
|
|
__IO uint16_t WRP0;
|
| 720 |
|
|
__IO uint16_t WRP1;
|
| 721 |
|
|
__IO uint16_t WRP2;
|
| 722 |
|
|
__IO uint16_t WRP3;
|
| 723 |
|
|
} OB_TypeDef;
|
| 724 |
|
|
|
| 725 |
|
|
/**
|
| 726 |
|
|
* @brief Flexible Static Memory Controller
|
| 727 |
|
|
*/
|
| 728 |
|
|
|
| 729 |
|
|
typedef struct
|
| 730 |
|
|
{
|
| 731 |
|
|
__IO uint32_t BTCR[8];
|
| 732 |
|
|
} FSMC_Bank1_TypeDef;
|
| 733 |
|
|
|
| 734 |
|
|
/**
|
| 735 |
|
|
* @brief Flexible Static Memory Controller Bank1E
|
| 736 |
|
|
*/
|
| 737 |
|
|
|
| 738 |
|
|
typedef struct
|
| 739 |
|
|
{
|
| 740 |
|
|
__IO uint32_t BWTR[7];
|
| 741 |
|
|
} FSMC_Bank1E_TypeDef;
|
| 742 |
|
|
|
| 743 |
|
|
/**
|
| 744 |
|
|
* @brief Flexible Static Memory Controller Bank2
|
| 745 |
|
|
*/
|
| 746 |
|
|
|
| 747 |
|
|
typedef struct
|
| 748 |
|
|
{
|
| 749 |
|
|
__IO uint32_t PCR2;
|
| 750 |
|
|
__IO uint32_t SR2;
|
| 751 |
|
|
__IO uint32_t PMEM2;
|
| 752 |
|
|
__IO uint32_t PATT2;
|
| 753 |
|
|
uint32_t RESERVED0;
|
| 754 |
|
|
__IO uint32_t ECCR2;
|
| 755 |
|
|
} FSMC_Bank2_TypeDef;
|
| 756 |
|
|
|
| 757 |
|
|
/**
|
| 758 |
|
|
* @brief Flexible Static Memory Controller Bank3
|
| 759 |
|
|
*/
|
| 760 |
|
|
|
| 761 |
|
|
typedef struct
|
| 762 |
|
|
{
|
| 763 |
|
|
__IO uint32_t PCR3;
|
| 764 |
|
|
__IO uint32_t SR3;
|
| 765 |
|
|
__IO uint32_t PMEM3;
|
| 766 |
|
|
__IO uint32_t PATT3;
|
| 767 |
|
|
uint32_t RESERVED0;
|
| 768 |
|
|
__IO uint32_t ECCR3;
|
| 769 |
|
|
} FSMC_Bank3_TypeDef;
|
| 770 |
|
|
|
| 771 |
|
|
/**
|
| 772 |
|
|
* @brief Flexible Static Memory Controller Bank4
|
| 773 |
|
|
*/
|
| 774 |
|
|
|
| 775 |
|
|
typedef struct
|
| 776 |
|
|
{
|
| 777 |
|
|
__IO uint32_t PCR4;
|
| 778 |
|
|
__IO uint32_t SR4;
|
| 779 |
|
|
__IO uint32_t PMEM4;
|
| 780 |
|
|
__IO uint32_t PATT4;
|
| 781 |
|
|
__IO uint32_t PIO4;
|
| 782 |
|
|
} FSMC_Bank4_TypeDef;
|
| 783 |
|
|
|
| 784 |
|
|
/**
|
| 785 |
|
|
* @brief General Purpose I/O
|
| 786 |
|
|
*/
|
| 787 |
|
|
|
| 788 |
|
|
typedef struct
|
| 789 |
|
|
{
|
| 790 |
|
|
__IO uint32_t CRL;
|
| 791 |
|
|
__IO uint32_t CRH;
|
| 792 |
|
|
__IO uint32_t IDR;
|
| 793 |
|
|
__IO uint32_t ODR;
|
| 794 |
|
|
__IO uint32_t BSRR;
|
| 795 |
|
|
__IO uint32_t BRR;
|
| 796 |
|
|
__IO uint32_t LCKR;
|
| 797 |
|
|
} GPIO_TypeDef;
|
| 798 |
|
|
|
| 799 |
|
|
/**
|
| 800 |
|
|
* @brief Alternate Function I/O
|
| 801 |
|
|
*/
|
| 802 |
|
|
|
| 803 |
|
|
typedef struct
|
| 804 |
|
|
{
|
| 805 |
|
|
__IO uint32_t EVCR;
|
| 806 |
|
|
__IO uint32_t MAPR;
|
| 807 |
|
|
__IO uint32_t EXTICR[4];
|
| 808 |
|
|
} AFIO_TypeDef;
|
| 809 |
|
|
/**
|
| 810 |
|
|
* @brief Inter-integrated Circuit Interface
|
| 811 |
|
|
*/
|
| 812 |
|
|
|
| 813 |
|
|
typedef struct
|
| 814 |
|
|
{
|
| 815 |
|
|
__IO uint16_t CR1;
|
| 816 |
|
|
uint16_t RESERVED0;
|
| 817 |
|
|
__IO uint16_t CR2;
|
| 818 |
|
|
uint16_t RESERVED1;
|
| 819 |
|
|
__IO uint16_t OAR1;
|
| 820 |
|
|
uint16_t RESERVED2;
|
| 821 |
|
|
__IO uint16_t OAR2;
|
| 822 |
|
|
uint16_t RESERVED3;
|
| 823 |
|
|
__IO uint16_t DR;
|
| 824 |
|
|
uint16_t RESERVED4;
|
| 825 |
|
|
__IO uint16_t SR1;
|
| 826 |
|
|
uint16_t RESERVED5;
|
| 827 |
|
|
__IO uint16_t SR2;
|
| 828 |
|
|
uint16_t RESERVED6;
|
| 829 |
|
|
__IO uint16_t CCR;
|
| 830 |
|
|
uint16_t RESERVED7;
|
| 831 |
|
|
__IO uint16_t TRISE;
|
| 832 |
|
|
uint16_t RESERVED8;
|
| 833 |
|
|
} I2C_TypeDef;
|
| 834 |
|
|
|
| 835 |
|
|
/**
|
| 836 |
|
|
* @brief Independent WATCHDOG
|
| 837 |
|
|
*/
|
| 838 |
|
|
|
| 839 |
|
|
typedef struct
|
| 840 |
|
|
{
|
| 841 |
|
|
__IO uint32_t KR;
|
| 842 |
|
|
__IO uint32_t PR;
|
| 843 |
|
|
__IO uint32_t RLR;
|
| 844 |
|
|
__IO uint32_t SR;
|
| 845 |
|
|
} IWDG_TypeDef;
|
| 846 |
|
|
|
| 847 |
|
|
/**
|
| 848 |
|
|
* @brief Power Control
|
| 849 |
|
|
*/
|
| 850 |
|
|
|
| 851 |
|
|
typedef struct
|
| 852 |
|
|
{
|
| 853 |
|
|
__IO uint32_t CR;
|
| 854 |
|
|
__IO uint32_t CSR;
|
| 855 |
|
|
} PWR_TypeDef;
|
| 856 |
|
|
|
| 857 |
|
|
/**
|
| 858 |
|
|
* @brief Reset and Clock Control
|
| 859 |
|
|
*/
|
| 860 |
|
|
|
| 861 |
|
|
typedef struct
|
| 862 |
|
|
{
|
| 863 |
|
|
__IO uint32_t CR;
|
| 864 |
|
|
__IO uint32_t CFGR;
|
| 865 |
|
|
__IO uint32_t CIR;
|
| 866 |
|
|
__IO uint32_t APB2RSTR;
|
| 867 |
|
|
__IO uint32_t APB1RSTR;
|
| 868 |
|
|
__IO uint32_t AHBENR;
|
| 869 |
|
|
__IO uint32_t APB2ENR;
|
| 870 |
|
|
__IO uint32_t APB1ENR;
|
| 871 |
|
|
__IO uint32_t BDCR;
|
| 872 |
|
|
__IO uint32_t CSR;
|
| 873 |
|
|
#ifdef STM32F10X_CL
|
| 874 |
|
|
__IO uint32_t AHBRSTR;
|
| 875 |
|
|
__IO uint32_t CFGR2;
|
| 876 |
|
|
#endif /* STM32F10X_CL */
|
| 877 |
|
|
} RCC_TypeDef;
|
| 878 |
|
|
|
| 879 |
|
|
/**
|
| 880 |
|
|
* @brief Real-Time Clock
|
| 881 |
|
|
*/
|
| 882 |
|
|
|
| 883 |
|
|
typedef struct
|
| 884 |
|
|
{
|
| 885 |
|
|
__IO uint16_t CRH;
|
| 886 |
|
|
uint16_t RESERVED0;
|
| 887 |
|
|
__IO uint16_t CRL;
|
| 888 |
|
|
uint16_t RESERVED1;
|
| 889 |
|
|
__IO uint16_t PRLH;
|
| 890 |
|
|
uint16_t RESERVED2;
|
| 891 |
|
|
__IO uint16_t PRLL;
|
| 892 |
|
|
uint16_t RESERVED3;
|
| 893 |
|
|
__IO uint16_t DIVH;
|
| 894 |
|
|
uint16_t RESERVED4;
|
| 895 |
|
|
__IO uint16_t DIVL;
|
| 896 |
|
|
uint16_t RESERVED5;
|
| 897 |
|
|
__IO uint16_t CNTH;
|
| 898 |
|
|
uint16_t RESERVED6;
|
| 899 |
|
|
__IO uint16_t CNTL;
|
| 900 |
|
|
uint16_t RESERVED7;
|
| 901 |
|
|
__IO uint16_t ALRH;
|
| 902 |
|
|
uint16_t RESERVED8;
|
| 903 |
|
|
__IO uint16_t ALRL;
|
| 904 |
|
|
uint16_t RESERVED9;
|
| 905 |
|
|
} RTC_TypeDef;
|
| 906 |
|
|
|
| 907 |
|
|
/**
|
| 908 |
|
|
* @brief SD host Interface
|
| 909 |
|
|
*/
|
| 910 |
|
|
|
| 911 |
|
|
typedef struct
|
| 912 |
|
|
{
|
| 913 |
|
|
__IO uint32_t POWER;
|
| 914 |
|
|
__IO uint32_t CLKCR;
|
| 915 |
|
|
__IO uint32_t ARG;
|
| 916 |
|
|
__IO uint32_t CMD;
|
| 917 |
|
|
__I uint32_t RESPCMD;
|
| 918 |
|
|
__I uint32_t RESP1;
|
| 919 |
|
|
__I uint32_t RESP2;
|
| 920 |
|
|
__I uint32_t RESP3;
|
| 921 |
|
|
__I uint32_t RESP4;
|
| 922 |
|
|
__IO uint32_t DTIMER;
|
| 923 |
|
|
__IO uint32_t DLEN;
|
| 924 |
|
|
__IO uint32_t DCTRL;
|
| 925 |
|
|
__I uint32_t DCOUNT;
|
| 926 |
|
|
__I uint32_t STA;
|
| 927 |
|
|
__IO uint32_t ICR;
|
| 928 |
|
|
__IO uint32_t MASK;
|
| 929 |
|
|
uint32_t RESERVED0[2];
|
| 930 |
|
|
__I uint32_t FIFOCNT;
|
| 931 |
|
|
uint32_t RESERVED1[13];
|
| 932 |
|
|
__IO uint32_t FIFO;
|
| 933 |
|
|
} SDIO_TypeDef;
|
| 934 |
|
|
|
| 935 |
|
|
/**
|
| 936 |
|
|
* @brief Serial Peripheral Interface
|
| 937 |
|
|
*/
|
| 938 |
|
|
|
| 939 |
|
|
typedef struct
|
| 940 |
|
|
{
|
| 941 |
|
|
__IO uint16_t CR1;
|
| 942 |
|
|
uint16_t RESERVED0;
|
| 943 |
|
|
__IO uint16_t CR2;
|
| 944 |
|
|
uint16_t RESERVED1;
|
| 945 |
|
|
__IO uint16_t SR;
|
| 946 |
|
|
uint16_t RESERVED2;
|
| 947 |
|
|
__IO uint16_t DR;
|
| 948 |
|
|
uint16_t RESERVED3;
|
| 949 |
|
|
__IO uint16_t CRCPR;
|
| 950 |
|
|
uint16_t RESERVED4;
|
| 951 |
|
|
__IO uint16_t RXCRCR;
|
| 952 |
|
|
uint16_t RESERVED5;
|
| 953 |
|
|
__IO uint16_t TXCRCR;
|
| 954 |
|
|
uint16_t RESERVED6;
|
| 955 |
|
|
__IO uint16_t I2SCFGR;
|
| 956 |
|
|
uint16_t RESERVED7;
|
| 957 |
|
|
__IO uint16_t I2SPR;
|
| 958 |
|
|
uint16_t RESERVED8;
|
| 959 |
|
|
} SPI_TypeDef;
|
| 960 |
|
|
|
| 961 |
|
|
/**
|
| 962 |
|
|
* @brief TIM
|
| 963 |
|
|
*/
|
| 964 |
|
|
|
| 965 |
|
|
typedef struct
|
| 966 |
|
|
{
|
| 967 |
|
|
__IO uint16_t CR1;
|
| 968 |
|
|
uint16_t RESERVED0;
|
| 969 |
|
|
__IO uint16_t CR2;
|
| 970 |
|
|
uint16_t RESERVED1;
|
| 971 |
|
|
__IO uint16_t SMCR;
|
| 972 |
|
|
uint16_t RESERVED2;
|
| 973 |
|
|
__IO uint16_t DIER;
|
| 974 |
|
|
uint16_t RESERVED3;
|
| 975 |
|
|
__IO uint16_t SR;
|
| 976 |
|
|
uint16_t RESERVED4;
|
| 977 |
|
|
__IO uint16_t EGR;
|
| 978 |
|
|
uint16_t RESERVED5;
|
| 979 |
|
|
__IO uint16_t CCMR1;
|
| 980 |
|
|
uint16_t RESERVED6;
|
| 981 |
|
|
__IO uint16_t CCMR2;
|
| 982 |
|
|
uint16_t RESERVED7;
|
| 983 |
|
|
__IO uint16_t CCER;
|
| 984 |
|
|
uint16_t RESERVED8;
|
| 985 |
|
|
__IO uint16_t CNT;
|
| 986 |
|
|
uint16_t RESERVED9;
|
| 987 |
|
|
__IO uint16_t PSC;
|
| 988 |
|
|
uint16_t RESERVED10;
|
| 989 |
|
|
__IO uint16_t ARR;
|
| 990 |
|
|
uint16_t RESERVED11;
|
| 991 |
|
|
__IO uint16_t RCR;
|
| 992 |
|
|
uint16_t RESERVED12;
|
| 993 |
|
|
__IO uint16_t CCR1;
|
| 994 |
|
|
uint16_t RESERVED13;
|
| 995 |
|
|
__IO uint16_t CCR2;
|
| 996 |
|
|
uint16_t RESERVED14;
|
| 997 |
|
|
__IO uint16_t CCR3;
|
| 998 |
|
|
uint16_t RESERVED15;
|
| 999 |
|
|
__IO uint16_t CCR4;
|
| 1000 |
|
|
uint16_t RESERVED16;
|
| 1001 |
|
|
__IO uint16_t BDTR;
|
| 1002 |
|
|
uint16_t RESERVED17;
|
| 1003 |
|
|
__IO uint16_t DCR;
|
| 1004 |
|
|
uint16_t RESERVED18;
|
| 1005 |
|
|
__IO uint16_t DMAR;
|
| 1006 |
|
|
uint16_t RESERVED19;
|
| 1007 |
|
|
} TIM_TypeDef;
|
| 1008 |
|
|
|
| 1009 |
|
|
/**
|
| 1010 |
|
|
* @brief Universal Synchronous Asynchronous Receiver Transmitter
|
| 1011 |
|
|
*/
|
| 1012 |
|
|
|
| 1013 |
|
|
typedef struct
|
| 1014 |
|
|
{
|
| 1015 |
|
|
__IO uint16_t SR;
|
| 1016 |
|
|
uint16_t RESERVED0;
|
| 1017 |
|
|
__IO uint16_t DR;
|
| 1018 |
|
|
uint16_t RESERVED1;
|
| 1019 |
|
|
__IO uint16_t BRR;
|
| 1020 |
|
|
uint16_t RESERVED2;
|
| 1021 |
|
|
__IO uint16_t CR1;
|
| 1022 |
|
|
uint16_t RESERVED3;
|
| 1023 |
|
|
__IO uint16_t CR2;
|
| 1024 |
|
|
uint16_t RESERVED4;
|
| 1025 |
|
|
__IO uint16_t CR3;
|
| 1026 |
|
|
uint16_t RESERVED5;
|
| 1027 |
|
|
__IO uint16_t GTPR;
|
| 1028 |
|
|
uint16_t RESERVED6;
|
| 1029 |
|
|
} USART_TypeDef;
|
| 1030 |
|
|
|
| 1031 |
|
|
/**
|
| 1032 |
|
|
* @brief Window WATCHDOG
|
| 1033 |
|
|
*/
|
| 1034 |
|
|
|
| 1035 |
|
|
typedef struct
|
| 1036 |
|
|
{
|
| 1037 |
|
|
__IO uint32_t CR;
|
| 1038 |
|
|
__IO uint32_t CFR;
|
| 1039 |
|
|
__IO uint32_t SR;
|
| 1040 |
|
|
} WWDG_TypeDef;
|
| 1041 |
|
|
|
| 1042 |
|
|
/**
|
| 1043 |
|
|
* @}
|
| 1044 |
|
|
*/
|
| 1045 |
|
|
|
| 1046 |
|
|
/** @addtogroup Peripheral_memory_map
|
| 1047 |
|
|
* @{
|
| 1048 |
|
|
*/
|
| 1049 |
|
|
|
| 1050 |
|
|
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
|
| 1051 |
|
|
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
|
| 1052 |
|
|
|
| 1053 |
|
|
#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
|
| 1054 |
|
|
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
|
| 1055 |
|
|
|
| 1056 |
|
|
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
|
| 1057 |
|
|
|
| 1058 |
|
|
/*!< Peripheral memory map */
|
| 1059 |
|
|
#define APB1PERIPH_BASE PERIPH_BASE
|
| 1060 |
|
|
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
| 1061 |
|
|
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
| 1062 |
|
|
|
| 1063 |
|
|
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
|
| 1064 |
|
|
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
|
| 1065 |
|
|
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
|
| 1066 |
|
|
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
|
| 1067 |
|
|
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
|
| 1068 |
|
|
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
|
| 1069 |
|
|
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
| 1070 |
|
|
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
|
| 1071 |
|
|
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
|
| 1072 |
|
|
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
|
| 1073 |
|
|
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
|
| 1074 |
|
|
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
|
| 1075 |
|
|
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
|
| 1076 |
|
|
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
|
| 1077 |
|
|
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
|
| 1078 |
|
|
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
|
| 1079 |
|
|
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
|
| 1080 |
|
|
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
|
| 1081 |
|
|
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
|
| 1082 |
|
|
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
|
| 1083 |
|
|
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
|
| 1084 |
|
|
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
|
| 1085 |
|
|
|
| 1086 |
|
|
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
|
| 1087 |
|
|
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
|
| 1088 |
|
|
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
|
| 1089 |
|
|
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
|
| 1090 |
|
|
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
|
| 1091 |
|
|
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
|
| 1092 |
|
|
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
|
| 1093 |
|
|
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
|
| 1094 |
|
|
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
|
| 1095 |
|
|
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
|
| 1096 |
|
|
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
|
| 1097 |
|
|
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
|
| 1098 |
|
|
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
|
| 1099 |
|
|
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
|
| 1100 |
|
|
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
|
| 1101 |
|
|
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
|
| 1102 |
|
|
|
| 1103 |
|
|
#define SDIO_BASE (PERIPH_BASE + 0x18000)
|
| 1104 |
|
|
|
| 1105 |
|
|
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
|
| 1106 |
|
|
#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
|
| 1107 |
|
|
#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
|
| 1108 |
|
|
#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
|
| 1109 |
|
|
#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
|
| 1110 |
|
|
#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
|
| 1111 |
|
|
#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
|
| 1112 |
|
|
#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
|
| 1113 |
|
|
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
|
| 1114 |
|
|
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
|
| 1115 |
|
|
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
|
| 1116 |
|
|
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
|
| 1117 |
|
|
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
|
| 1118 |
|
|
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
|
| 1119 |
|
|
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
|
| 1120 |
|
|
#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
|
| 1121 |
|
|
|
| 1122 |
|
|
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
|
| 1123 |
|
|
#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
|
| 1124 |
|
|
|
| 1125 |
|
|
#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
|
| 1126 |
|
|
|
| 1127 |
|
|
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
|
| 1128 |
|
|
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
|
| 1129 |
|
|
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
|
| 1130 |
|
|
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
|
| 1131 |
|
|
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
|
| 1132 |
|
|
|
| 1133 |
|
|
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
| 1134 |
|
|
|
| 1135 |
|
|
/**
|
| 1136 |
|
|
* @}
|
| 1137 |
|
|
*/
|
| 1138 |
|
|
|
| 1139 |
|
|
/** @addtogroup Peripheral_declaration
|
| 1140 |
|
|
* @{
|
| 1141 |
|
|
*/
|
| 1142 |
|
|
|
| 1143 |
|
|
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
|
| 1144 |
|
|
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
| 1145 |
|
|
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
|
| 1146 |
|
|
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
|
| 1147 |
|
|
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
|
| 1148 |
|
|
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
|
| 1149 |
|
|
#define RTC ((RTC_TypeDef *) RTC_BASE)
|
| 1150 |
|
|
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
| 1151 |
|
|
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
| 1152 |
|
|
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
|
| 1153 |
|
|
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
|
| 1154 |
|
|
#define USART2 ((USART_TypeDef *) USART2_BASE)
|
| 1155 |
|
|
#define USART3 ((USART_TypeDef *) USART3_BASE)
|
| 1156 |
|
|
#define UART4 ((USART_TypeDef *) UART4_BASE)
|
| 1157 |
|
|
#define UART5 ((USART_TypeDef *) UART5_BASE)
|
| 1158 |
|
|
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
| 1159 |
|
|
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
| 1160 |
|
|
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
|
| 1161 |
|
|
#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
|
| 1162 |
|
|
#define BKP ((BKP_TypeDef *) BKP_BASE)
|
| 1163 |
|
|
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
| 1164 |
|
|
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
| 1165 |
|
|
#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
|
| 1166 |
|
|
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
| 1167 |
|
|
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
| 1168 |
|
|
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
| 1169 |
|
|
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
| 1170 |
|
|
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
| 1171 |
|
|
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
| 1172 |
|
|
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
|
| 1173 |
|
|
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
|
| 1174 |
|
|
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
| 1175 |
|
|
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
|
| 1176 |
|
|
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
| 1177 |
|
|
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
| 1178 |
|
|
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
|
| 1179 |
|
|
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
| 1180 |
|
|
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
|
| 1181 |
|
|
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
|
| 1182 |
|
|
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
| 1183 |
|
|
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
|
| 1184 |
|
|
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
|
| 1185 |
|
|
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
|
| 1186 |
|
|
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
|
| 1187 |
|
|
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
|
| 1188 |
|
|
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
|
| 1189 |
|
|
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
|
| 1190 |
|
|
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
|
| 1191 |
|
|
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
|
| 1192 |
|
|
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
|
| 1193 |
|
|
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
|
| 1194 |
|
|
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
|
| 1195 |
|
|
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
|
| 1196 |
|
|
#define RCC ((RCC_TypeDef *) RCC_BASE)
|
| 1197 |
|
|
#define CRC ((CRC_TypeDef *) CRC_BASE)
|
| 1198 |
|
|
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
| 1199 |
|
|
#define OB ((OB_TypeDef *) OB_BASE)
|
| 1200 |
|
|
#define ETH ((ETH_TypeDef *) ETH_BASE)
|
| 1201 |
|
|
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
|
| 1202 |
|
|
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
|
| 1203 |
|
|
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
|
| 1204 |
|
|
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
|
| 1205 |
|
|
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
|
| 1206 |
|
|
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
| 1207 |
|
|
|
| 1208 |
|
|
/**
|
| 1209 |
|
|
* @}
|
| 1210 |
|
|
*/
|
| 1211 |
|
|
|
| 1212 |
|
|
/** @addtogroup Exported_constants
|
| 1213 |
|
|
* @{
|
| 1214 |
|
|
*/
|
| 1215 |
|
|
|
| 1216 |
|
|
/** @addtogroup Peripheral_Registers_Bits_Definition
|
| 1217 |
|
|
* @{
|
| 1218 |
|
|
*/
|
| 1219 |
|
|
|
| 1220 |
|
|
/******************************************************************************/
|
| 1221 |
|
|
/* Peripheral Registers_Bits_Definition */
|
| 1222 |
|
|
/******************************************************************************/
|
| 1223 |
|
|
|
| 1224 |
|
|
/******************************************************************************/
|
| 1225 |
|
|
/* */
|
| 1226 |
|
|
/* CRC calculation unit */
|
| 1227 |
|
|
/* */
|
| 1228 |
|
|
/******************************************************************************/
|
| 1229 |
|
|
|
| 1230 |
|
|
/******************* Bit definition for CRC_DR register *********************/
|
| 1231 |
|
|
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
| 1232 |
|
|
|
| 1233 |
|
|
|
| 1234 |
|
|
/******************* Bit definition for CRC_IDR register ********************/
|
| 1235 |
|
|
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
| 1236 |
|
|
|
| 1237 |
|
|
|
| 1238 |
|
|
/******************** Bit definition for CRC_CR register ********************/
|
| 1239 |
|
|
#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
|
| 1240 |
|
|
|
| 1241 |
|
|
/******************************************************************************/
|
| 1242 |
|
|
/* */
|
| 1243 |
|
|
/* Power Control */
|
| 1244 |
|
|
/* */
|
| 1245 |
|
|
/******************************************************************************/
|
| 1246 |
|
|
|
| 1247 |
|
|
/******************** Bit definition for PWR_CR register ********************/
|
| 1248 |
|
|
#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
|
| 1249 |
|
|
#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
|
| 1250 |
|
|
#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
|
| 1251 |
|
|
#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
|
| 1252 |
|
|
#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
|
| 1253 |
|
|
|
| 1254 |
|
|
#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
|
| 1255 |
|
|
#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
|
| 1256 |
|
|
#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
|
| 1257 |
|
|
#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
|
| 1258 |
|
|
|
| 1259 |
|
|
/*!< PVD level configuration */
|
| 1260 |
|
|
#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
|
| 1261 |
|
|
#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
|
| 1262 |
|
|
#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
|
| 1263 |
|
|
#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
|
| 1264 |
|
|
#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
|
| 1265 |
|
|
#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
|
| 1266 |
|
|
#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
|
| 1267 |
|
|
#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
|
| 1268 |
|
|
|
| 1269 |
|
|
#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
|
| 1270 |
|
|
|
| 1271 |
|
|
|
| 1272 |
|
|
/******************* Bit definition for PWR_CSR register ********************/
|
| 1273 |
|
|
#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
|
| 1274 |
|
|
#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
|
| 1275 |
|
|
#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
|
| 1276 |
|
|
#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
|
| 1277 |
|
|
|
| 1278 |
|
|
/******************************************************************************/
|
| 1279 |
|
|
/* */
|
| 1280 |
|
|
/* Backup registers */
|
| 1281 |
|
|
/* */
|
| 1282 |
|
|
/******************************************************************************/
|
| 1283 |
|
|
|
| 1284 |
|
|
/******************* Bit definition for BKP_DR1 register ********************/
|
| 1285 |
|
|
#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1286 |
|
|
|
| 1287 |
|
|
/******************* Bit definition for BKP_DR2 register ********************/
|
| 1288 |
|
|
#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1289 |
|
|
|
| 1290 |
|
|
/******************* Bit definition for BKP_DR3 register ********************/
|
| 1291 |
|
|
#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1292 |
|
|
|
| 1293 |
|
|
/******************* Bit definition for BKP_DR4 register ********************/
|
| 1294 |
|
|
#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1295 |
|
|
|
| 1296 |
|
|
/******************* Bit definition for BKP_DR5 register ********************/
|
| 1297 |
|
|
#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1298 |
|
|
|
| 1299 |
|
|
/******************* Bit definition for BKP_DR6 register ********************/
|
| 1300 |
|
|
#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1301 |
|
|
|
| 1302 |
|
|
/******************* Bit definition for BKP_DR7 register ********************/
|
| 1303 |
|
|
#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1304 |
|
|
|
| 1305 |
|
|
/******************* Bit definition for BKP_DR8 register ********************/
|
| 1306 |
|
|
#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1307 |
|
|
|
| 1308 |
|
|
/******************* Bit definition for BKP_DR9 register ********************/
|
| 1309 |
|
|
#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1310 |
|
|
|
| 1311 |
|
|
/******************* Bit definition for BKP_DR10 register *******************/
|
| 1312 |
|
|
#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1313 |
|
|
|
| 1314 |
|
|
/******************* Bit definition for BKP_DR11 register *******************/
|
| 1315 |
|
|
#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1316 |
|
|
|
| 1317 |
|
|
/******************* Bit definition for BKP_DR12 register *******************/
|
| 1318 |
|
|
#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1319 |
|
|
|
| 1320 |
|
|
/******************* Bit definition for BKP_DR13 register *******************/
|
| 1321 |
|
|
#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1322 |
|
|
|
| 1323 |
|
|
/******************* Bit definition for BKP_DR14 register *******************/
|
| 1324 |
|
|
#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1325 |
|
|
|
| 1326 |
|
|
/******************* Bit definition for BKP_DR15 register *******************/
|
| 1327 |
|
|
#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1328 |
|
|
|
| 1329 |
|
|
/******************* Bit definition for BKP_DR16 register *******************/
|
| 1330 |
|
|
#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1331 |
|
|
|
| 1332 |
|
|
/******************* Bit definition for BKP_DR17 register *******************/
|
| 1333 |
|
|
#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1334 |
|
|
|
| 1335 |
|
|
/****************** Bit definition for BKP_DR18 register ********************/
|
| 1336 |
|
|
#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1337 |
|
|
|
| 1338 |
|
|
/******************* Bit definition for BKP_DR19 register *******************/
|
| 1339 |
|
|
#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1340 |
|
|
|
| 1341 |
|
|
/******************* Bit definition for BKP_DR20 register *******************/
|
| 1342 |
|
|
#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1343 |
|
|
|
| 1344 |
|
|
/******************* Bit definition for BKP_DR21 register *******************/
|
| 1345 |
|
|
#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1346 |
|
|
|
| 1347 |
|
|
/******************* Bit definition for BKP_DR22 register *******************/
|
| 1348 |
|
|
#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1349 |
|
|
|
| 1350 |
|
|
/******************* Bit definition for BKP_DR23 register *******************/
|
| 1351 |
|
|
#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1352 |
|
|
|
| 1353 |
|
|
/******************* Bit definition for BKP_DR24 register *******************/
|
| 1354 |
|
|
#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1355 |
|
|
|
| 1356 |
|
|
/******************* Bit definition for BKP_DR25 register *******************/
|
| 1357 |
|
|
#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1358 |
|
|
|
| 1359 |
|
|
/******************* Bit definition for BKP_DR26 register *******************/
|
| 1360 |
|
|
#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1361 |
|
|
|
| 1362 |
|
|
/******************* Bit definition for BKP_DR27 register *******************/
|
| 1363 |
|
|
#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1364 |
|
|
|
| 1365 |
|
|
/******************* Bit definition for BKP_DR28 register *******************/
|
| 1366 |
|
|
#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1367 |
|
|
|
| 1368 |
|
|
/******************* Bit definition for BKP_DR29 register *******************/
|
| 1369 |
|
|
#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1370 |
|
|
|
| 1371 |
|
|
/******************* Bit definition for BKP_DR30 register *******************/
|
| 1372 |
|
|
#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1373 |
|
|
|
| 1374 |
|
|
/******************* Bit definition for BKP_DR31 register *******************/
|
| 1375 |
|
|
#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1376 |
|
|
|
| 1377 |
|
|
/******************* Bit definition for BKP_DR32 register *******************/
|
| 1378 |
|
|
#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1379 |
|
|
|
| 1380 |
|
|
/******************* Bit definition for BKP_DR33 register *******************/
|
| 1381 |
|
|
#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1382 |
|
|
|
| 1383 |
|
|
/******************* Bit definition for BKP_DR34 register *******************/
|
| 1384 |
|
|
#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1385 |
|
|
|
| 1386 |
|
|
/******************* Bit definition for BKP_DR35 register *******************/
|
| 1387 |
|
|
#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1388 |
|
|
|
| 1389 |
|
|
/******************* Bit definition for BKP_DR36 register *******************/
|
| 1390 |
|
|
#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1391 |
|
|
|
| 1392 |
|
|
/******************* Bit definition for BKP_DR37 register *******************/
|
| 1393 |
|
|
#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1394 |
|
|
|
| 1395 |
|
|
/******************* Bit definition for BKP_DR38 register *******************/
|
| 1396 |
|
|
#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1397 |
|
|
|
| 1398 |
|
|
/******************* Bit definition for BKP_DR39 register *******************/
|
| 1399 |
|
|
#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1400 |
|
|
|
| 1401 |
|
|
/******************* Bit definition for BKP_DR40 register *******************/
|
| 1402 |
|
|
#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1403 |
|
|
|
| 1404 |
|
|
/******************* Bit definition for BKP_DR41 register *******************/
|
| 1405 |
|
|
#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1406 |
|
|
|
| 1407 |
|
|
/******************* Bit definition for BKP_DR42 register *******************/
|
| 1408 |
|
|
#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
|
| 1409 |
|
|
|
| 1410 |
|
|
/****************** Bit definition for BKP_RTCCR register *******************/
|
| 1411 |
|
|
#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
|
| 1412 |
|
|
#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
|
| 1413 |
|
|
#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
|
| 1414 |
|
|
#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
|
| 1415 |
|
|
|
| 1416 |
|
|
/******************** Bit definition for BKP_CR register ********************/
|
| 1417 |
|
|
#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
|
| 1418 |
|
|
#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
|
| 1419 |
|
|
|
| 1420 |
|
|
/******************* Bit definition for BKP_CSR register ********************/
|
| 1421 |
|
|
#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
|
| 1422 |
|
|
#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
|
| 1423 |
|
|
#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
|
| 1424 |
|
|
#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
|
| 1425 |
|
|
#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
|
| 1426 |
|
|
|
| 1427 |
|
|
/******************************************************************************/
|
| 1428 |
|
|
/* */
|
| 1429 |
|
|
/* Reset and Clock Control */
|
| 1430 |
|
|
/* */
|
| 1431 |
|
|
/******************************************************************************/
|
| 1432 |
|
|
|
| 1433 |
|
|
/******************** Bit definition for RCC_CR register ********************/
|
| 1434 |
|
|
#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
|
| 1435 |
|
|
#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
|
| 1436 |
|
|
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
|
| 1437 |
|
|
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
|
| 1438 |
|
|
#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
|
| 1439 |
|
|
#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
|
| 1440 |
|
|
#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
|
| 1441 |
|
|
#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
|
| 1442 |
|
|
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
|
| 1443 |
|
|
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
|
| 1444 |
|
|
|
| 1445 |
|
|
#ifdef STM32F10X_CL
|
| 1446 |
|
|
#define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
|
| 1447 |
|
|
#define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
|
| 1448 |
|
|
#define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
|
| 1449 |
|
|
#define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
|
| 1450 |
|
|
#endif /* STM32F10X_CL */
|
| 1451 |
|
|
|
| 1452 |
|
|
/******************* Bit definition for RCC_CFGR register *******************/
|
| 1453 |
|
|
/*!< SW configuration */
|
| 1454 |
|
|
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
|
| 1455 |
|
|
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 1456 |
|
|
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 1457 |
|
|
|
| 1458 |
|
|
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
|
| 1459 |
|
|
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
|
| 1460 |
|
|
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
|
| 1461 |
|
|
|
| 1462 |
|
|
/*!< SWS configuration */
|
| 1463 |
|
|
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
|
| 1464 |
|
|
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
|
| 1465 |
|
|
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
|
| 1466 |
|
|
|
| 1467 |
|
|
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
|
| 1468 |
|
|
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
|
| 1469 |
|
|
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
|
| 1470 |
|
|
|
| 1471 |
|
|
/*!< HPRE configuration */
|
| 1472 |
|
|
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
|
| 1473 |
|
|
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
| 1474 |
|
|
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
| 1475 |
|
|
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
| 1476 |
|
|
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
|
| 1477 |
|
|
|
| 1478 |
|
|
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
|
| 1479 |
|
|
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
|
| 1480 |
|
|
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
|
| 1481 |
|
|
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
|
| 1482 |
|
|
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
|
| 1483 |
|
|
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
|
| 1484 |
|
|
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
|
| 1485 |
|
|
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
|
| 1486 |
|
|
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
|
| 1487 |
|
|
|
| 1488 |
|
|
/*!< PPRE1 configuration */
|
| 1489 |
|
|
#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
|
| 1490 |
|
|
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
| 1491 |
|
|
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
| 1492 |
|
|
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
|
| 1493 |
|
|
|
| 1494 |
|
|
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
| 1495 |
|
|
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
|
| 1496 |
|
|
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
|
| 1497 |
|
|
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
|
| 1498 |
|
|
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
|
| 1499 |
|
|
|
| 1500 |
|
|
/*!< PPRE2 configuration */
|
| 1501 |
|
|
#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
|
| 1502 |
|
|
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
|
| 1503 |
|
|
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
|
| 1504 |
|
|
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
|
| 1505 |
|
|
|
| 1506 |
|
|
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
| 1507 |
|
|
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
|
| 1508 |
|
|
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
|
| 1509 |
|
|
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
|
| 1510 |
|
|
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
|
| 1511 |
|
|
|
| 1512 |
|
|
/*!< ADCPPRE configuration */
|
| 1513 |
|
|
#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
|
| 1514 |
|
|
#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
|
| 1515 |
|
|
#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
|
| 1516 |
|
|
|
| 1517 |
|
|
#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
|
| 1518 |
|
|
#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
|
| 1519 |
|
|
#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
|
| 1520 |
|
|
#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
|
| 1521 |
|
|
|
| 1522 |
|
|
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
|
| 1523 |
|
|
|
| 1524 |
|
|
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
|
| 1525 |
|
|
|
| 1526 |
|
|
/*!< PLLMUL configuration */
|
| 1527 |
|
|
#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
|
| 1528 |
|
|
#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
| 1529 |
|
|
#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
| 1530 |
|
|
#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
|
| 1531 |
|
|
#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
|
| 1532 |
|
|
|
| 1533 |
|
|
#ifdef STM32F10X_CL
|
| 1534 |
|
|
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
|
| 1535 |
|
|
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
|
| 1536 |
|
|
|
| 1537 |
|
|
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
|
| 1538 |
|
|
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
|
| 1539 |
|
|
|
| 1540 |
|
|
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */
|
| 1541 |
|
|
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */
|
| 1542 |
|
|
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */
|
| 1543 |
|
|
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */
|
| 1544 |
|
|
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */
|
| 1545 |
|
|
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */
|
| 1546 |
|
|
#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
|
| 1547 |
|
|
|
| 1548 |
|
|
#define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTF FS prescaler */
|
| 1549 |
|
|
|
| 1550 |
|
|
/*!< MCO configuration */
|
| 1551 |
|
|
#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
|
| 1552 |
|
|
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
| 1553 |
|
|
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
| 1554 |
|
|
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
| 1555 |
|
|
#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
|
| 1556 |
|
|
|
| 1557 |
|
|
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
|
| 1558 |
|
|
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
|
| 1559 |
|
|
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
|
| 1560 |
|
|
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
|
| 1561 |
|
|
#define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
|
| 1562 |
|
|
#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
|
| 1563 |
|
|
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
|
| 1564 |
|
|
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source (for Ethernet) */
|
| 1565 |
|
|
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source (for Ethernet) */
|
| 1566 |
|
|
#else
|
| 1567 |
|
|
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
|
| 1568 |
|
|
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
|
| 1569 |
|
|
|
| 1570 |
|
|
#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
|
| 1571 |
|
|
#define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
|
| 1572 |
|
|
|
| 1573 |
|
|
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
|
| 1574 |
|
|
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
|
| 1575 |
|
|
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
|
| 1576 |
|
|
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
|
| 1577 |
|
|
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
|
| 1578 |
|
|
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
|
| 1579 |
|
|
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
|
| 1580 |
|
|
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
|
| 1581 |
|
|
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
|
| 1582 |
|
|
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
|
| 1583 |
|
|
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
|
| 1584 |
|
|
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
|
| 1585 |
|
|
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
|
| 1586 |
|
|
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
|
| 1587 |
|
|
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
|
| 1588 |
|
|
#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
|
| 1589 |
|
|
|
| 1590 |
|
|
/*!< MCO configuration */
|
| 1591 |
|
|
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
|
| 1592 |
|
|
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
| 1593 |
|
|
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
| 1594 |
|
|
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
| 1595 |
|
|
|
| 1596 |
|
|
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
|
| 1597 |
|
|
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
|
| 1598 |
|
|
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
|
| 1599 |
|
|
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
|
| 1600 |
|
|
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
|
| 1601 |
|
|
#endif /* STM32F10X_CL */
|
| 1602 |
|
|
|
| 1603 |
|
|
/*!<****************** Bit definition for RCC_CIR register ********************/
|
| 1604 |
|
|
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
| 1605 |
|
|
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
|
| 1606 |
|
|
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
|
| 1607 |
|
|
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
|
| 1608 |
|
|
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
|
| 1609 |
|
|
#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
|
| 1610 |
|
|
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
|
| 1611 |
|
|
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
|
| 1612 |
|
|
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
|
| 1613 |
|
|
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
|
| 1614 |
|
|
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
|
| 1615 |
|
|
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
|
| 1616 |
|
|
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
|
| 1617 |
|
|
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
|
| 1618 |
|
|
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
|
| 1619 |
|
|
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
|
| 1620 |
|
|
#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
|
| 1621 |
|
|
|
| 1622 |
|
|
#ifdef STM32F10X_CL
|
| 1623 |
|
|
#define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */
|
| 1624 |
|
|
#define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */
|
| 1625 |
|
|
#define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */
|
| 1626 |
|
|
#define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */
|
| 1627 |
|
|
#define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */
|
| 1628 |
|
|
#define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */
|
| 1629 |
|
|
#endif /* STM32F10X_CL */
|
| 1630 |
|
|
|
| 1631 |
|
|
/***************** Bit definition for RCC_APB2RSTR register *****************/
|
| 1632 |
|
|
#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */
|
| 1633 |
|
|
#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */
|
| 1634 |
|
|
#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */
|
| 1635 |
|
|
#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */
|
| 1636 |
|
|
#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */
|
| 1637 |
|
|
#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */
|
| 1638 |
|
|
#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */
|
| 1639 |
|
|
#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */
|
| 1640 |
|
|
#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */
|
| 1641 |
|
|
#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */
|
| 1642 |
|
|
|
| 1643 |
|
|
#ifndef STM32F10X_LD
|
| 1644 |
|
|
#define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */
|
| 1645 |
|
|
#endif /* STM32F10X_HD */
|
| 1646 |
|
|
|
| 1647 |
|
|
#ifdef STM32F10X_HD
|
| 1648 |
|
|
#define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */
|
| 1649 |
|
|
#define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */
|
| 1650 |
|
|
#define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */
|
| 1651 |
|
|
#define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */
|
| 1652 |
|
|
#endif /* STM32F10X_HD */
|
| 1653 |
|
|
|
| 1654 |
|
|
/***************** Bit definition for RCC_APB1RSTR register *****************/
|
| 1655 |
|
|
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
|
| 1656 |
|
|
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
|
| 1657 |
|
|
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
|
| 1658 |
|
|
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
|
| 1659 |
|
|
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
|
| 1660 |
|
|
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
|
| 1661 |
|
|
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
|
| 1662 |
|
|
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
|
| 1663 |
|
|
|
| 1664 |
|
|
#ifndef STM32F10X_LD
|
| 1665 |
|
|
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
|
| 1666 |
|
|
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
|
| 1667 |
|
|
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
|
| 1668 |
|
|
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
|
| 1669 |
|
|
#endif /* STM32F10X_HD */
|
| 1670 |
|
|
|
| 1671 |
|
|
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
|
| 1672 |
|
|
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
|
| 1673 |
|
|
#endif
|
| 1674 |
|
|
|
| 1675 |
|
|
#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
|
| 1676 |
|
|
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
|
| 1677 |
|
|
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
|
| 1678 |
|
|
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
|
| 1679 |
|
|
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
|
| 1680 |
|
|
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
|
| 1681 |
|
|
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
|
| 1682 |
|
|
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
|
| 1683 |
|
|
#endif
|
| 1684 |
|
|
|
| 1685 |
|
|
#ifdef STM32F10X_CL
|
| 1686 |
|
|
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */
|
| 1687 |
|
|
#endif /* STM32F10X_CL */
|
| 1688 |
|
|
|
| 1689 |
|
|
/****************** Bit definition for RCC_AHBENR register ******************/
|
| 1690 |
|
|
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
|
| 1691 |
|
|
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
|
| 1692 |
|
|
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
|
| 1693 |
|
|
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
|
| 1694 |
|
|
|
| 1695 |
|
|
#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
|
| 1696 |
|
|
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
|
| 1697 |
|
|
#endif
|
| 1698 |
|
|
|
| 1699 |
|
|
#ifdef STM32F10X_HD
|
| 1700 |
|
|
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
|
| 1701 |
|
|
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
|
| 1702 |
|
|
#endif /* STM32F10X_HD */
|
| 1703 |
|
|
|
| 1704 |
|
|
#ifdef STM32F10X_CL
|
| 1705 |
|
|
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
|
| 1706 |
|
|
#define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */
|
| 1707 |
|
|
#define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */
|
| 1708 |
|
|
#define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */
|
| 1709 |
|
|
#endif /* STM32F10X_CL */
|
| 1710 |
|
|
|
| 1711 |
|
|
/****************** Bit definition for RCC_APB2ENR register *****************/
|
| 1712 |
|
|
#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */
|
| 1713 |
|
|
#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */
|
| 1714 |
|
|
#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */
|
| 1715 |
|
|
#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */
|
| 1716 |
|
|
#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */
|
| 1717 |
|
|
#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */
|
| 1718 |
|
|
#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */
|
| 1719 |
|
|
#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */
|
| 1720 |
|
|
#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */
|
| 1721 |
|
|
#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */
|
| 1722 |
|
|
|
| 1723 |
|
|
#ifndef STM32F10X_LD
|
| 1724 |
|
|
#define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */
|
| 1725 |
|
|
#endif /* STM32F10X_HD */
|
| 1726 |
|
|
|
| 1727 |
|
|
#ifdef STM32F10X_HD
|
| 1728 |
|
|
#define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */
|
| 1729 |
|
|
#define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */
|
| 1730 |
|
|
#define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */
|
| 1731 |
|
|
#define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */
|
| 1732 |
|
|
#endif /* STM32F10X_HD */
|
| 1733 |
|
|
|
| 1734 |
|
|
/***************** Bit definition for RCC_APB1ENR register ******************/
|
| 1735 |
|
|
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
|
| 1736 |
|
|
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
|
| 1737 |
|
|
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
|
| 1738 |
|
|
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
|
| 1739 |
|
|
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
|
| 1740 |
|
|
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
|
| 1741 |
|
|
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
|
| 1742 |
|
|
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
|
| 1743 |
|
|
|
| 1744 |
|
|
#ifndef STM32F10X_LD
|
| 1745 |
|
|
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
|
| 1746 |
|
|
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
|
| 1747 |
|
|
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
|
| 1748 |
|
|
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
|
| 1749 |
|
|
#endif /* STM32F10X_HD */
|
| 1750 |
|
|
|
| 1751 |
|
|
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
|
| 1752 |
|
|
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
|
| 1753 |
|
|
#endif
|
| 1754 |
|
|
|
| 1755 |
|
|
#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
|
| 1756 |
|
|
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
|
| 1757 |
|
|
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
|
| 1758 |
|
|
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
|
| 1759 |
|
|
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
|
| 1760 |
|
|
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
|
| 1761 |
|
|
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
|
| 1762 |
|
|
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
|
| 1763 |
|
|
#endif
|
| 1764 |
|
|
|
| 1765 |
|
|
#ifdef STM32F10X_CL
|
| 1766 |
|
|
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */
|
| 1767 |
|
|
#endif /* STM32F10X_CL */
|
| 1768 |
|
|
|
| 1769 |
|
|
/******************* Bit definition for RCC_BDCR register *******************/
|
| 1770 |
|
|
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
|
| 1771 |
|
|
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
|
| 1772 |
|
|
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
|
| 1773 |
|
|
|
| 1774 |
|
|
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
|
| 1775 |
|
|
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
| 1776 |
|
|
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
| 1777 |
|
|
|
| 1778 |
|
|
/*!< RTC congiguration */
|
| 1779 |
|
|
#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
|
| 1780 |
|
|
#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
|
| 1781 |
|
|
#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
|
| 1782 |
|
|
#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
|
| 1783 |
|
|
|
| 1784 |
|
|
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
|
| 1785 |
|
|
#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
|
| 1786 |
|
|
|
| 1787 |
|
|
/******************* Bit definition for RCC_CSR register ********************/
|
| 1788 |
|
|
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
|
| 1789 |
|
|
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
|
| 1790 |
|
|
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
|
| 1791 |
|
|
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
|
| 1792 |
|
|
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
|
| 1793 |
|
|
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
|
| 1794 |
|
|
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
|
| 1795 |
|
|
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
|
| 1796 |
|
|
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
|
| 1797 |
|
|
|
| 1798 |
|
|
#ifdef STM32F10X_CL
|
| 1799 |
|
|
/******************* Bit definition for RCC_AHBRSTR register ****************/
|
| 1800 |
|
|
#define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */
|
| 1801 |
|
|
#define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */
|
| 1802 |
|
|
|
| 1803 |
|
|
/******************* Bit definition for RCC_CFGR2 register ******************/
|
| 1804 |
|
|
/*!< PREDIV1 configuration */
|
| 1805 |
|
|
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
|
| 1806 |
|
|
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 1807 |
|
|
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 1808 |
|
|
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 1809 |
|
|
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 1810 |
|
|
|
| 1811 |
|
|
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
|
| 1812 |
|
|
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
|
| 1813 |
|
|
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
|
| 1814 |
|
|
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
|
| 1815 |
|
|
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
|
| 1816 |
|
|
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
|
| 1817 |
|
|
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
|
| 1818 |
|
|
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
|
| 1819 |
|
|
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
|
| 1820 |
|
|
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
|
| 1821 |
|
|
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
|
| 1822 |
|
|
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
|
| 1823 |
|
|
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
|
| 1824 |
|
|
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
|
| 1825 |
|
|
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
|
| 1826 |
|
|
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
|
| 1827 |
|
|
|
| 1828 |
|
|
/*!< PREDIV2 configuration */
|
| 1829 |
|
|
#define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */
|
| 1830 |
|
|
#define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
| 1831 |
|
|
#define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
| 1832 |
|
|
#define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
| 1833 |
|
|
#define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */
|
| 1834 |
|
|
|
| 1835 |
|
|
#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
|
| 1836 |
|
|
#define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */
|
| 1837 |
|
|
#define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */
|
| 1838 |
|
|
#define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */
|
| 1839 |
|
|
#define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */
|
| 1840 |
|
|
#define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */
|
| 1841 |
|
|
#define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */
|
| 1842 |
|
|
#define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */
|
| 1843 |
|
|
#define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */
|
| 1844 |
|
|
#define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */
|
| 1845 |
|
|
#define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */
|
| 1846 |
|
|
#define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */
|
| 1847 |
|
|
#define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */
|
| 1848 |
|
|
#define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */
|
| 1849 |
|
|
#define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */
|
| 1850 |
|
|
#define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */
|
| 1851 |
|
|
|
| 1852 |
|
|
/*!< PLL2MUL configuration */
|
| 1853 |
|
|
#define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */
|
| 1854 |
|
|
#define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
| 1855 |
|
|
#define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
| 1856 |
|
|
#define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
|
| 1857 |
|
|
#define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
|
| 1858 |
|
|
|
| 1859 |
|
|
#define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */
|
| 1860 |
|
|
#define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */
|
| 1861 |
|
|
#define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */
|
| 1862 |
|
|
#define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */
|
| 1863 |
|
|
#define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */
|
| 1864 |
|
|
#define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */
|
| 1865 |
|
|
#define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */
|
| 1866 |
|
|
#define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */
|
| 1867 |
|
|
#define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */
|
| 1868 |
|
|
|
| 1869 |
|
|
/*!< PLL3MUL configuration */
|
| 1870 |
|
|
#define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */
|
| 1871 |
|
|
#define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
|
| 1872 |
|
|
#define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
|
| 1873 |
|
|
#define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
|
| 1874 |
|
|
#define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */
|
| 1875 |
|
|
|
| 1876 |
|
|
#define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */
|
| 1877 |
|
|
#define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */
|
| 1878 |
|
|
#define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */
|
| 1879 |
|
|
#define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */
|
| 1880 |
|
|
#define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */
|
| 1881 |
|
|
#define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */
|
| 1882 |
|
|
#define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */
|
| 1883 |
|
|
#define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */
|
| 1884 |
|
|
#define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */
|
| 1885 |
|
|
|
| 1886 |
|
|
#define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */
|
| 1887 |
|
|
#define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */
|
| 1888 |
|
|
#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
|
| 1889 |
|
|
#define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */
|
| 1890 |
|
|
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
|
| 1891 |
|
|
#endif /* STM32F10X_CL */
|
| 1892 |
|
|
|
| 1893 |
|
|
/******************************************************************************/
|
| 1894 |
|
|
/* */
|
| 1895 |
|
|
/* General Purpose and Alternate Function I/O */
|
| 1896 |
|
|
/* */
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| 1897 |
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/******************************************************************************/
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| 1898 |
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| 1899 |
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/******************* Bit definition for GPIO_CRL register *******************/
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| 1900 |
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#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
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| 1901 |
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| 1902 |
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#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
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| 1903 |
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#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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| 1904 |
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#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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| 1905 |
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| 1906 |
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#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
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| 1907 |
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#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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| 1908 |
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#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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| 1909 |
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| 1910 |
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#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
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| 1911 |
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#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
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| 1912 |
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#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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| 1913 |
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| 1914 |
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#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
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| 1915 |
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#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
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| 1916 |
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#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
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| 1917 |
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| 1918 |
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#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
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| 1919 |
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#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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| 1920 |
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#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
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| 1921 |
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| 1922 |
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#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
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| 1923 |
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#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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| 1924 |
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#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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| 1925 |
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| 1926 |
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#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
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| 1927 |
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#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
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| 1928 |
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#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
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| 1929 |
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| 1930 |
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#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
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| 1931 |
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#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
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| 1932 |
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#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
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| 1933 |
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| 1934 |
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#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
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| 1935 |
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| 1936 |
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#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
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| 1937 |
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#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
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| 1938 |
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#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
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| 1939 |
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| 1940 |
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#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
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| 1941 |
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#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
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| 1942 |
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#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
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| 1943 |
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| 1944 |
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#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
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| 1945 |
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#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
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| 1946 |
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#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
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| 1947 |
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| 1948 |
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#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
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| 1949 |
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#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
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| 1950 |
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#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
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| 1951 |
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| 1952 |
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#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
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| 1953 |
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#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
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| 1954 |
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#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
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| 1955 |
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| 1956 |
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#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
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| 1957 |
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#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
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| 1958 |
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#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
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| 1959 |
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| 1960 |
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#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
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| 1961 |
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#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
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| 1962 |
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#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
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| 1963 |
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| 1964 |
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#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
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| 1965 |
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#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
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| 1966 |
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#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
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| 1967 |
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| 1968 |
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/******************* Bit definition for GPIO_CRH register *******************/
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| 1969 |
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#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
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| 1970 |
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| 1971 |
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#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
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| 1972 |
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#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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| 1973 |
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#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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| 1974 |
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| 1975 |
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#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
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| 1976 |
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#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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| 1977 |
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#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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| 1978 |
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| 1979 |
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#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
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| 1980 |
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#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
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| 1981 |
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#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
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| 1982 |
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| 1983 |
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#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
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| 1984 |
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#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
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| 1985 |
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#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
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| 1986 |
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| 1987 |
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#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
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| 1988 |
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#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
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| 1989 |
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#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
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| 1990 |
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| 1991 |
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#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
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| 1992 |
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#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
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| 1993 |
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#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
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| 1994 |
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| 1995 |
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#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
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| 1996 |
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#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
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| 1997 |
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#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
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| 1998 |
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| 1999 |
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#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
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| 2000 |
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#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
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| 2001 |
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#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
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| 2002 |
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| 2003 |
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#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
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| 2004 |
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| 2005 |
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#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
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| 2006 |
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#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
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| 2007 |
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#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
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| 2008 |
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| 2009 |
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#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
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| 2010 |
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#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
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| 2011 |
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#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
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| 2012 |
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| 2013 |
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#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
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| 2014 |
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#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
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| 2015 |
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#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
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| 2016 |
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| 2017 |
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#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
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| 2018 |
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#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
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| 2019 |
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#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
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| 2020 |
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| 2021 |
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#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
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| 2022 |
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#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
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| 2023 |
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#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
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| 2024 |
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| 2025 |
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#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
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| 2026 |
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#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
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| 2027 |
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#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
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| 2028 |
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| 2029 |
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#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
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| 2030 |
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#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
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| 2031 |
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#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
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| 2032 |
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| 2033 |
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#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
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| 2034 |
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#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
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| 2035 |
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#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
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| 2036 |
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| 2037 |
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/*!<****************** Bit definition for GPIO_IDR register *******************/
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| 2038 |
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#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
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| 2039 |
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#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
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| 2040 |
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#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
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| 2041 |
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#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
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| 2042 |
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#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
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| 2043 |
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#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
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| 2044 |
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#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
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| 2045 |
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#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
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| 2046 |
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#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
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| 2047 |
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#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
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| 2048 |
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#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
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| 2049 |
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#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
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| 2050 |
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#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
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| 2051 |
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#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
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| 2052 |
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#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
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| 2053 |
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#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
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| 2054 |
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| 2055 |
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/******************* Bit definition for GPIO_ODR register *******************/
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| 2056 |
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#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
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| 2057 |
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#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
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| 2058 |
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#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
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| 2059 |
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#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
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| 2060 |
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#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
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| 2061 |
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#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
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| 2062 |
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#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
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| 2063 |
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#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
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| 2064 |
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#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
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| 2065 |
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#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
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| 2066 |
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#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
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| 2067 |
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#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
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| 2068 |
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#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
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| 2069 |
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#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
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| 2070 |
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#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
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| 2071 |
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#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
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| 2072 |
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| 2073 |
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/****************** Bit definition for GPIO_BSRR register *******************/
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| 2074 |
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#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
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| 2075 |
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#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
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| 2076 |
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#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
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| 2077 |
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#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
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| 2078 |
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#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
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| 2079 |
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#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
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| 2080 |
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#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
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| 2081 |
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#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
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| 2082 |
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#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
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| 2083 |
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#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
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| 2084 |
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#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
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| 2085 |
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#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
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| 2086 |
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#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
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| 2087 |
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#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
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| 2088 |
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#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
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| 2089 |
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#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
|
| 2090 |
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|
| 2091 |
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#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
|
| 2092 |
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#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
|
| 2093 |
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#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
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| 2094 |
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#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
|
| 2095 |
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#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
|
| 2096 |
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#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
|
| 2097 |
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#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
|
| 2098 |
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#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
|
| 2099 |
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#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
|
| 2100 |
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#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
|
| 2101 |
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#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
|
| 2102 |
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#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
|
| 2103 |
|
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#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
|
| 2104 |
|
|
#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
|
| 2105 |
|
|
#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
|
| 2106 |
|
|
#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
|
| 2107 |
|
|
|
| 2108 |
|
|
/******************* Bit definition for GPIO_BRR register *******************/
|
| 2109 |
|
|
#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
|
| 2110 |
|
|
#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
|
| 2111 |
|
|
#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
|
| 2112 |
|
|
#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
|
| 2113 |
|
|
#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
|
| 2114 |
|
|
#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
|
| 2115 |
|
|
#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
|
| 2116 |
|
|
#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
|
| 2117 |
|
|
#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
|
| 2118 |
|
|
#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
|
| 2119 |
|
|
#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
|
| 2120 |
|
|
#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
|
| 2121 |
|
|
#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
|
| 2122 |
|
|
#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
|
| 2123 |
|
|
#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
|
| 2124 |
|
|
#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
|
| 2125 |
|
|
|
| 2126 |
|
|
/****************** Bit definition for GPIO_LCKR register *******************/
|
| 2127 |
|
|
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
|
| 2128 |
|
|
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
|
| 2129 |
|
|
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
|
| 2130 |
|
|
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
|
| 2131 |
|
|
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
|
| 2132 |
|
|
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
|
| 2133 |
|
|
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
|
| 2134 |
|
|
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
|
| 2135 |
|
|
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
|
| 2136 |
|
|
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
|
| 2137 |
|
|
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
|
| 2138 |
|
|
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
|
| 2139 |
|
|
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
|
| 2140 |
|
|
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
|
| 2141 |
|
|
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
|
| 2142 |
|
|
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
|
| 2143 |
|
|
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
|
| 2144 |
|
|
|
| 2145 |
|
|
/*----------------------------------------------------------------------------*/
|
| 2146 |
|
|
|
| 2147 |
|
|
/****************** Bit definition for AFIO_EVCR register *******************/
|
| 2148 |
|
|
#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
|
| 2149 |
|
|
#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
|
| 2150 |
|
|
#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
|
| 2151 |
|
|
#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
|
| 2152 |
|
|
#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
|
| 2153 |
|
|
|
| 2154 |
|
|
/*!< PIN configuration */
|
| 2155 |
|
|
#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
|
| 2156 |
|
|
#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
|
| 2157 |
|
|
#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
|
| 2158 |
|
|
#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
|
| 2159 |
|
|
#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
|
| 2160 |
|
|
#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
|
| 2161 |
|
|
#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
|
| 2162 |
|
|
#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
|
| 2163 |
|
|
#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
|
| 2164 |
|
|
#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
|
| 2165 |
|
|
#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
|
| 2166 |
|
|
#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
|
| 2167 |
|
|
#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
|
| 2168 |
|
|
#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
|
| 2169 |
|
|
#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
|
| 2170 |
|
|
#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
|
| 2171 |
|
|
|
| 2172 |
|
|
#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
|
| 2173 |
|
|
#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
|
| 2174 |
|
|
#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
|
| 2175 |
|
|
#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
|
| 2176 |
|
|
|
| 2177 |
|
|
/*!< PORT configuration */
|
| 2178 |
|
|
#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
|
| 2179 |
|
|
#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
|
| 2180 |
|
|
#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
|
| 2181 |
|
|
#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
|
| 2182 |
|
|
#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
|
| 2183 |
|
|
|
| 2184 |
|
|
#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
|
| 2185 |
|
|
|
| 2186 |
|
|
/****************** Bit definition for AFIO_MAPR register *******************/
|
| 2187 |
|
|
#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
|
| 2188 |
|
|
#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
|
| 2189 |
|
|
#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
|
| 2190 |
|
|
#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
|
| 2191 |
|
|
|
| 2192 |
|
|
#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
|
| 2193 |
|
|
#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
| 2194 |
|
|
#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
| 2195 |
|
|
|
| 2196 |
|
|
/* USART3_REMAP configuration */
|
| 2197 |
|
|
#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
|
| 2198 |
|
|
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
|
| 2199 |
|
|
#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
|
| 2200 |
|
|
|
| 2201 |
|
|
#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
|
| 2202 |
|
|
#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
|
| 2203 |
|
|
#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
|
| 2204 |
|
|
|
| 2205 |
|
|
/*!< TIM1_REMAP configuration */
|
| 2206 |
|
|
#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
|
| 2207 |
|
|
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
|
| 2208 |
|
|
#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
|
| 2209 |
|
|
|
| 2210 |
|
|
#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
|
| 2211 |
|
|
#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
| 2212 |
|
|
#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
| 2213 |
|
|
|
| 2214 |
|
|
/*!< TIM2_REMAP configuration */
|
| 2215 |
|
|
#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
|
| 2216 |
|
|
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
|
| 2217 |
|
|
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
|
| 2218 |
|
|
#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
|
| 2219 |
|
|
|
| 2220 |
|
|
#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
|
| 2221 |
|
|
#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 2222 |
|
|
#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 2223 |
|
|
|
| 2224 |
|
|
/*!< TIM3_REMAP configuration */
|
| 2225 |
|
|
#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
|
| 2226 |
|
|
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
|
| 2227 |
|
|
#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
|
| 2228 |
|
|
|
| 2229 |
|
|
#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
|
| 2230 |
|
|
|
| 2231 |
|
|
#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
|
| 2232 |
|
|
#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
|
| 2233 |
|
|
#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
|
| 2234 |
|
|
|
| 2235 |
|
|
/*!< CAN_REMAP configuration */
|
| 2236 |
|
|
#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
|
| 2237 |
|
|
#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
|
| 2238 |
|
|
#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
|
| 2239 |
|
|
|
| 2240 |
|
|
#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
|
| 2241 |
|
|
#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
|
| 2242 |
|
|
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
|
| 2243 |
|
|
#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
|
| 2244 |
|
|
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
|
| 2245 |
|
|
#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
|
| 2246 |
|
|
|
| 2247 |
|
|
#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
|
| 2248 |
|
|
#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
| 2249 |
|
|
#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
| 2250 |
|
|
#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
| 2251 |
|
|
|
| 2252 |
|
|
/*!< SWJ_CFG configuration */
|
| 2253 |
|
|
#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
|
| 2254 |
|
|
#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
|
| 2255 |
|
|
#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
|
| 2256 |
|
|
#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
|
| 2257 |
|
|
|
| 2258 |
|
|
/***************** Bit definition for AFIO_EXTICR1 register *****************/
|
| 2259 |
|
|
#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
|
| 2260 |
|
|
#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
|
| 2261 |
|
|
#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
|
| 2262 |
|
|
#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
|
| 2263 |
|
|
|
| 2264 |
|
|
/*!< EXTI0 configuration */
|
| 2265 |
|
|
#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
|
| 2266 |
|
|
#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
|
| 2267 |
|
|
#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
|
| 2268 |
|
|
#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
|
| 2269 |
|
|
#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
|
| 2270 |
|
|
#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
|
| 2271 |
|
|
#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
|
| 2272 |
|
|
|
| 2273 |
|
|
/*!< EXTI1 configuration */
|
| 2274 |
|
|
#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
|
| 2275 |
|
|
#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
|
| 2276 |
|
|
#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
|
| 2277 |
|
|
#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
|
| 2278 |
|
|
#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
|
| 2279 |
|
|
#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
|
| 2280 |
|
|
#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
|
| 2281 |
|
|
|
| 2282 |
|
|
/*!< EXTI2 configuration */
|
| 2283 |
|
|
#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
|
| 2284 |
|
|
#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
|
| 2285 |
|
|
#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
|
| 2286 |
|
|
#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
|
| 2287 |
|
|
#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
|
| 2288 |
|
|
#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
|
| 2289 |
|
|
#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
|
| 2290 |
|
|
|
| 2291 |
|
|
/*!< EXTI3 configuration */
|
| 2292 |
|
|
#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
|
| 2293 |
|
|
#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
|
| 2294 |
|
|
#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
|
| 2295 |
|
|
#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
|
| 2296 |
|
|
#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
|
| 2297 |
|
|
#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
|
| 2298 |
|
|
#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
|
| 2299 |
|
|
|
| 2300 |
|
|
/***************** Bit definition for AFIO_EXTICR2 register *****************/
|
| 2301 |
|
|
#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
|
| 2302 |
|
|
#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
|
| 2303 |
|
|
#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
|
| 2304 |
|
|
#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
|
| 2305 |
|
|
|
| 2306 |
|
|
/*!< EXTI4 configuration */
|
| 2307 |
|
|
#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
|
| 2308 |
|
|
#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
|
| 2309 |
|
|
#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
|
| 2310 |
|
|
#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
|
| 2311 |
|
|
#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
|
| 2312 |
|
|
#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
|
| 2313 |
|
|
#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
|
| 2314 |
|
|
|
| 2315 |
|
|
/* EXTI5 configuration */
|
| 2316 |
|
|
#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
|
| 2317 |
|
|
#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
|
| 2318 |
|
|
#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
|
| 2319 |
|
|
#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
|
| 2320 |
|
|
#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
|
| 2321 |
|
|
#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
|
| 2322 |
|
|
#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
|
| 2323 |
|
|
|
| 2324 |
|
|
/*!< EXTI6 configuration */
|
| 2325 |
|
|
#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
|
| 2326 |
|
|
#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
|
| 2327 |
|
|
#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
|
| 2328 |
|
|
#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
|
| 2329 |
|
|
#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
|
| 2330 |
|
|
#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
|
| 2331 |
|
|
#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
|
| 2332 |
|
|
|
| 2333 |
|
|
/*!< EXTI7 configuration */
|
| 2334 |
|
|
#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
|
| 2335 |
|
|
#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
|
| 2336 |
|
|
#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
|
| 2337 |
|
|
#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
|
| 2338 |
|
|
#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
|
| 2339 |
|
|
#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
|
| 2340 |
|
|
#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
|
| 2341 |
|
|
|
| 2342 |
|
|
/***************** Bit definition for AFIO_EXTICR3 register *****************/
|
| 2343 |
|
|
#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
|
| 2344 |
|
|
#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
|
| 2345 |
|
|
#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
|
| 2346 |
|
|
#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
|
| 2347 |
|
|
|
| 2348 |
|
|
/*!< EXTI8 configuration */
|
| 2349 |
|
|
#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
|
| 2350 |
|
|
#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
|
| 2351 |
|
|
#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
|
| 2352 |
|
|
#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
|
| 2353 |
|
|
#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
|
| 2354 |
|
|
#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
|
| 2355 |
|
|
#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
|
| 2356 |
|
|
|
| 2357 |
|
|
/*!< EXTI9 configuration */
|
| 2358 |
|
|
#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
|
| 2359 |
|
|
#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
|
| 2360 |
|
|
#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
|
| 2361 |
|
|
#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
|
| 2362 |
|
|
#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
|
| 2363 |
|
|
#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
|
| 2364 |
|
|
#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
|
| 2365 |
|
|
|
| 2366 |
|
|
/*!< EXTI10 configuration */
|
| 2367 |
|
|
#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
|
| 2368 |
|
|
#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
|
| 2369 |
|
|
#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
|
| 2370 |
|
|
#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
|
| 2371 |
|
|
#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
|
| 2372 |
|
|
#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
|
| 2373 |
|
|
#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
|
| 2374 |
|
|
|
| 2375 |
|
|
/*!< EXTI11 configuration */
|
| 2376 |
|
|
#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
|
| 2377 |
|
|
#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
|
| 2378 |
|
|
#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
|
| 2379 |
|
|
#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
|
| 2380 |
|
|
#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
|
| 2381 |
|
|
#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
|
| 2382 |
|
|
#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
|
| 2383 |
|
|
|
| 2384 |
|
|
/***************** Bit definition for AFIO_EXTICR4 register *****************/
|
| 2385 |
|
|
#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
|
| 2386 |
|
|
#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
|
| 2387 |
|
|
#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
|
| 2388 |
|
|
#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
|
| 2389 |
|
|
|
| 2390 |
|
|
/* EXTI12 configuration */
|
| 2391 |
|
|
#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
|
| 2392 |
|
|
#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
|
| 2393 |
|
|
#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
|
| 2394 |
|
|
#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
|
| 2395 |
|
|
#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
|
| 2396 |
|
|
#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
|
| 2397 |
|
|
#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
|
| 2398 |
|
|
|
| 2399 |
|
|
/* EXTI13 configuration */
|
| 2400 |
|
|
#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
|
| 2401 |
|
|
#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
|
| 2402 |
|
|
#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
|
| 2403 |
|
|
#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
|
| 2404 |
|
|
#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
|
| 2405 |
|
|
#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
|
| 2406 |
|
|
#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
|
| 2407 |
|
|
|
| 2408 |
|
|
/*!< EXTI14 configuration */
|
| 2409 |
|
|
#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
|
| 2410 |
|
|
#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
|
| 2411 |
|
|
#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
|
| 2412 |
|
|
#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
|
| 2413 |
|
|
#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
|
| 2414 |
|
|
#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
|
| 2415 |
|
|
#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
|
| 2416 |
|
|
|
| 2417 |
|
|
/*!< EXTI15 configuration */
|
| 2418 |
|
|
#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
|
| 2419 |
|
|
#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
|
| 2420 |
|
|
#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
|
| 2421 |
|
|
#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
|
| 2422 |
|
|
#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
|
| 2423 |
|
|
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
|
| 2424 |
|
|
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
|
| 2425 |
|
|
|
| 2426 |
|
|
/******************************************************************************/
|
| 2427 |
|
|
/* */
|
| 2428 |
|
|
/* SystemTick */
|
| 2429 |
|
|
/* */
|
| 2430 |
|
|
/******************************************************************************/
|
| 2431 |
|
|
|
| 2432 |
|
|
/***************** Bit definition for SysTick_CTRL register *****************/
|
| 2433 |
|
|
#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
|
| 2434 |
|
|
#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
|
| 2435 |
|
|
#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
|
| 2436 |
|
|
#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
|
| 2437 |
|
|
|
| 2438 |
|
|
/***************** Bit definition for SysTick_LOAD register *****************/
|
| 2439 |
|
|
#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
|
| 2440 |
|
|
|
| 2441 |
|
|
/***************** Bit definition for SysTick_VAL register ******************/
|
| 2442 |
|
|
#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
|
| 2443 |
|
|
|
| 2444 |
|
|
/***************** Bit definition for SysTick_CALIB register ****************/
|
| 2445 |
|
|
#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
|
| 2446 |
|
|
#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
|
| 2447 |
|
|
#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
|
| 2448 |
|
|
|
| 2449 |
|
|
/******************************************************************************/
|
| 2450 |
|
|
/* */
|
| 2451 |
|
|
/* Nested Vectored Interrupt Controller */
|
| 2452 |
|
|
/* */
|
| 2453 |
|
|
/******************************************************************************/
|
| 2454 |
|
|
|
| 2455 |
|
|
/****************** Bit definition for NVIC_ISER register *******************/
|
| 2456 |
|
|
#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
|
| 2457 |
|
|
#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 2458 |
|
|
#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 2459 |
|
|
#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 2460 |
|
|
#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 2461 |
|
|
#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 2462 |
|
|
#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 2463 |
|
|
#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 2464 |
|
|
#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 2465 |
|
|
#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 2466 |
|
|
#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 2467 |
|
|
#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 2468 |
|
|
#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 2469 |
|
|
#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 2470 |
|
|
#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 2471 |
|
|
#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 2472 |
|
|
#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 2473 |
|
|
#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 2474 |
|
|
#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 2475 |
|
|
#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 2476 |
|
|
#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 2477 |
|
|
#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 2478 |
|
|
#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 2479 |
|
|
#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 2480 |
|
|
#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 2481 |
|
|
#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 2482 |
|
|
#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 2483 |
|
|
#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 2484 |
|
|
#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 2485 |
|
|
#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 2486 |
|
|
#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 2487 |
|
|
#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 2488 |
|
|
#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 2489 |
|
|
|
| 2490 |
|
|
/****************** Bit definition for NVIC_ICER register *******************/
|
| 2491 |
|
|
#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
|
| 2492 |
|
|
#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 2493 |
|
|
#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 2494 |
|
|
#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 2495 |
|
|
#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 2496 |
|
|
#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 2497 |
|
|
#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 2498 |
|
|
#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 2499 |
|
|
#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 2500 |
|
|
#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 2501 |
|
|
#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 2502 |
|
|
#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 2503 |
|
|
#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 2504 |
|
|
#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 2505 |
|
|
#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 2506 |
|
|
#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 2507 |
|
|
#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 2508 |
|
|
#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 2509 |
|
|
#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 2510 |
|
|
#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 2511 |
|
|
#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 2512 |
|
|
#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 2513 |
|
|
#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 2514 |
|
|
#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 2515 |
|
|
#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 2516 |
|
|
#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 2517 |
|
|
#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 2518 |
|
|
#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 2519 |
|
|
#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 2520 |
|
|
#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 2521 |
|
|
#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 2522 |
|
|
#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 2523 |
|
|
#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 2524 |
|
|
|
| 2525 |
|
|
/****************** Bit definition for NVIC_ISPR register *******************/
|
| 2526 |
|
|
#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
|
| 2527 |
|
|
#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 2528 |
|
|
#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 2529 |
|
|
#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 2530 |
|
|
#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 2531 |
|
|
#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 2532 |
|
|
#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 2533 |
|
|
#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 2534 |
|
|
#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 2535 |
|
|
#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 2536 |
|
|
#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 2537 |
|
|
#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 2538 |
|
|
#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 2539 |
|
|
#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 2540 |
|
|
#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 2541 |
|
|
#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 2542 |
|
|
#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 2543 |
|
|
#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 2544 |
|
|
#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 2545 |
|
|
#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 2546 |
|
|
#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 2547 |
|
|
#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 2548 |
|
|
#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 2549 |
|
|
#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 2550 |
|
|
#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 2551 |
|
|
#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 2552 |
|
|
#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 2553 |
|
|
#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 2554 |
|
|
#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 2555 |
|
|
#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 2556 |
|
|
#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 2557 |
|
|
#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 2558 |
|
|
#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 2559 |
|
|
|
| 2560 |
|
|
/****************** Bit definition for NVIC_ICPR register *******************/
|
| 2561 |
|
|
#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
|
| 2562 |
|
|
#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 2563 |
|
|
#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 2564 |
|
|
#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 2565 |
|
|
#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 2566 |
|
|
#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 2567 |
|
|
#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 2568 |
|
|
#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 2569 |
|
|
#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 2570 |
|
|
#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 2571 |
|
|
#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 2572 |
|
|
#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 2573 |
|
|
#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 2574 |
|
|
#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 2575 |
|
|
#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 2576 |
|
|
#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 2577 |
|
|
#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 2578 |
|
|
#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 2579 |
|
|
#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 2580 |
|
|
#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 2581 |
|
|
#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 2582 |
|
|
#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 2583 |
|
|
#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 2584 |
|
|
#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 2585 |
|
|
#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 2586 |
|
|
#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 2587 |
|
|
#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 2588 |
|
|
#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 2589 |
|
|
#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 2590 |
|
|
#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 2591 |
|
|
#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 2592 |
|
|
#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 2593 |
|
|
#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 2594 |
|
|
|
| 2595 |
|
|
/****************** Bit definition for NVIC_IABR register *******************/
|
| 2596 |
|
|
#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
|
| 2597 |
|
|
#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 2598 |
|
|
#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 2599 |
|
|
#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 2600 |
|
|
#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 2601 |
|
|
#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 2602 |
|
|
#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 2603 |
|
|
#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 2604 |
|
|
#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 2605 |
|
|
#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 2606 |
|
|
#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 2607 |
|
|
#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 2608 |
|
|
#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 2609 |
|
|
#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 2610 |
|
|
#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 2611 |
|
|
#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 2612 |
|
|
#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 2613 |
|
|
#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 2614 |
|
|
#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 2615 |
|
|
#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 2616 |
|
|
#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 2617 |
|
|
#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 2618 |
|
|
#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 2619 |
|
|
#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 2620 |
|
|
#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 2621 |
|
|
#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 2622 |
|
|
#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 2623 |
|
|
#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 2624 |
|
|
#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 2625 |
|
|
#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 2626 |
|
|
#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 2627 |
|
|
#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 2628 |
|
|
#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 2629 |
|
|
|
| 2630 |
|
|
/****************** Bit definition for NVIC_PRI0 register *******************/
|
| 2631 |
|
|
#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
|
| 2632 |
|
|
#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
|
| 2633 |
|
|
#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
|
| 2634 |
|
|
#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
|
| 2635 |
|
|
|
| 2636 |
|
|
/****************** Bit definition for NVIC_PRI1 register *******************/
|
| 2637 |
|
|
#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
|
| 2638 |
|
|
#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
|
| 2639 |
|
|
#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
|
| 2640 |
|
|
#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
|
| 2641 |
|
|
|
| 2642 |
|
|
/****************** Bit definition for NVIC_PRI2 register *******************/
|
| 2643 |
|
|
#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
|
| 2644 |
|
|
#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
|
| 2645 |
|
|
#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
|
| 2646 |
|
|
#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
|
| 2647 |
|
|
|
| 2648 |
|
|
/****************** Bit definition for NVIC_PRI3 register *******************/
|
| 2649 |
|
|
#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
|
| 2650 |
|
|
#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
|
| 2651 |
|
|
#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
|
| 2652 |
|
|
#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
|
| 2653 |
|
|
|
| 2654 |
|
|
/****************** Bit definition for NVIC_PRI4 register *******************/
|
| 2655 |
|
|
#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
|
| 2656 |
|
|
#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
|
| 2657 |
|
|
#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
|
| 2658 |
|
|
#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
|
| 2659 |
|
|
|
| 2660 |
|
|
/****************** Bit definition for NVIC_PRI5 register *******************/
|
| 2661 |
|
|
#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
|
| 2662 |
|
|
#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
|
| 2663 |
|
|
#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
|
| 2664 |
|
|
#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
|
| 2665 |
|
|
|
| 2666 |
|
|
/****************** Bit definition for NVIC_PRI6 register *******************/
|
| 2667 |
|
|
#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
|
| 2668 |
|
|
#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
|
| 2669 |
|
|
#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
|
| 2670 |
|
|
#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
|
| 2671 |
|
|
|
| 2672 |
|
|
/****************** Bit definition for NVIC_PRI7 register *******************/
|
| 2673 |
|
|
#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
|
| 2674 |
|
|
#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
|
| 2675 |
|
|
#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
|
| 2676 |
|
|
#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
|
| 2677 |
|
|
|
| 2678 |
|
|
/****************** Bit definition for SCB_CPUID register *******************/
|
| 2679 |
|
|
#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
|
| 2680 |
|
|
#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
|
| 2681 |
|
|
#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
|
| 2682 |
|
|
#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
|
| 2683 |
|
|
#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
|
| 2684 |
|
|
|
| 2685 |
|
|
/******************* Bit definition for SCB_ICSR register *******************/
|
| 2686 |
|
|
#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
|
| 2687 |
|
|
#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
|
| 2688 |
|
|
#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
|
| 2689 |
|
|
#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
|
| 2690 |
|
|
#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
|
| 2691 |
|
|
#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
|
| 2692 |
|
|
#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
|
| 2693 |
|
|
#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
|
| 2694 |
|
|
#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
|
| 2695 |
|
|
#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
|
| 2696 |
|
|
|
| 2697 |
|
|
/******************* Bit definition for SCB_VTOR register *******************/
|
| 2698 |
|
|
#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
|
| 2699 |
|
|
#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
|
| 2700 |
|
|
|
| 2701 |
|
|
/*!<***************** Bit definition for SCB_AIRCR register *******************/
|
| 2702 |
|
|
#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
|
| 2703 |
|
|
#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
|
| 2704 |
|
|
#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
|
| 2705 |
|
|
|
| 2706 |
|
|
#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
|
| 2707 |
|
|
#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
| 2708 |
|
|
#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
| 2709 |
|
|
#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
|
| 2710 |
|
|
|
| 2711 |
|
|
/* prority group configuration */
|
| 2712 |
|
|
#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
|
| 2713 |
|
|
#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
|
| 2714 |
|
|
#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
|
| 2715 |
|
|
#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
|
| 2716 |
|
|
#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
|
| 2717 |
|
|
#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
|
| 2718 |
|
|
#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
|
| 2719 |
|
|
#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
|
| 2720 |
|
|
|
| 2721 |
|
|
#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
|
| 2722 |
|
|
#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
|
| 2723 |
|
|
|
| 2724 |
|
|
/******************* Bit definition for SCB_SCR register ********************/
|
| 2725 |
|
|
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
|
| 2726 |
|
|
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
|
| 2727 |
|
|
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
|
| 2728 |
|
|
|
| 2729 |
|
|
/******************** Bit definition for SCB_CCR register *******************/
|
| 2730 |
|
|
#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
|
| 2731 |
|
|
#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
|
| 2732 |
|
|
#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
|
| 2733 |
|
|
#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
|
| 2734 |
|
|
#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
|
| 2735 |
|
|
#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
|
| 2736 |
|
|
|
| 2737 |
|
|
/******************* Bit definition for SCB_SHPR register ********************/
|
| 2738 |
|
|
#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
|
| 2739 |
|
|
#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
|
| 2740 |
|
|
#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
|
| 2741 |
|
|
#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
|
| 2742 |
|
|
|
| 2743 |
|
|
/****************** Bit definition for SCB_SHCSR register *******************/
|
| 2744 |
|
|
#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
|
| 2745 |
|
|
#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
|
| 2746 |
|
|
#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
|
| 2747 |
|
|
#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
|
| 2748 |
|
|
#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
|
| 2749 |
|
|
#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
|
| 2750 |
|
|
#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
|
| 2751 |
|
|
#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
|
| 2752 |
|
|
#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
|
| 2753 |
|
|
#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
|
| 2754 |
|
|
#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
|
| 2755 |
|
|
#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
|
| 2756 |
|
|
#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
|
| 2757 |
|
|
#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
|
| 2758 |
|
|
|
| 2759 |
|
|
/******************* Bit definition for SCB_CFSR register *******************/
|
| 2760 |
|
|
/*!< MFSR */
|
| 2761 |
|
|
#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
|
| 2762 |
|
|
#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
|
| 2763 |
|
|
#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
|
| 2764 |
|
|
#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
|
| 2765 |
|
|
#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
|
| 2766 |
|
|
/*!< BFSR */
|
| 2767 |
|
|
#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
|
| 2768 |
|
|
#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
|
| 2769 |
|
|
#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
|
| 2770 |
|
|
#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
|
| 2771 |
|
|
#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
|
| 2772 |
|
|
#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
|
| 2773 |
|
|
/*!< UFSR */
|
| 2774 |
|
|
#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
|
| 2775 |
|
|
#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
|
| 2776 |
|
|
#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
|
| 2777 |
|
|
#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
|
| 2778 |
|
|
#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
|
| 2779 |
|
|
#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
|
| 2780 |
|
|
|
| 2781 |
|
|
/******************* Bit definition for SCB_HFSR register *******************/
|
| 2782 |
|
|
#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
|
| 2783 |
|
|
#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
|
| 2784 |
|
|
#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
|
| 2785 |
|
|
|
| 2786 |
|
|
/******************* Bit definition for SCB_DFSR register *******************/
|
| 2787 |
|
|
#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
|
| 2788 |
|
|
#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
|
| 2789 |
|
|
#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
|
| 2790 |
|
|
#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
|
| 2791 |
|
|
#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
|
| 2792 |
|
|
|
| 2793 |
|
|
/******************* Bit definition for SCB_MMFAR register ******************/
|
| 2794 |
|
|
#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
|
| 2795 |
|
|
|
| 2796 |
|
|
/******************* Bit definition for SCB_BFAR register *******************/
|
| 2797 |
|
|
#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
|
| 2798 |
|
|
|
| 2799 |
|
|
/******************* Bit definition for SCB_afsr register *******************/
|
| 2800 |
|
|
#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
|
| 2801 |
|
|
|
| 2802 |
|
|
/******************************************************************************/
|
| 2803 |
|
|
/* */
|
| 2804 |
|
|
/* External Interrupt/Event Controller */
|
| 2805 |
|
|
/* */
|
| 2806 |
|
|
/******************************************************************************/
|
| 2807 |
|
|
|
| 2808 |
|
|
/******************* Bit definition for EXTI_IMR register *******************/
|
| 2809 |
|
|
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
| 2810 |
|
|
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
| 2811 |
|
|
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
| 2812 |
|
|
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
|
| 2813 |
|
|
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
|
| 2814 |
|
|
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
|
| 2815 |
|
|
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
|
| 2816 |
|
|
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
|
| 2817 |
|
|
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
|
| 2818 |
|
|
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
|
| 2819 |
|
|
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
|
| 2820 |
|
|
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
|
| 2821 |
|
|
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
|
| 2822 |
|
|
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
|
| 2823 |
|
|
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
|
| 2824 |
|
|
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
|
| 2825 |
|
|
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
|
| 2826 |
|
|
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
|
| 2827 |
|
|
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
|
| 2828 |
|
|
|
| 2829 |
|
|
/******************* Bit definition for EXTI_EMR register *******************/
|
| 2830 |
|
|
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
| 2831 |
|
|
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
| 2832 |
|
|
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
| 2833 |
|
|
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
|
| 2834 |
|
|
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
|
| 2835 |
|
|
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
|
| 2836 |
|
|
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
|
| 2837 |
|
|
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
|
| 2838 |
|
|
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
|
| 2839 |
|
|
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
|
| 2840 |
|
|
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
|
| 2841 |
|
|
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
|
| 2842 |
|
|
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
|
| 2843 |
|
|
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
|
| 2844 |
|
|
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
|
| 2845 |
|
|
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
|
| 2846 |
|
|
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
|
| 2847 |
|
|
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
|
| 2848 |
|
|
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
|
| 2849 |
|
|
|
| 2850 |
|
|
/****************** Bit definition for EXTI_RTSR register *******************/
|
| 2851 |
|
|
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
| 2852 |
|
|
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
| 2853 |
|
|
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
| 2854 |
|
|
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
|
| 2855 |
|
|
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
|
| 2856 |
|
|
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
|
| 2857 |
|
|
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
|
| 2858 |
|
|
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
|
| 2859 |
|
|
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
|
| 2860 |
|
|
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
|
| 2861 |
|
|
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
|
| 2862 |
|
|
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
|
| 2863 |
|
|
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
|
| 2864 |
|
|
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
|
| 2865 |
|
|
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
|
| 2866 |
|
|
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
|
| 2867 |
|
|
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
|
| 2868 |
|
|
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
|
| 2869 |
|
|
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
|
| 2870 |
|
|
|
| 2871 |
|
|
/****************** Bit definition for EXTI_FTSR register *******************/
|
| 2872 |
|
|
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
| 2873 |
|
|
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
| 2874 |
|
|
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
| 2875 |
|
|
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
|
| 2876 |
|
|
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
|
| 2877 |
|
|
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
|
| 2878 |
|
|
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
|
| 2879 |
|
|
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
|
| 2880 |
|
|
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
|
| 2881 |
|
|
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
|
| 2882 |
|
|
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
|
| 2883 |
|
|
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
|
| 2884 |
|
|
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
|
| 2885 |
|
|
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
|
| 2886 |
|
|
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
|
| 2887 |
|
|
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
|
| 2888 |
|
|
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
|
| 2889 |
|
|
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
|
| 2890 |
|
|
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
|
| 2891 |
|
|
|
| 2892 |
|
|
/****************** Bit definition for EXTI_SWIER register ******************/
|
| 2893 |
|
|
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
| 2894 |
|
|
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
| 2895 |
|
|
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
| 2896 |
|
|
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
|
| 2897 |
|
|
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
|
| 2898 |
|
|
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
|
| 2899 |
|
|
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
|
| 2900 |
|
|
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
|
| 2901 |
|
|
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
|
| 2902 |
|
|
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
|
| 2903 |
|
|
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
|
| 2904 |
|
|
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
|
| 2905 |
|
|
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
|
| 2906 |
|
|
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
|
| 2907 |
|
|
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
|
| 2908 |
|
|
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
|
| 2909 |
|
|
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
|
| 2910 |
|
|
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
|
| 2911 |
|
|
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
|
| 2912 |
|
|
|
| 2913 |
|
|
/******************* Bit definition for EXTI_PR register ********************/
|
| 2914 |
|
|
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
|
| 2915 |
|
|
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
|
| 2916 |
|
|
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
|
| 2917 |
|
|
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
|
| 2918 |
|
|
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
|
| 2919 |
|
|
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
|
| 2920 |
|
|
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
|
| 2921 |
|
|
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
|
| 2922 |
|
|
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
|
| 2923 |
|
|
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
|
| 2924 |
|
|
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
|
| 2925 |
|
|
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
|
| 2926 |
|
|
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
|
| 2927 |
|
|
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
|
| 2928 |
|
|
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
|
| 2929 |
|
|
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
|
| 2930 |
|
|
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
|
| 2931 |
|
|
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
|
| 2932 |
|
|
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Trigger request occurred on the external interrupt line 18 */
|
| 2933 |
|
|
|
| 2934 |
|
|
/******************************************************************************/
|
| 2935 |
|
|
/* */
|
| 2936 |
|
|
/* DMA Controller */
|
| 2937 |
|
|
/* */
|
| 2938 |
|
|
/******************************************************************************/
|
| 2939 |
|
|
|
| 2940 |
|
|
/******************* Bit definition for DMA_ISR register ********************/
|
| 2941 |
|
|
#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
|
| 2942 |
|
|
#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
|
| 2943 |
|
|
#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
|
| 2944 |
|
|
#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
|
| 2945 |
|
|
#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
|
| 2946 |
|
|
#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
|
| 2947 |
|
|
#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
|
| 2948 |
|
|
#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
|
| 2949 |
|
|
#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
|
| 2950 |
|
|
#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
|
| 2951 |
|
|
#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
|
| 2952 |
|
|
#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
|
| 2953 |
|
|
#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
|
| 2954 |
|
|
#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
|
| 2955 |
|
|
#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
|
| 2956 |
|
|
#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
|
| 2957 |
|
|
#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
|
| 2958 |
|
|
#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
|
| 2959 |
|
|
#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
|
| 2960 |
|
|
#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
|
| 2961 |
|
|
#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
|
| 2962 |
|
|
#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
|
| 2963 |
|
|
#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
|
| 2964 |
|
|
#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
|
| 2965 |
|
|
#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
|
| 2966 |
|
|
#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
|
| 2967 |
|
|
#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
|
| 2968 |
|
|
#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
|
| 2969 |
|
|
|
| 2970 |
|
|
/******************* Bit definition for DMA_IFCR register *******************/
|
| 2971 |
|
|
#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
|
| 2972 |
|
|
#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
|
| 2973 |
|
|
#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
|
| 2974 |
|
|
#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
|
| 2975 |
|
|
#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
|
| 2976 |
|
|
#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
|
| 2977 |
|
|
#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
|
| 2978 |
|
|
#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
|
| 2979 |
|
|
#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
|
| 2980 |
|
|
#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
|
| 2981 |
|
|
#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
|
| 2982 |
|
|
#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
|
| 2983 |
|
|
#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
|
| 2984 |
|
|
#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
|
| 2985 |
|
|
#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
|
| 2986 |
|
|
#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
|
| 2987 |
|
|
#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
|
| 2988 |
|
|
#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
|
| 2989 |
|
|
#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
|
| 2990 |
|
|
#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
|
| 2991 |
|
|
#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
|
| 2992 |
|
|
#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
|
| 2993 |
|
|
#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
|
| 2994 |
|
|
#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
|
| 2995 |
|
|
#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
|
| 2996 |
|
|
#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
|
| 2997 |
|
|
#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
|
| 2998 |
|
|
#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
|
| 2999 |
|
|
|
| 3000 |
|
|
/******************* Bit definition for DMA_CCR1 register *******************/
|
| 3001 |
|
|
#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
|
| 3002 |
|
|
#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
|
| 3003 |
|
|
#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 3004 |
|
|
#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 3005 |
|
|
#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 3006 |
|
|
#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 3007 |
|
|
#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 3008 |
|
|
#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 3009 |
|
|
|
| 3010 |
|
|
#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 3011 |
|
|
#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 3012 |
|
|
#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 3013 |
|
|
|
| 3014 |
|
|
#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 3015 |
|
|
#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 3016 |
|
|
#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 3017 |
|
|
|
| 3018 |
|
|
#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
|
| 3019 |
|
|
#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 3020 |
|
|
#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 3021 |
|
|
|
| 3022 |
|
|
#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
|
| 3023 |
|
|
|
| 3024 |
|
|
/******************* Bit definition for DMA_CCR2 register *******************/
|
| 3025 |
|
|
#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
|
| 3026 |
|
|
#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
|
| 3027 |
|
|
#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 3028 |
|
|
#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 3029 |
|
|
#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 3030 |
|
|
#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 3031 |
|
|
#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 3032 |
|
|
#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 3033 |
|
|
|
| 3034 |
|
|
#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 3035 |
|
|
#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 3036 |
|
|
#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 3037 |
|
|
|
| 3038 |
|
|
#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 3039 |
|
|
#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 3040 |
|
|
#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 3041 |
|
|
|
| 3042 |
|
|
#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
|
| 3043 |
|
|
#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 3044 |
|
|
#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 3045 |
|
|
|
| 3046 |
|
|
#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
|
| 3047 |
|
|
|
| 3048 |
|
|
/******************* Bit definition for DMA_CCR3 register *******************/
|
| 3049 |
|
|
#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
|
| 3050 |
|
|
#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
|
| 3051 |
|
|
#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 3052 |
|
|
#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 3053 |
|
|
#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 3054 |
|
|
#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 3055 |
|
|
#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 3056 |
|
|
#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 3057 |
|
|
|
| 3058 |
|
|
#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 3059 |
|
|
#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 3060 |
|
|
#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 3061 |
|
|
|
| 3062 |
|
|
#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 3063 |
|
|
#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 3064 |
|
|
#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 3065 |
|
|
|
| 3066 |
|
|
#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
|
| 3067 |
|
|
#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 3068 |
|
|
#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 3069 |
|
|
|
| 3070 |
|
|
#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
|
| 3071 |
|
|
|
| 3072 |
|
|
/*!<****************** Bit definition for DMA_CCR4 register *******************/
|
| 3073 |
|
|
#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */
|
| 3074 |
|
|
#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
|
| 3075 |
|
|
#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
|
| 3076 |
|
|
#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
|
| 3077 |
|
|
#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
|
| 3078 |
|
|
#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */
|
| 3079 |
|
|
#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
|
| 3080 |
|
|
#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
|
| 3081 |
|
|
|
| 3082 |
|
|
#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
|
| 3083 |
|
|
#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3084 |
|
|
#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3085 |
|
|
|
| 3086 |
|
|
#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
|
| 3087 |
|
|
#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 3088 |
|
|
#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 3089 |
|
|
|
| 3090 |
|
|
#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
|
| 3091 |
|
|
#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3092 |
|
|
#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3093 |
|
|
|
| 3094 |
|
|
#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
|
| 3095 |
|
|
|
| 3096 |
|
|
/****************** Bit definition for DMA_CCR5 register *******************/
|
| 3097 |
|
|
#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */
|
| 3098 |
|
|
#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
|
| 3099 |
|
|
#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
|
| 3100 |
|
|
#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
|
| 3101 |
|
|
#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
|
| 3102 |
|
|
#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */
|
| 3103 |
|
|
#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
|
| 3104 |
|
|
#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
|
| 3105 |
|
|
|
| 3106 |
|
|
#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
|
| 3107 |
|
|
#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3108 |
|
|
#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3109 |
|
|
|
| 3110 |
|
|
#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
|
| 3111 |
|
|
#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 3112 |
|
|
#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 3113 |
|
|
|
| 3114 |
|
|
#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
|
| 3115 |
|
|
#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3116 |
|
|
#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3117 |
|
|
|
| 3118 |
|
|
#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
|
| 3119 |
|
|
|
| 3120 |
|
|
/******************* Bit definition for DMA_CCR6 register *******************/
|
| 3121 |
|
|
#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */
|
| 3122 |
|
|
#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
|
| 3123 |
|
|
#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
|
| 3124 |
|
|
#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
|
| 3125 |
|
|
#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
|
| 3126 |
|
|
#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */
|
| 3127 |
|
|
#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
|
| 3128 |
|
|
#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
|
| 3129 |
|
|
|
| 3130 |
|
|
#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
|
| 3131 |
|
|
#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3132 |
|
|
#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3133 |
|
|
|
| 3134 |
|
|
#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
|
| 3135 |
|
|
#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 3136 |
|
|
#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 3137 |
|
|
|
| 3138 |
|
|
#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
|
| 3139 |
|
|
#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3140 |
|
|
#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3141 |
|
|
|
| 3142 |
|
|
#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
|
| 3143 |
|
|
|
| 3144 |
|
|
/******************* Bit definition for DMA_CCR7 register *******************/
|
| 3145 |
|
|
#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */
|
| 3146 |
|
|
#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
|
| 3147 |
|
|
#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
|
| 3148 |
|
|
#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
|
| 3149 |
|
|
#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
|
| 3150 |
|
|
#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */
|
| 3151 |
|
|
#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
|
| 3152 |
|
|
#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
|
| 3153 |
|
|
|
| 3154 |
|
|
#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
|
| 3155 |
|
|
#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3156 |
|
|
#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3157 |
|
|
|
| 3158 |
|
|
#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
|
| 3159 |
|
|
#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 3160 |
|
|
#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 3161 |
|
|
|
| 3162 |
|
|
#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
|
| 3163 |
|
|
#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3164 |
|
|
#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3165 |
|
|
|
| 3166 |
|
|
#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
|
| 3167 |
|
|
|
| 3168 |
|
|
/****************** Bit definition for DMA_CNDTR1 register ******************/
|
| 3169 |
|
|
#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
|
| 3170 |
|
|
|
| 3171 |
|
|
/****************** Bit definition for DMA_CNDTR2 register ******************/
|
| 3172 |
|
|
#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
|
| 3173 |
|
|
|
| 3174 |
|
|
/****************** Bit definition for DMA_CNDTR3 register ******************/
|
| 3175 |
|
|
#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
|
| 3176 |
|
|
|
| 3177 |
|
|
/****************** Bit definition for DMA_CNDTR4 register ******************/
|
| 3178 |
|
|
#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
|
| 3179 |
|
|
|
| 3180 |
|
|
/****************** Bit definition for DMA_CNDTR5 register ******************/
|
| 3181 |
|
|
#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
|
| 3182 |
|
|
|
| 3183 |
|
|
/****************** Bit definition for DMA_CNDTR6 register ******************/
|
| 3184 |
|
|
#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
|
| 3185 |
|
|
|
| 3186 |
|
|
/****************** Bit definition for DMA_CNDTR7 register ******************/
|
| 3187 |
|
|
#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
|
| 3188 |
|
|
|
| 3189 |
|
|
/****************** Bit definition for DMA_CPAR1 register *******************/
|
| 3190 |
|
|
#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
|
| 3191 |
|
|
|
| 3192 |
|
|
/****************** Bit definition for DMA_CPAR2 register *******************/
|
| 3193 |
|
|
#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
|
| 3194 |
|
|
|
| 3195 |
|
|
/****************** Bit definition for DMA_CPAR3 register *******************/
|
| 3196 |
|
|
#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
|
| 3197 |
|
|
|
| 3198 |
|
|
|
| 3199 |
|
|
/****************** Bit definition for DMA_CPAR4 register *******************/
|
| 3200 |
|
|
#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
|
| 3201 |
|
|
|
| 3202 |
|
|
/****************** Bit definition for DMA_CPAR5 register *******************/
|
| 3203 |
|
|
#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
|
| 3204 |
|
|
|
| 3205 |
|
|
/****************** Bit definition for DMA_CPAR6 register *******************/
|
| 3206 |
|
|
#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
|
| 3207 |
|
|
|
| 3208 |
|
|
|
| 3209 |
|
|
/****************** Bit definition for DMA_CPAR7 register *******************/
|
| 3210 |
|
|
#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
|
| 3211 |
|
|
|
| 3212 |
|
|
/****************** Bit definition for DMA_CMAR1 register *******************/
|
| 3213 |
|
|
#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
|
| 3214 |
|
|
|
| 3215 |
|
|
/****************** Bit definition for DMA_CMAR2 register *******************/
|
| 3216 |
|
|
#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
|
| 3217 |
|
|
|
| 3218 |
|
|
/****************** Bit definition for DMA_CMAR3 register *******************/
|
| 3219 |
|
|
#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
|
| 3220 |
|
|
|
| 3221 |
|
|
|
| 3222 |
|
|
/****************** Bit definition for DMA_CMAR4 register *******************/
|
| 3223 |
|
|
#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
|
| 3224 |
|
|
|
| 3225 |
|
|
/****************** Bit definition for DMA_CMAR5 register *******************/
|
| 3226 |
|
|
#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
|
| 3227 |
|
|
|
| 3228 |
|
|
/****************** Bit definition for DMA_CMAR6 register *******************/
|
| 3229 |
|
|
#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
|
| 3230 |
|
|
|
| 3231 |
|
|
/****************** Bit definition for DMA_CMAR7 register *******************/
|
| 3232 |
|
|
#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
|
| 3233 |
|
|
|
| 3234 |
|
|
/******************************************************************************/
|
| 3235 |
|
|
/* */
|
| 3236 |
|
|
/* Analog to Digital Converter */
|
| 3237 |
|
|
/* */
|
| 3238 |
|
|
/******************************************************************************/
|
| 3239 |
|
|
|
| 3240 |
|
|
/******************** Bit definition for ADC_SR register ********************/
|
| 3241 |
|
|
#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
|
| 3242 |
|
|
#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
|
| 3243 |
|
|
#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
|
| 3244 |
|
|
#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
|
| 3245 |
|
|
#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
|
| 3246 |
|
|
|
| 3247 |
|
|
/******************* Bit definition for ADC_CR1 register ********************/
|
| 3248 |
|
|
#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
|
| 3249 |
|
|
#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 3250 |
|
|
#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 3251 |
|
|
#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 3252 |
|
|
#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 3253 |
|
|
#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 3254 |
|
|
|
| 3255 |
|
|
#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
|
| 3256 |
|
|
#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
|
| 3257 |
|
|
#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
|
| 3258 |
|
|
#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
|
| 3259 |
|
|
#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
|
| 3260 |
|
|
#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
|
| 3261 |
|
|
#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
|
| 3262 |
|
|
#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
|
| 3263 |
|
|
|
| 3264 |
|
|
#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
|
| 3265 |
|
|
#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
| 3266 |
|
|
#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
| 3267 |
|
|
#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
| 3268 |
|
|
|
| 3269 |
|
|
#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */
|
| 3270 |
|
|
#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 3271 |
|
|
#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 3272 |
|
|
#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 3273 |
|
|
#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 3274 |
|
|
|
| 3275 |
|
|
#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
|
| 3276 |
|
|
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
|
| 3277 |
|
|
|
| 3278 |
|
|
|
| 3279 |
|
|
/******************* Bit definition for ADC_CR2 register ********************/
|
| 3280 |
|
|
#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
|
| 3281 |
|
|
#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
|
| 3282 |
|
|
#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */
|
| 3283 |
|
|
#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */
|
| 3284 |
|
|
#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
|
| 3285 |
|
|
#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
|
| 3286 |
|
|
|
| 3287 |
|
|
#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */
|
| 3288 |
|
|
#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
| 3289 |
|
|
#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
| 3290 |
|
|
#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
| 3291 |
|
|
|
| 3292 |
|
|
#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */
|
| 3293 |
|
|
|
| 3294 |
|
|
#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */
|
| 3295 |
|
|
#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
| 3296 |
|
|
#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
| 3297 |
|
|
#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
| 3298 |
|
|
|
| 3299 |
|
|
#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */
|
| 3300 |
|
|
#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */
|
| 3301 |
|
|
#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */
|
| 3302 |
|
|
#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
|
| 3303 |
|
|
|
| 3304 |
|
|
/****************** Bit definition for ADC_SMPR1 register *******************/
|
| 3305 |
|
|
#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
|
| 3306 |
|
|
#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 3307 |
|
|
#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 3308 |
|
|
#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 3309 |
|
|
|
| 3310 |
|
|
#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
|
| 3311 |
|
|
#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
| 3312 |
|
|
#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
| 3313 |
|
|
#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
| 3314 |
|
|
|
| 3315 |
|
|
#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
|
| 3316 |
|
|
#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
| 3317 |
|
|
#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
| 3318 |
|
|
#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
| 3319 |
|
|
|
| 3320 |
|
|
#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
|
| 3321 |
|
|
#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
| 3322 |
|
|
#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
| 3323 |
|
|
#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
| 3324 |
|
|
|
| 3325 |
|
|
#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
|
| 3326 |
|
|
#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
| 3327 |
|
|
#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
| 3328 |
|
|
#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
| 3329 |
|
|
|
| 3330 |
|
|
#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
|
| 3331 |
|
|
#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
| 3332 |
|
|
#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
| 3333 |
|
|
#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
| 3334 |
|
|
|
| 3335 |
|
|
#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
|
| 3336 |
|
|
#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
| 3337 |
|
|
#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
| 3338 |
|
|
#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
|
| 3339 |
|
|
|
| 3340 |
|
|
#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
|
| 3341 |
|
|
#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
| 3342 |
|
|
#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
| 3343 |
|
|
#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
| 3344 |
|
|
|
| 3345 |
|
|
/****************** Bit definition for ADC_SMPR2 register *******************/
|
| 3346 |
|
|
#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
|
| 3347 |
|
|
#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 3348 |
|
|
#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 3349 |
|
|
#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 3350 |
|
|
|
| 3351 |
|
|
#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
|
| 3352 |
|
|
#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
| 3353 |
|
|
#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
| 3354 |
|
|
#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
| 3355 |
|
|
|
| 3356 |
|
|
#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
|
| 3357 |
|
|
#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
| 3358 |
|
|
#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
| 3359 |
|
|
#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
| 3360 |
|
|
|
| 3361 |
|
|
#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
|
| 3362 |
|
|
#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
| 3363 |
|
|
#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
| 3364 |
|
|
#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
| 3365 |
|
|
|
| 3366 |
|
|
#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
|
| 3367 |
|
|
#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
| 3368 |
|
|
#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
| 3369 |
|
|
#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
| 3370 |
|
|
|
| 3371 |
|
|
#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
|
| 3372 |
|
|
#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
| 3373 |
|
|
#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
| 3374 |
|
|
#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
| 3375 |
|
|
|
| 3376 |
|
|
#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
|
| 3377 |
|
|
#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
| 3378 |
|
|
#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
| 3379 |
|
|
#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
|
| 3380 |
|
|
|
| 3381 |
|
|
#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
|
| 3382 |
|
|
#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
| 3383 |
|
|
#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
| 3384 |
|
|
#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
| 3385 |
|
|
|
| 3386 |
|
|
#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
|
| 3387 |
|
|
#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 3388 |
|
|
#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 3389 |
|
|
#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 3390 |
|
|
|
| 3391 |
|
|
#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
|
| 3392 |
|
|
#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
|
| 3393 |
|
|
#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
|
| 3394 |
|
|
#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
|
| 3395 |
|
|
|
| 3396 |
|
|
/****************** Bit definition for ADC_JOFR1 register *******************/
|
| 3397 |
|
|
#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
|
| 3398 |
|
|
|
| 3399 |
|
|
/****************** Bit definition for ADC_JOFR2 register *******************/
|
| 3400 |
|
|
#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
|
| 3401 |
|
|
|
| 3402 |
|
|
/****************** Bit definition for ADC_JOFR3 register *******************/
|
| 3403 |
|
|
#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
|
| 3404 |
|
|
|
| 3405 |
|
|
/****************** Bit definition for ADC_JOFR4 register *******************/
|
| 3406 |
|
|
#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
|
| 3407 |
|
|
|
| 3408 |
|
|
/******************* Bit definition for ADC_HTR register ********************/
|
| 3409 |
|
|
#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
|
| 3410 |
|
|
|
| 3411 |
|
|
/******************* Bit definition for ADC_LTR register ********************/
|
| 3412 |
|
|
#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
|
| 3413 |
|
|
|
| 3414 |
|
|
/******************* Bit definition for ADC_SQR1 register *******************/
|
| 3415 |
|
|
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
|
| 3416 |
|
|
#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 3417 |
|
|
#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 3418 |
|
|
#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 3419 |
|
|
#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 3420 |
|
|
#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 3421 |
|
|
|
| 3422 |
|
|
#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
|
| 3423 |
|
|
#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
| 3424 |
|
|
#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
| 3425 |
|
|
#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
| 3426 |
|
|
#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
| 3427 |
|
|
#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
| 3428 |
|
|
|
| 3429 |
|
|
#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
|
| 3430 |
|
|
#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 3431 |
|
|
#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 3432 |
|
|
#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 3433 |
|
|
#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 3434 |
|
|
#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 3435 |
|
|
|
| 3436 |
|
|
#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
|
| 3437 |
|
|
#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
| 3438 |
|
|
#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
| 3439 |
|
|
#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
| 3440 |
|
|
#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
| 3441 |
|
|
#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
| 3442 |
|
|
|
| 3443 |
|
|
#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
|
| 3444 |
|
|
#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 3445 |
|
|
#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 3446 |
|
|
#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 3447 |
|
|
#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 3448 |
|
|
|
| 3449 |
|
|
/******************* Bit definition for ADC_SQR2 register *******************/
|
| 3450 |
|
|
#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
|
| 3451 |
|
|
#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 3452 |
|
|
#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 3453 |
|
|
#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 3454 |
|
|
#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 3455 |
|
|
#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 3456 |
|
|
|
| 3457 |
|
|
#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
|
| 3458 |
|
|
#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
| 3459 |
|
|
#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
| 3460 |
|
|
#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
| 3461 |
|
|
#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
| 3462 |
|
|
#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
| 3463 |
|
|
|
| 3464 |
|
|
#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
|
| 3465 |
|
|
#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 3466 |
|
|
#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 3467 |
|
|
#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 3468 |
|
|
#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 3469 |
|
|
#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 3470 |
|
|
|
| 3471 |
|
|
#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
|
| 3472 |
|
|
#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
| 3473 |
|
|
#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
| 3474 |
|
|
#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
| 3475 |
|
|
#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
| 3476 |
|
|
#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
| 3477 |
|
|
|
| 3478 |
|
|
#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
|
| 3479 |
|
|
#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 3480 |
|
|
#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 3481 |
|
|
#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 3482 |
|
|
#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 3483 |
|
|
#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
|
| 3484 |
|
|
|
| 3485 |
|
|
#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
|
| 3486 |
|
|
#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
|
| 3487 |
|
|
#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
|
| 3488 |
|
|
#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
|
| 3489 |
|
|
#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
|
| 3490 |
|
|
#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
|
| 3491 |
|
|
|
| 3492 |
|
|
/******************* Bit definition for ADC_SQR3 register *******************/
|
| 3493 |
|
|
#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
|
| 3494 |
|
|
#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 3495 |
|
|
#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 3496 |
|
|
#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 3497 |
|
|
#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 3498 |
|
|
#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 3499 |
|
|
|
| 3500 |
|
|
#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
|
| 3501 |
|
|
#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
| 3502 |
|
|
#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
| 3503 |
|
|
#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
| 3504 |
|
|
#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
| 3505 |
|
|
#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
| 3506 |
|
|
|
| 3507 |
|
|
#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
|
| 3508 |
|
|
#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 3509 |
|
|
#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 3510 |
|
|
#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 3511 |
|
|
#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 3512 |
|
|
#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 3513 |
|
|
|
| 3514 |
|
|
#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
|
| 3515 |
|
|
#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
| 3516 |
|
|
#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
| 3517 |
|
|
#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
| 3518 |
|
|
#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
| 3519 |
|
|
#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
| 3520 |
|
|
|
| 3521 |
|
|
#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
|
| 3522 |
|
|
#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 3523 |
|
|
#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 3524 |
|
|
#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 3525 |
|
|
#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 3526 |
|
|
#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
|
| 3527 |
|
|
|
| 3528 |
|
|
#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
|
| 3529 |
|
|
#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
|
| 3530 |
|
|
#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
|
| 3531 |
|
|
#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
|
| 3532 |
|
|
#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
|
| 3533 |
|
|
#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
|
| 3534 |
|
|
|
| 3535 |
|
|
/******************* Bit definition for ADC_JSQR register *******************/
|
| 3536 |
|
|
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
|
| 3537 |
|
|
#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 3538 |
|
|
#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 3539 |
|
|
#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 3540 |
|
|
#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 3541 |
|
|
#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 3542 |
|
|
|
| 3543 |
|
|
#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
|
| 3544 |
|
|
#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
| 3545 |
|
|
#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
| 3546 |
|
|
#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
| 3547 |
|
|
#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
| 3548 |
|
|
#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
| 3549 |
|
|
|
| 3550 |
|
|
#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
|
| 3551 |
|
|
#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 3552 |
|
|
#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 3553 |
|
|
#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 3554 |
|
|
#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 3555 |
|
|
#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 3556 |
|
|
|
| 3557 |
|
|
#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
|
| 3558 |
|
|
#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
| 3559 |
|
|
#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
| 3560 |
|
|
#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
| 3561 |
|
|
#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
| 3562 |
|
|
#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
| 3563 |
|
|
|
| 3564 |
|
|
#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
|
| 3565 |
|
|
#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 3566 |
|
|
#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 3567 |
|
|
|
| 3568 |
|
|
/******************* Bit definition for ADC_JDR1 register *******************/
|
| 3569 |
|
|
#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
|
| 3570 |
|
|
|
| 3571 |
|
|
/******************* Bit definition for ADC_JDR2 register *******************/
|
| 3572 |
|
|
#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
|
| 3573 |
|
|
|
| 3574 |
|
|
/******************* Bit definition for ADC_JDR3 register *******************/
|
| 3575 |
|
|
#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
|
| 3576 |
|
|
|
| 3577 |
|
|
/******************* Bit definition for ADC_JDR4 register *******************/
|
| 3578 |
|
|
#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
|
| 3579 |
|
|
|
| 3580 |
|
|
/******************** Bit definition for ADC_DR register ********************/
|
| 3581 |
|
|
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
|
| 3582 |
|
|
#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
|
| 3583 |
|
|
|
| 3584 |
|
|
/******************************************************************************/
|
| 3585 |
|
|
/* */
|
| 3586 |
|
|
/* Digital to Analog Converter */
|
| 3587 |
|
|
/* */
|
| 3588 |
|
|
/******************************************************************************/
|
| 3589 |
|
|
|
| 3590 |
|
|
/******************** Bit definition for DAC_CR register ********************/
|
| 3591 |
|
|
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
|
| 3592 |
|
|
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
|
| 3593 |
|
|
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
|
| 3594 |
|
|
|
| 3595 |
|
|
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
|
| 3596 |
|
|
#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
| 3597 |
|
|
#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
| 3598 |
|
|
#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
| 3599 |
|
|
|
| 3600 |
|
|
#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
|
| 3601 |
|
|
#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
| 3602 |
|
|
#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
| 3603 |
|
|
|
| 3604 |
|
|
#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
|
| 3605 |
|
|
#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 3606 |
|
|
#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 3607 |
|
|
#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 3608 |
|
|
#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 3609 |
|
|
|
| 3610 |
|
|
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
|
| 3611 |
|
|
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
|
| 3612 |
|
|
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
|
| 3613 |
|
|
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
|
| 3614 |
|
|
|
| 3615 |
|
|
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
|
| 3616 |
|
|
#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
|
| 3617 |
|
|
#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
|
| 3618 |
|
|
#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
|
| 3619 |
|
|
|
| 3620 |
|
|
#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
|
| 3621 |
|
|
#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
| 3622 |
|
|
#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
| 3623 |
|
|
|
| 3624 |
|
|
#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
|
| 3625 |
|
|
#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 3626 |
|
|
#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 3627 |
|
|
#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 3628 |
|
|
#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 3629 |
|
|
|
| 3630 |
|
|
#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
|
| 3631 |
|
|
|
| 3632 |
|
|
/***************** Bit definition for DAC_SWTRIGR register ******************/
|
| 3633 |
|
|
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
|
| 3634 |
|
|
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
|
| 3635 |
|
|
|
| 3636 |
|
|
/***************** Bit definition for DAC_DHR12R1 register ******************/
|
| 3637 |
|
|
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
|
| 3638 |
|
|
|
| 3639 |
|
|
/***************** Bit definition for DAC_DHR12L1 register ******************/
|
| 3640 |
|
|
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
|
| 3641 |
|
|
|
| 3642 |
|
|
/****************** Bit definition for DAC_DHR8R1 register ******************/
|
| 3643 |
|
|
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
|
| 3644 |
|
|
|
| 3645 |
|
|
/***************** Bit definition for DAC_DHR12R2 register ******************/
|
| 3646 |
|
|
#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
|
| 3647 |
|
|
|
| 3648 |
|
|
/***************** Bit definition for DAC_DHR12L2 register ******************/
|
| 3649 |
|
|
#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
|
| 3650 |
|
|
|
| 3651 |
|
|
/****************** Bit definition for DAC_DHR8R2 register ******************/
|
| 3652 |
|
|
#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
|
| 3653 |
|
|
|
| 3654 |
|
|
/***************** Bit definition for DAC_DHR12RD register ******************/
|
| 3655 |
|
|
#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
|
| 3656 |
|
|
#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
|
| 3657 |
|
|
|
| 3658 |
|
|
/***************** Bit definition for DAC_DHR12LD register ******************/
|
| 3659 |
|
|
#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
|
| 3660 |
|
|
#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
|
| 3661 |
|
|
|
| 3662 |
|
|
/****************** Bit definition for DAC_DHR8RD register ******************/
|
| 3663 |
|
|
#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
|
| 3664 |
|
|
#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
|
| 3665 |
|
|
|
| 3666 |
|
|
/******************* Bit definition for DAC_DOR1 register *******************/
|
| 3667 |
|
|
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
|
| 3668 |
|
|
|
| 3669 |
|
|
/******************* Bit definition for DAC_DOR2 register *******************/
|
| 3670 |
|
|
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
|
| 3671 |
|
|
|
| 3672 |
|
|
/******************************************************************************/
|
| 3673 |
|
|
/* */
|
| 3674 |
|
|
/* TIM */
|
| 3675 |
|
|
/* */
|
| 3676 |
|
|
/******************************************************************************/
|
| 3677 |
|
|
|
| 3678 |
|
|
/******************* Bit definition for TIM_CR1 register ********************/
|
| 3679 |
|
|
#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
|
| 3680 |
|
|
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
|
| 3681 |
|
|
#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
|
| 3682 |
|
|
#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
|
| 3683 |
|
|
#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
|
| 3684 |
|
|
|
| 3685 |
|
|
#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
|
| 3686 |
|
|
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
|
| 3687 |
|
|
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
|
| 3688 |
|
|
|
| 3689 |
|
|
#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
|
| 3690 |
|
|
|
| 3691 |
|
|
#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
|
| 3692 |
|
|
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3693 |
|
|
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3694 |
|
|
|
| 3695 |
|
|
/******************* Bit definition for TIM_CR2 register ********************/
|
| 3696 |
|
|
#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
|
| 3697 |
|
|
#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
|
| 3698 |
|
|
#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
|
| 3699 |
|
|
|
| 3700 |
|
|
#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
|
| 3701 |
|
|
#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3702 |
|
|
#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3703 |
|
|
#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3704 |
|
|
|
| 3705 |
|
|
#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
|
| 3706 |
|
|
#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
|
| 3707 |
|
|
#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
|
| 3708 |
|
|
#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
|
| 3709 |
|
|
#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
|
| 3710 |
|
|
#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
|
| 3711 |
|
|
#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
|
| 3712 |
|
|
#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
|
| 3713 |
|
|
|
| 3714 |
|
|
/******************* Bit definition for TIM_SMCR register *******************/
|
| 3715 |
|
|
#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
|
| 3716 |
|
|
#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3717 |
|
|
#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3718 |
|
|
#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
|
| 3719 |
|
|
|
| 3720 |
|
|
#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
|
| 3721 |
|
|
#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3722 |
|
|
#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3723 |
|
|
#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3724 |
|
|
|
| 3725 |
|
|
#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
|
| 3726 |
|
|
|
| 3727 |
|
|
#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
|
| 3728 |
|
|
#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3729 |
|
|
#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3730 |
|
|
#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
|
| 3731 |
|
|
#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
|
| 3732 |
|
|
|
| 3733 |
|
|
#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
|
| 3734 |
|
|
#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3735 |
|
|
#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3736 |
|
|
|
| 3737 |
|
|
#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
|
| 3738 |
|
|
#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
|
| 3739 |
|
|
|
| 3740 |
|
|
/******************* Bit definition for TIM_DIER register *******************/
|
| 3741 |
|
|
#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
|
| 3742 |
|
|
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
|
| 3743 |
|
|
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
|
| 3744 |
|
|
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
|
| 3745 |
|
|
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
|
| 3746 |
|
|
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
|
| 3747 |
|
|
#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
|
| 3748 |
|
|
#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
|
| 3749 |
|
|
#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
|
| 3750 |
|
|
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
|
| 3751 |
|
|
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
|
| 3752 |
|
|
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
|
| 3753 |
|
|
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
|
| 3754 |
|
|
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
|
| 3755 |
|
|
#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
|
| 3756 |
|
|
|
| 3757 |
|
|
/******************** Bit definition for TIM_SR register ********************/
|
| 3758 |
|
|
#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
|
| 3759 |
|
|
#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
|
| 3760 |
|
|
#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
|
| 3761 |
|
|
#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
|
| 3762 |
|
|
#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
|
| 3763 |
|
|
#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
|
| 3764 |
|
|
#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
|
| 3765 |
|
|
#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
|
| 3766 |
|
|
#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
|
| 3767 |
|
|
#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
|
| 3768 |
|
|
#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
|
| 3769 |
|
|
#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
|
| 3770 |
|
|
|
| 3771 |
|
|
/******************* Bit definition for TIM_EGR register ********************/
|
| 3772 |
|
|
#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
|
| 3773 |
|
|
#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
|
| 3774 |
|
|
#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
|
| 3775 |
|
|
#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
|
| 3776 |
|
|
#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
|
| 3777 |
|
|
#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
|
| 3778 |
|
|
#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
|
| 3779 |
|
|
#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
|
| 3780 |
|
|
|
| 3781 |
|
|
/****************** Bit definition for TIM_CCMR1 register *******************/
|
| 3782 |
|
|
#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
|
| 3783 |
|
|
#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3784 |
|
|
#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3785 |
|
|
|
| 3786 |
|
|
#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
|
| 3787 |
|
|
#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
|
| 3788 |
|
|
|
| 3789 |
|
|
#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
|
| 3790 |
|
|
#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3791 |
|
|
#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3792 |
|
|
#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3793 |
|
|
|
| 3794 |
|
|
#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
|
| 3795 |
|
|
|
| 3796 |
|
|
#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
|
| 3797 |
|
|
#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3798 |
|
|
#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3799 |
|
|
|
| 3800 |
|
|
#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
|
| 3801 |
|
|
#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
|
| 3802 |
|
|
|
| 3803 |
|
|
#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
|
| 3804 |
|
|
#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3805 |
|
|
#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3806 |
|
|
#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
|
| 3807 |
|
|
|
| 3808 |
|
|
#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
|
| 3809 |
|
|
|
| 3810 |
|
|
/*----------------------------------------------------------------------------*/
|
| 3811 |
|
|
|
| 3812 |
|
|
#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
|
| 3813 |
|
|
#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
|
| 3814 |
|
|
#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
|
| 3815 |
|
|
|
| 3816 |
|
|
#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
|
| 3817 |
|
|
#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3818 |
|
|
#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3819 |
|
|
#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3820 |
|
|
#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
|
| 3821 |
|
|
|
| 3822 |
|
|
#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
|
| 3823 |
|
|
#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 3824 |
|
|
#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 3825 |
|
|
|
| 3826 |
|
|
#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
|
| 3827 |
|
|
#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3828 |
|
|
#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3829 |
|
|
#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
|
| 3830 |
|
|
#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
|
| 3831 |
|
|
|
| 3832 |
|
|
/****************** Bit definition for TIM_CCMR2 register *******************/
|
| 3833 |
|
|
#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
|
| 3834 |
|
|
#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3835 |
|
|
#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3836 |
|
|
|
| 3837 |
|
|
#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
|
| 3838 |
|
|
#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
|
| 3839 |
|
|
|
| 3840 |
|
|
#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
| 3841 |
|
|
#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3842 |
|
|
#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3843 |
|
|
#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3844 |
|
|
|
| 3845 |
|
|
#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
|
| 3846 |
|
|
|
| 3847 |
|
|
#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
|
| 3848 |
|
|
#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3849 |
|
|
#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3850 |
|
|
|
| 3851 |
|
|
#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
|
| 3852 |
|
|
#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
|
| 3853 |
|
|
|
| 3854 |
|
|
#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
| 3855 |
|
|
#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3856 |
|
|
#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3857 |
|
|
#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
|
| 3858 |
|
|
|
| 3859 |
|
|
#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
|
| 3860 |
|
|
|
| 3861 |
|
|
/*----------------------------------------------------------------------------*/
|
| 3862 |
|
|
|
| 3863 |
|
|
#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
|
| 3864 |
|
|
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
|
| 3865 |
|
|
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
|
| 3866 |
|
|
|
| 3867 |
|
|
#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
|
| 3868 |
|
|
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3869 |
|
|
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3870 |
|
|
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3871 |
|
|
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
|
| 3872 |
|
|
|
| 3873 |
|
|
#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
|
| 3874 |
|
|
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 3875 |
|
|
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 3876 |
|
|
|
| 3877 |
|
|
#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
|
| 3878 |
|
|
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3879 |
|
|
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3880 |
|
|
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
|
| 3881 |
|
|
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
|
| 3882 |
|
|
|
| 3883 |
|
|
/******************* Bit definition for TIM_CCER register *******************/
|
| 3884 |
|
|
#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
|
| 3885 |
|
|
#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
|
| 3886 |
|
|
#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
|
| 3887 |
|
|
#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
|
| 3888 |
|
|
#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
|
| 3889 |
|
|
#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
|
| 3890 |
|
|
#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
|
| 3891 |
|
|
#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
|
| 3892 |
|
|
#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
|
| 3893 |
|
|
#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
|
| 3894 |
|
|
#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
|
| 3895 |
|
|
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
|
| 3896 |
|
|
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
|
| 3897 |
|
|
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
|
| 3898 |
|
|
|
| 3899 |
|
|
/******************* Bit definition for TIM_CNT register ********************/
|
| 3900 |
|
|
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
|
| 3901 |
|
|
|
| 3902 |
|
|
/******************* Bit definition for TIM_PSC register ********************/
|
| 3903 |
|
|
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
|
| 3904 |
|
|
|
| 3905 |
|
|
/******************* Bit definition for TIM_ARR register ********************/
|
| 3906 |
|
|
#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
|
| 3907 |
|
|
|
| 3908 |
|
|
/******************* Bit definition for TIM_RCR register ********************/
|
| 3909 |
|
|
#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
|
| 3910 |
|
|
|
| 3911 |
|
|
/******************* Bit definition for TIM_CCR1 register *******************/
|
| 3912 |
|
|
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
|
| 3913 |
|
|
|
| 3914 |
|
|
/******************* Bit definition for TIM_CCR2 register *******************/
|
| 3915 |
|
|
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
|
| 3916 |
|
|
|
| 3917 |
|
|
/******************* Bit definition for TIM_CCR3 register *******************/
|
| 3918 |
|
|
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
|
| 3919 |
|
|
|
| 3920 |
|
|
/******************* Bit definition for TIM_CCR4 register *******************/
|
| 3921 |
|
|
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
|
| 3922 |
|
|
|
| 3923 |
|
|
/******************* Bit definition for TIM_BDTR register *******************/
|
| 3924 |
|
|
#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
|
| 3925 |
|
|
#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3926 |
|
|
#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3927 |
|
|
#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
|
| 3928 |
|
|
#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
|
| 3929 |
|
|
#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
|
| 3930 |
|
|
#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
|
| 3931 |
|
|
#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
|
| 3932 |
|
|
#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
|
| 3933 |
|
|
|
| 3934 |
|
|
#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
|
| 3935 |
|
|
#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3936 |
|
|
#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3937 |
|
|
|
| 3938 |
|
|
#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
|
| 3939 |
|
|
#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
|
| 3940 |
|
|
#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
|
| 3941 |
|
|
#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
|
| 3942 |
|
|
#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
|
| 3943 |
|
|
#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
|
| 3944 |
|
|
|
| 3945 |
|
|
/******************* Bit definition for TIM_DCR register ********************/
|
| 3946 |
|
|
#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
|
| 3947 |
|
|
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3948 |
|
|
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3949 |
|
|
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
|
| 3950 |
|
|
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
|
| 3951 |
|
|
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
|
| 3952 |
|
|
|
| 3953 |
|
|
#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
|
| 3954 |
|
|
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3955 |
|
|
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3956 |
|
|
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
|
| 3957 |
|
|
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
|
| 3958 |
|
|
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
|
| 3959 |
|
|
|
| 3960 |
|
|
/******************* Bit definition for TIM_DMAR register *******************/
|
| 3961 |
|
|
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
|
| 3962 |
|
|
|
| 3963 |
|
|
/******************************************************************************/
|
| 3964 |
|
|
/* */
|
| 3965 |
|
|
/* Real-Time Clock */
|
| 3966 |
|
|
/* */
|
| 3967 |
|
|
/******************************************************************************/
|
| 3968 |
|
|
|
| 3969 |
|
|
/******************* Bit definition for RTC_CRH register ********************/
|
| 3970 |
|
|
#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */
|
| 3971 |
|
|
#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */
|
| 3972 |
|
|
#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */
|
| 3973 |
|
|
|
| 3974 |
|
|
/******************* Bit definition for RTC_CRL register ********************/
|
| 3975 |
|
|
#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */
|
| 3976 |
|
|
#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */
|
| 3977 |
|
|
#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */
|
| 3978 |
|
|
#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */
|
| 3979 |
|
|
#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */
|
| 3980 |
|
|
#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */
|
| 3981 |
|
|
|
| 3982 |
|
|
/******************* Bit definition for RTC_PRLH register *******************/
|
| 3983 |
|
|
#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */
|
| 3984 |
|
|
|
| 3985 |
|
|
/******************* Bit definition for RTC_PRLL register *******************/
|
| 3986 |
|
|
#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */
|
| 3987 |
|
|
|
| 3988 |
|
|
/******************* Bit definition for RTC_DIVH register *******************/
|
| 3989 |
|
|
#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */
|
| 3990 |
|
|
|
| 3991 |
|
|
/******************* Bit definition for RTC_DIVL register *******************/
|
| 3992 |
|
|
#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */
|
| 3993 |
|
|
|
| 3994 |
|
|
/******************* Bit definition for RTC_CNTH register *******************/
|
| 3995 |
|
|
#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */
|
| 3996 |
|
|
|
| 3997 |
|
|
/******************* Bit definition for RTC_CNTL register *******************/
|
| 3998 |
|
|
#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */
|
| 3999 |
|
|
|
| 4000 |
|
|
/******************* Bit definition for RTC_ALRH register *******************/
|
| 4001 |
|
|
#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */
|
| 4002 |
|
|
|
| 4003 |
|
|
/******************* Bit definition for RTC_ALRL register *******************/
|
| 4004 |
|
|
#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */
|
| 4005 |
|
|
|
| 4006 |
|
|
/******************************************************************************/
|
| 4007 |
|
|
/* */
|
| 4008 |
|
|
/* Independent WATCHDOG */
|
| 4009 |
|
|
/* */
|
| 4010 |
|
|
/******************************************************************************/
|
| 4011 |
|
|
|
| 4012 |
|
|
/******************* Bit definition for IWDG_KR register ********************/
|
| 4013 |
|
|
#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
|
| 4014 |
|
|
|
| 4015 |
|
|
/******************* Bit definition for IWDG_PR register ********************/
|
| 4016 |
|
|
#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
|
| 4017 |
|
|
#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
|
| 4018 |
|
|
#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
|
| 4019 |
|
|
#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
|
| 4020 |
|
|
|
| 4021 |
|
|
/******************* Bit definition for IWDG_RLR register *******************/
|
| 4022 |
|
|
#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
|
| 4023 |
|
|
|
| 4024 |
|
|
/******************* Bit definition for IWDG_SR register ********************/
|
| 4025 |
|
|
#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
|
| 4026 |
|
|
#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
|
| 4027 |
|
|
|
| 4028 |
|
|
/******************************************************************************/
|
| 4029 |
|
|
/* */
|
| 4030 |
|
|
/* Window WATCHDOG */
|
| 4031 |
|
|
/* */
|
| 4032 |
|
|
/******************************************************************************/
|
| 4033 |
|
|
|
| 4034 |
|
|
/******************* Bit definition for WWDG_CR register ********************/
|
| 4035 |
|
|
#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
| 4036 |
|
|
#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
|
| 4037 |
|
|
#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
|
| 4038 |
|
|
#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
|
| 4039 |
|
|
#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
|
| 4040 |
|
|
#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
|
| 4041 |
|
|
#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
|
| 4042 |
|
|
#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
|
| 4043 |
|
|
|
| 4044 |
|
|
#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
|
| 4045 |
|
|
|
| 4046 |
|
|
/******************* Bit definition for WWDG_CFR register *******************/
|
| 4047 |
|
|
#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
|
| 4048 |
|
|
#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 4049 |
|
|
#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 4050 |
|
|
#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
|
| 4051 |
|
|
#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
|
| 4052 |
|
|
#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
|
| 4053 |
|
|
#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
|
| 4054 |
|
|
#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
|
| 4055 |
|
|
|
| 4056 |
|
|
#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
|
| 4057 |
|
|
#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
|
| 4058 |
|
|
#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
|
| 4059 |
|
|
|
| 4060 |
|
|
#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
|
| 4061 |
|
|
|
| 4062 |
|
|
/******************* Bit definition for WWDG_SR register ********************/
|
| 4063 |
|
|
#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
|
| 4064 |
|
|
|
| 4065 |
|
|
/******************************************************************************/
|
| 4066 |
|
|
/* */
|
| 4067 |
|
|
/* Flexible Static Memory Controller */
|
| 4068 |
|
|
/* */
|
| 4069 |
|
|
/******************************************************************************/
|
| 4070 |
|
|
|
| 4071 |
|
|
/****************** Bit definition for FSMC_BCR1 register *******************/
|
| 4072 |
|
|
#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
| 4073 |
|
|
#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
| 4074 |
|
|
|
| 4075 |
|
|
#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
| 4076 |
|
|
#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
| 4077 |
|
|
#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
| 4078 |
|
|
|
| 4079 |
|
|
#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
| 4080 |
|
|
#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4081 |
|
|
#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4082 |
|
|
|
| 4083 |
|
|
#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
| 4084 |
|
|
#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
| 4085 |
|
|
#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
| 4086 |
|
|
#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
| 4087 |
|
|
#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
| 4088 |
|
|
#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
| 4089 |
|
|
#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
| 4090 |
|
|
#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
| 4091 |
|
|
#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
| 4092 |
|
|
|
| 4093 |
|
|
/****************** Bit definition for FSMC_BCR2 register *******************/
|
| 4094 |
|
|
#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
| 4095 |
|
|
#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
| 4096 |
|
|
|
| 4097 |
|
|
#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
| 4098 |
|
|
#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
| 4099 |
|
|
#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
| 4100 |
|
|
|
| 4101 |
|
|
#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
| 4102 |
|
|
#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4103 |
|
|
#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4104 |
|
|
|
| 4105 |
|
|
#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
| 4106 |
|
|
#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
| 4107 |
|
|
#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
| 4108 |
|
|
#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
| 4109 |
|
|
#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
| 4110 |
|
|
#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
| 4111 |
|
|
#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
| 4112 |
|
|
#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
| 4113 |
|
|
#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
| 4114 |
|
|
|
| 4115 |
|
|
/****************** Bit definition for FSMC_BCR3 register *******************/
|
| 4116 |
|
|
#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
| 4117 |
|
|
#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
| 4118 |
|
|
|
| 4119 |
|
|
#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
| 4120 |
|
|
#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
| 4121 |
|
|
#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
| 4122 |
|
|
|
| 4123 |
|
|
#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
| 4124 |
|
|
#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4125 |
|
|
#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4126 |
|
|
|
| 4127 |
|
|
#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
| 4128 |
|
|
#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
| 4129 |
|
|
#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */
|
| 4130 |
|
|
#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
| 4131 |
|
|
#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
| 4132 |
|
|
#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
| 4133 |
|
|
#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
| 4134 |
|
|
#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
| 4135 |
|
|
#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
| 4136 |
|
|
|
| 4137 |
|
|
/****************** Bit definition for FSMC_BCR4 register *******************/
|
| 4138 |
|
|
#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
| 4139 |
|
|
#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
| 4140 |
|
|
|
| 4141 |
|
|
#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
| 4142 |
|
|
#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
| 4143 |
|
|
#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
| 4144 |
|
|
|
| 4145 |
|
|
#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
| 4146 |
|
|
#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4147 |
|
|
#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4148 |
|
|
|
| 4149 |
|
|
#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
| 4150 |
|
|
#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
| 4151 |
|
|
#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
| 4152 |
|
|
#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
| 4153 |
|
|
#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
| 4154 |
|
|
#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
| 4155 |
|
|
#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
| 4156 |
|
|
#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
| 4157 |
|
|
#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
| 4158 |
|
|
|
| 4159 |
|
|
/****************** Bit definition for FSMC_BTR1 register ******************/
|
| 4160 |
|
|
#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
| 4161 |
|
|
#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4162 |
|
|
#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4163 |
|
|
#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4164 |
|
|
#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4165 |
|
|
|
| 4166 |
|
|
#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
| 4167 |
|
|
#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4168 |
|
|
#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4169 |
|
|
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
| 4170 |
|
|
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
| 4171 |
|
|
|
| 4172 |
|
|
#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
| 4173 |
|
|
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4174 |
|
|
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4175 |
|
|
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4176 |
|
|
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4177 |
|
|
|
| 4178 |
|
|
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
| 4179 |
|
|
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4180 |
|
|
#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4181 |
|
|
#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4182 |
|
|
#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4183 |
|
|
|
| 4184 |
|
|
#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
| 4185 |
|
|
#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 4186 |
|
|
#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 4187 |
|
|
#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 4188 |
|
|
#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 4189 |
|
|
|
| 4190 |
|
|
#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
| 4191 |
|
|
#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4192 |
|
|
#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4193 |
|
|
#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4194 |
|
|
#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4195 |
|
|
|
| 4196 |
|
|
#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
| 4197 |
|
|
#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
| 4198 |
|
|
#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
| 4199 |
|
|
|
| 4200 |
|
|
/****************** Bit definition for FSMC_BTR2 register *******************/
|
| 4201 |
|
|
#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
| 4202 |
|
|
#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4203 |
|
|
#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4204 |
|
|
#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4205 |
|
|
#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4206 |
|
|
|
| 4207 |
|
|
#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
| 4208 |
|
|
#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4209 |
|
|
#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4210 |
|
|
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
| 4211 |
|
|
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
| 4212 |
|
|
|
| 4213 |
|
|
#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
| 4214 |
|
|
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4215 |
|
|
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4216 |
|
|
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4217 |
|
|
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4218 |
|
|
|
| 4219 |
|
|
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
| 4220 |
|
|
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4221 |
|
|
#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4222 |
|
|
#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4223 |
|
|
#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4224 |
|
|
|
| 4225 |
|
|
#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
| 4226 |
|
|
#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 4227 |
|
|
#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 4228 |
|
|
#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 4229 |
|
|
#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 4230 |
|
|
|
| 4231 |
|
|
#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
| 4232 |
|
|
#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4233 |
|
|
#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4234 |
|
|
#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4235 |
|
|
#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4236 |
|
|
|
| 4237 |
|
|
#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
| 4238 |
|
|
#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
| 4239 |
|
|
#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
| 4240 |
|
|
|
| 4241 |
|
|
/******************* Bit definition for FSMC_BTR3 register *******************/
|
| 4242 |
|
|
#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
| 4243 |
|
|
#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4244 |
|
|
#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4245 |
|
|
#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4246 |
|
|
#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4247 |
|
|
|
| 4248 |
|
|
#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
| 4249 |
|
|
#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4250 |
|
|
#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4251 |
|
|
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
| 4252 |
|
|
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
| 4253 |
|
|
|
| 4254 |
|
|
#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
| 4255 |
|
|
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4256 |
|
|
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4257 |
|
|
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4258 |
|
|
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4259 |
|
|
|
| 4260 |
|
|
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
| 4261 |
|
|
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4262 |
|
|
#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4263 |
|
|
#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4264 |
|
|
#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4265 |
|
|
|
| 4266 |
|
|
#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
| 4267 |
|
|
#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 4268 |
|
|
#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 4269 |
|
|
#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 4270 |
|
|
#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 4271 |
|
|
|
| 4272 |
|
|
#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
| 4273 |
|
|
#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4274 |
|
|
#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4275 |
|
|
#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4276 |
|
|
#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4277 |
|
|
|
| 4278 |
|
|
#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
| 4279 |
|
|
#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
| 4280 |
|
|
#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
| 4281 |
|
|
|
| 4282 |
|
|
/****************** Bit definition for FSMC_BTR4 register *******************/
|
| 4283 |
|
|
#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
| 4284 |
|
|
#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4285 |
|
|
#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4286 |
|
|
#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4287 |
|
|
#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4288 |
|
|
|
| 4289 |
|
|
#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
| 4290 |
|
|
#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4291 |
|
|
#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4292 |
|
|
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
| 4293 |
|
|
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
| 4294 |
|
|
|
| 4295 |
|
|
#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
| 4296 |
|
|
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4297 |
|
|
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4298 |
|
|
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4299 |
|
|
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4300 |
|
|
|
| 4301 |
|
|
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
| 4302 |
|
|
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4303 |
|
|
#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4304 |
|
|
#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4305 |
|
|
#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4306 |
|
|
|
| 4307 |
|
|
#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
| 4308 |
|
|
#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 4309 |
|
|
#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 4310 |
|
|
#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 4311 |
|
|
#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 4312 |
|
|
|
| 4313 |
|
|
#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
| 4314 |
|
|
#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4315 |
|
|
#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4316 |
|
|
#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4317 |
|
|
#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4318 |
|
|
|
| 4319 |
|
|
#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
| 4320 |
|
|
#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
| 4321 |
|
|
#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
| 4322 |
|
|
|
| 4323 |
|
|
/****************** Bit definition for FSMC_BWTR1 register ******************/
|
| 4324 |
|
|
#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
| 4325 |
|
|
#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4326 |
|
|
#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4327 |
|
|
#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4328 |
|
|
#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4329 |
|
|
|
| 4330 |
|
|
#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
| 4331 |
|
|
#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4332 |
|
|
#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4333 |
|
|
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
| 4334 |
|
|
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
| 4335 |
|
|
|
| 4336 |
|
|
#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
| 4337 |
|
|
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4338 |
|
|
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4339 |
|
|
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4340 |
|
|
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4341 |
|
|
|
| 4342 |
|
|
#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
| 4343 |
|
|
#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 4344 |
|
|
#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 4345 |
|
|
#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 4346 |
|
|
#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 4347 |
|
|
|
| 4348 |
|
|
#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
| 4349 |
|
|
#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4350 |
|
|
#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4351 |
|
|
#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4352 |
|
|
#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4353 |
|
|
|
| 4354 |
|
|
#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
| 4355 |
|
|
#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
| 4356 |
|
|
#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
| 4357 |
|
|
|
| 4358 |
|
|
/****************** Bit definition for FSMC_BWTR2 register ******************/
|
| 4359 |
|
|
#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
| 4360 |
|
|
#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4361 |
|
|
#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4362 |
|
|
#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4363 |
|
|
#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4364 |
|
|
|
| 4365 |
|
|
#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
| 4366 |
|
|
#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4367 |
|
|
#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4368 |
|
|
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
| 4369 |
|
|
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
| 4370 |
|
|
|
| 4371 |
|
|
#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
| 4372 |
|
|
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4373 |
|
|
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4374 |
|
|
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4375 |
|
|
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4376 |
|
|
|
| 4377 |
|
|
#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
| 4378 |
|
|
#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 4379 |
|
|
#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
|
| 4380 |
|
|
#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 4381 |
|
|
#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 4382 |
|
|
|
| 4383 |
|
|
#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
| 4384 |
|
|
#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4385 |
|
|
#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4386 |
|
|
#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4387 |
|
|
#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4388 |
|
|
|
| 4389 |
|
|
#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
| 4390 |
|
|
#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
| 4391 |
|
|
#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
| 4392 |
|
|
|
| 4393 |
|
|
/****************** Bit definition for FSMC_BWTR3 register ******************/
|
| 4394 |
|
|
#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
| 4395 |
|
|
#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4396 |
|
|
#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4397 |
|
|
#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4398 |
|
|
#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4399 |
|
|
|
| 4400 |
|
|
#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
| 4401 |
|
|
#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4402 |
|
|
#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4403 |
|
|
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
| 4404 |
|
|
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
| 4405 |
|
|
|
| 4406 |
|
|
#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
| 4407 |
|
|
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4408 |
|
|
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4409 |
|
|
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4410 |
|
|
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4411 |
|
|
|
| 4412 |
|
|
#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
| 4413 |
|
|
#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 4414 |
|
|
#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 4415 |
|
|
#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 4416 |
|
|
#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 4417 |
|
|
|
| 4418 |
|
|
#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
| 4419 |
|
|
#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4420 |
|
|
#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4421 |
|
|
#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4422 |
|
|
#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4423 |
|
|
|
| 4424 |
|
|
#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
| 4425 |
|
|
#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
| 4426 |
|
|
#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
| 4427 |
|
|
|
| 4428 |
|
|
/****************** Bit definition for FSMC_BWTR4 register ******************/
|
| 4429 |
|
|
#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
| 4430 |
|
|
#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4431 |
|
|
#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4432 |
|
|
#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4433 |
|
|
#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4434 |
|
|
|
| 4435 |
|
|
#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
| 4436 |
|
|
#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4437 |
|
|
#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4438 |
|
|
#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
| 4439 |
|
|
#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
| 4440 |
|
|
|
| 4441 |
|
|
#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
| 4442 |
|
|
#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4443 |
|
|
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4444 |
|
|
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4445 |
|
|
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4446 |
|
|
|
| 4447 |
|
|
#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
| 4448 |
|
|
#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
| 4449 |
|
|
#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
| 4450 |
|
|
#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
| 4451 |
|
|
#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
| 4452 |
|
|
|
| 4453 |
|
|
#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
| 4454 |
|
|
#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4455 |
|
|
#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4456 |
|
|
#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4457 |
|
|
#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4458 |
|
|
|
| 4459 |
|
|
#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
| 4460 |
|
|
#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
| 4461 |
|
|
#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
| 4462 |
|
|
|
| 4463 |
|
|
/****************** Bit definition for FSMC_PCR2 register *******************/
|
| 4464 |
|
|
#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
|
| 4465 |
|
|
#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
|
| 4466 |
|
|
#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
|
| 4467 |
|
|
|
| 4468 |
|
|
#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
| 4469 |
|
|
#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4470 |
|
|
#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4471 |
|
|
|
| 4472 |
|
|
#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
|
| 4473 |
|
|
|
| 4474 |
|
|
#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
| 4475 |
|
|
#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
| 4476 |
|
|
#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
| 4477 |
|
|
#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
| 4478 |
|
|
#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
|
| 4479 |
|
|
|
| 4480 |
|
|
#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
|
| 4481 |
|
|
#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
| 4482 |
|
|
#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
| 4483 |
|
|
#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
| 4484 |
|
|
#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
| 4485 |
|
|
|
| 4486 |
|
|
#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
|
| 4487 |
|
|
#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
| 4488 |
|
|
#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
| 4489 |
|
|
#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
| 4490 |
|
|
|
| 4491 |
|
|
/****************** Bit definition for FSMC_PCR3 register *******************/
|
| 4492 |
|
|
#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
|
| 4493 |
|
|
#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
|
| 4494 |
|
|
#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
|
| 4495 |
|
|
|
| 4496 |
|
|
#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
| 4497 |
|
|
#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4498 |
|
|
#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4499 |
|
|
|
| 4500 |
|
|
#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
|
| 4501 |
|
|
|
| 4502 |
|
|
#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
| 4503 |
|
|
#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
| 4504 |
|
|
#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
| 4505 |
|
|
#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
| 4506 |
|
|
#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
|
| 4507 |
|
|
|
| 4508 |
|
|
#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
|
| 4509 |
|
|
#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
| 4510 |
|
|
#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
| 4511 |
|
|
#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
| 4512 |
|
|
#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
| 4513 |
|
|
|
| 4514 |
|
|
#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
|
| 4515 |
|
|
#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
| 4516 |
|
|
#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
| 4517 |
|
|
#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
| 4518 |
|
|
|
| 4519 |
|
|
/****************** Bit definition for FSMC_PCR4 register *******************/
|
| 4520 |
|
|
#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
|
| 4521 |
|
|
#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
|
| 4522 |
|
|
#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
|
| 4523 |
|
|
|
| 4524 |
|
|
#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
| 4525 |
|
|
#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 4526 |
|
|
#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 4527 |
|
|
|
| 4528 |
|
|
#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
|
| 4529 |
|
|
|
| 4530 |
|
|
#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
| 4531 |
|
|
#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
| 4532 |
|
|
#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
| 4533 |
|
|
#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
| 4534 |
|
|
#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
|
| 4535 |
|
|
|
| 4536 |
|
|
#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
|
| 4537 |
|
|
#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
| 4538 |
|
|
#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
| 4539 |
|
|
#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
| 4540 |
|
|
#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
| 4541 |
|
|
|
| 4542 |
|
|
#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
|
| 4543 |
|
|
#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
| 4544 |
|
|
#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
| 4545 |
|
|
#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
| 4546 |
|
|
|
| 4547 |
|
|
/******************* Bit definition for FSMC_SR2 register *******************/
|
| 4548 |
|
|
#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
|
| 4549 |
|
|
#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
|
| 4550 |
|
|
#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
|
| 4551 |
|
|
#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
|
| 4552 |
|
|
#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
|
| 4553 |
|
|
#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
|
| 4554 |
|
|
#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
|
| 4555 |
|
|
|
| 4556 |
|
|
/******************* Bit definition for FSMC_SR3 register *******************/
|
| 4557 |
|
|
#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
|
| 4558 |
|
|
#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
|
| 4559 |
|
|
#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
|
| 4560 |
|
|
#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
|
| 4561 |
|
|
#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
|
| 4562 |
|
|
#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
|
| 4563 |
|
|
#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
|
| 4564 |
|
|
|
| 4565 |
|
|
/******************* Bit definition for FSMC_SR4 register *******************/
|
| 4566 |
|
|
#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
|
| 4567 |
|
|
#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
|
| 4568 |
|
|
#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
|
| 4569 |
|
|
#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
|
| 4570 |
|
|
#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
|
| 4571 |
|
|
#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
|
| 4572 |
|
|
#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
|
| 4573 |
|
|
|
| 4574 |
|
|
/****************** Bit definition for FSMC_PMEM2 register ******************/
|
| 4575 |
|
|
#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
|
| 4576 |
|
|
#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4577 |
|
|
#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4578 |
|
|
#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4579 |
|
|
#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4580 |
|
|
#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 4581 |
|
|
#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
| 4582 |
|
|
#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
| 4583 |
|
|
#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
| 4584 |
|
|
|
| 4585 |
|
|
#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
|
| 4586 |
|
|
#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4587 |
|
|
#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4588 |
|
|
#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4589 |
|
|
#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4590 |
|
|
#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
| 4591 |
|
|
#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
| 4592 |
|
|
#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
| 4593 |
|
|
#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
| 4594 |
|
|
|
| 4595 |
|
|
#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
|
| 4596 |
|
|
#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4597 |
|
|
#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4598 |
|
|
#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4599 |
|
|
#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4600 |
|
|
#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
| 4601 |
|
|
#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
| 4602 |
|
|
#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
| 4603 |
|
|
#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
| 4604 |
|
|
|
| 4605 |
|
|
#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
|
| 4606 |
|
|
#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4607 |
|
|
#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4608 |
|
|
#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4609 |
|
|
#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4610 |
|
|
#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
| 4611 |
|
|
#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
| 4612 |
|
|
#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
| 4613 |
|
|
#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
| 4614 |
|
|
|
| 4615 |
|
|
/****************** Bit definition for FSMC_PMEM3 register ******************/
|
| 4616 |
|
|
#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
|
| 4617 |
|
|
#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4618 |
|
|
#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4619 |
|
|
#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4620 |
|
|
#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4621 |
|
|
#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 4622 |
|
|
#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
| 4623 |
|
|
#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
| 4624 |
|
|
#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
| 4625 |
|
|
|
| 4626 |
|
|
#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
|
| 4627 |
|
|
#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4628 |
|
|
#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4629 |
|
|
#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4630 |
|
|
#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4631 |
|
|
#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
| 4632 |
|
|
#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
| 4633 |
|
|
#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
| 4634 |
|
|
#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
| 4635 |
|
|
|
| 4636 |
|
|
#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
|
| 4637 |
|
|
#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4638 |
|
|
#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4639 |
|
|
#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4640 |
|
|
#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4641 |
|
|
#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
| 4642 |
|
|
#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
| 4643 |
|
|
#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
| 4644 |
|
|
#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
| 4645 |
|
|
|
| 4646 |
|
|
#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
|
| 4647 |
|
|
#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4648 |
|
|
#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4649 |
|
|
#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4650 |
|
|
#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4651 |
|
|
#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
| 4652 |
|
|
#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
| 4653 |
|
|
#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
| 4654 |
|
|
#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
| 4655 |
|
|
|
| 4656 |
|
|
/****************** Bit definition for FSMC_PMEM4 register ******************/
|
| 4657 |
|
|
#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
|
| 4658 |
|
|
#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4659 |
|
|
#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4660 |
|
|
#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4661 |
|
|
#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4662 |
|
|
#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 4663 |
|
|
#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
| 4664 |
|
|
#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
| 4665 |
|
|
#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
| 4666 |
|
|
|
| 4667 |
|
|
#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
|
| 4668 |
|
|
#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4669 |
|
|
#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4670 |
|
|
#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4671 |
|
|
#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4672 |
|
|
#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
| 4673 |
|
|
#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
| 4674 |
|
|
#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
| 4675 |
|
|
#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
| 4676 |
|
|
|
| 4677 |
|
|
#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
|
| 4678 |
|
|
#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4679 |
|
|
#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4680 |
|
|
#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4681 |
|
|
#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4682 |
|
|
#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
| 4683 |
|
|
#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
| 4684 |
|
|
#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
| 4685 |
|
|
#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
| 4686 |
|
|
|
| 4687 |
|
|
#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
|
| 4688 |
|
|
#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4689 |
|
|
#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4690 |
|
|
#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4691 |
|
|
#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4692 |
|
|
#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
| 4693 |
|
|
#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
| 4694 |
|
|
#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
| 4695 |
|
|
#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
| 4696 |
|
|
|
| 4697 |
|
|
/****************** Bit definition for FSMC_PATT2 register ******************/
|
| 4698 |
|
|
#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
|
| 4699 |
|
|
#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4700 |
|
|
#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4701 |
|
|
#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4702 |
|
|
#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4703 |
|
|
#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 4704 |
|
|
#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
| 4705 |
|
|
#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
| 4706 |
|
|
#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
| 4707 |
|
|
|
| 4708 |
|
|
#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
|
| 4709 |
|
|
#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4710 |
|
|
#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4711 |
|
|
#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4712 |
|
|
#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4713 |
|
|
#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
| 4714 |
|
|
#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
| 4715 |
|
|
#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
| 4716 |
|
|
#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
| 4717 |
|
|
|
| 4718 |
|
|
#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
|
| 4719 |
|
|
#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4720 |
|
|
#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4721 |
|
|
#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4722 |
|
|
#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4723 |
|
|
#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
| 4724 |
|
|
#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
| 4725 |
|
|
#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
| 4726 |
|
|
#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
| 4727 |
|
|
|
| 4728 |
|
|
#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
|
| 4729 |
|
|
#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4730 |
|
|
#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4731 |
|
|
#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4732 |
|
|
#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4733 |
|
|
#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
| 4734 |
|
|
#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
| 4735 |
|
|
#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
| 4736 |
|
|
#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
| 4737 |
|
|
|
| 4738 |
|
|
/****************** Bit definition for FSMC_PATT3 register ******************/
|
| 4739 |
|
|
#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
|
| 4740 |
|
|
#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4741 |
|
|
#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4742 |
|
|
#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4743 |
|
|
#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4744 |
|
|
#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 4745 |
|
|
#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
| 4746 |
|
|
#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
| 4747 |
|
|
#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
| 4748 |
|
|
|
| 4749 |
|
|
#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
|
| 4750 |
|
|
#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4751 |
|
|
#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4752 |
|
|
#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4753 |
|
|
#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4754 |
|
|
#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
| 4755 |
|
|
#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
| 4756 |
|
|
#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
| 4757 |
|
|
#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
| 4758 |
|
|
|
| 4759 |
|
|
#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
|
| 4760 |
|
|
#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4761 |
|
|
#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4762 |
|
|
#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4763 |
|
|
#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4764 |
|
|
#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
| 4765 |
|
|
#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
| 4766 |
|
|
#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
| 4767 |
|
|
#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
| 4768 |
|
|
|
| 4769 |
|
|
#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
|
| 4770 |
|
|
#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4771 |
|
|
#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4772 |
|
|
#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4773 |
|
|
#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4774 |
|
|
#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
| 4775 |
|
|
#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
| 4776 |
|
|
#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
| 4777 |
|
|
#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
| 4778 |
|
|
|
| 4779 |
|
|
/****************** Bit definition for FSMC_PATT4 register ******************/
|
| 4780 |
|
|
#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
|
| 4781 |
|
|
#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4782 |
|
|
#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4783 |
|
|
#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4784 |
|
|
#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4785 |
|
|
#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 4786 |
|
|
#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
| 4787 |
|
|
#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
| 4788 |
|
|
#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
| 4789 |
|
|
|
| 4790 |
|
|
#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
|
| 4791 |
|
|
#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4792 |
|
|
#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4793 |
|
|
#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4794 |
|
|
#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4795 |
|
|
#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
| 4796 |
|
|
#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
| 4797 |
|
|
#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
| 4798 |
|
|
#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
| 4799 |
|
|
|
| 4800 |
|
|
#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
|
| 4801 |
|
|
#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4802 |
|
|
#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4803 |
|
|
#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4804 |
|
|
#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4805 |
|
|
#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
| 4806 |
|
|
#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
| 4807 |
|
|
#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
| 4808 |
|
|
#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
| 4809 |
|
|
|
| 4810 |
|
|
#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
|
| 4811 |
|
|
#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4812 |
|
|
#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4813 |
|
|
#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4814 |
|
|
#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4815 |
|
|
#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
| 4816 |
|
|
#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
| 4817 |
|
|
#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
| 4818 |
|
|
#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
| 4819 |
|
|
|
| 4820 |
|
|
/****************** Bit definition for FSMC_PIO4 register *******************/
|
| 4821 |
|
|
#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
|
| 4822 |
|
|
#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
| 4823 |
|
|
#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
| 4824 |
|
|
#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
| 4825 |
|
|
#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
| 4826 |
|
|
#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
| 4827 |
|
|
#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
| 4828 |
|
|
#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
| 4829 |
|
|
#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
| 4830 |
|
|
|
| 4831 |
|
|
#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
|
| 4832 |
|
|
#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 4833 |
|
|
#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 4834 |
|
|
#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 4835 |
|
|
#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 4836 |
|
|
#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
| 4837 |
|
|
#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
| 4838 |
|
|
#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
| 4839 |
|
|
#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
| 4840 |
|
|
|
| 4841 |
|
|
#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
|
| 4842 |
|
|
#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 4843 |
|
|
#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 4844 |
|
|
#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 4845 |
|
|
#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 4846 |
|
|
#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
| 4847 |
|
|
#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
| 4848 |
|
|
#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
| 4849 |
|
|
#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
| 4850 |
|
|
|
| 4851 |
|
|
#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
|
| 4852 |
|
|
#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 4853 |
|
|
#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 4854 |
|
|
#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 4855 |
|
|
#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 4856 |
|
|
#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
| 4857 |
|
|
#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
| 4858 |
|
|
#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
| 4859 |
|
|
#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
| 4860 |
|
|
|
| 4861 |
|
|
/****************** Bit definition for FSMC_ECCR2 register ******************/
|
| 4862 |
|
|
#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
|
| 4863 |
|
|
|
| 4864 |
|
|
/****************** Bit definition for FSMC_ECCR3 register ******************/
|
| 4865 |
|
|
#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
|
| 4866 |
|
|
|
| 4867 |
|
|
/******************************************************************************/
|
| 4868 |
|
|
/* */
|
| 4869 |
|
|
/* SD host Interface */
|
| 4870 |
|
|
/* */
|
| 4871 |
|
|
/******************************************************************************/
|
| 4872 |
|
|
|
| 4873 |
|
|
/****************** Bit definition for SDIO_POWER register ******************/
|
| 4874 |
|
|
#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
|
| 4875 |
|
|
#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
|
| 4876 |
|
|
#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
|
| 4877 |
|
|
|
| 4878 |
|
|
/****************** Bit definition for SDIO_CLKCR register ******************/
|
| 4879 |
|
|
#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
|
| 4880 |
|
|
#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
|
| 4881 |
|
|
#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
|
| 4882 |
|
|
#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
|
| 4883 |
|
|
|
| 4884 |
|
|
#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
|
| 4885 |
|
|
#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
|
| 4886 |
|
|
#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
|
| 4887 |
|
|
|
| 4888 |
|
|
#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
|
| 4889 |
|
|
#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
|
| 4890 |
|
|
|
| 4891 |
|
|
/******************* Bit definition for SDIO_ARG register *******************/
|
| 4892 |
|
|
#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
|
| 4893 |
|
|
|
| 4894 |
|
|
/******************* Bit definition for SDIO_CMD register *******************/
|
| 4895 |
|
|
#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
|
| 4896 |
|
|
|
| 4897 |
|
|
#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
|
| 4898 |
|
|
#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
|
| 4899 |
|
|
#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
|
| 4900 |
|
|
|
| 4901 |
|
|
#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
|
| 4902 |
|
|
#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
|
| 4903 |
|
|
#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
|
| 4904 |
|
|
#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
|
| 4905 |
|
|
#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
|
| 4906 |
|
|
#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
|
| 4907 |
|
|
#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
|
| 4908 |
|
|
|
| 4909 |
|
|
/***************** Bit definition for SDIO_RESPCMD register *****************/
|
| 4910 |
|
|
#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
|
| 4911 |
|
|
|
| 4912 |
|
|
/****************** Bit definition for SDIO_RESP0 register ******************/
|
| 4913 |
|
|
#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
| 4914 |
|
|
|
| 4915 |
|
|
/****************** Bit definition for SDIO_RESP1 register ******************/
|
| 4916 |
|
|
#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
| 4917 |
|
|
|
| 4918 |
|
|
/****************** Bit definition for SDIO_RESP2 register ******************/
|
| 4919 |
|
|
#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
| 4920 |
|
|
|
| 4921 |
|
|
/****************** Bit definition for SDIO_RESP3 register ******************/
|
| 4922 |
|
|
#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
| 4923 |
|
|
|
| 4924 |
|
|
/****************** Bit definition for SDIO_RESP4 register ******************/
|
| 4925 |
|
|
#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
| 4926 |
|
|
|
| 4927 |
|
|
/****************** Bit definition for SDIO_DTIMER register *****************/
|
| 4928 |
|
|
#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
|
| 4929 |
|
|
|
| 4930 |
|
|
/****************** Bit definition for SDIO_DLEN register *******************/
|
| 4931 |
|
|
#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
|
| 4932 |
|
|
|
| 4933 |
|
|
/****************** Bit definition for SDIO_DCTRL register ******************/
|
| 4934 |
|
|
#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
|
| 4935 |
|
|
#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
|
| 4936 |
|
|
#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
|
| 4937 |
|
|
#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
|
| 4938 |
|
|
|
| 4939 |
|
|
#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
|
| 4940 |
|
|
#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 4941 |
|
|
#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 4942 |
|
|
#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 4943 |
|
|
#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
|
| 4944 |
|
|
|
| 4945 |
|
|
#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
|
| 4946 |
|
|
#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
|
| 4947 |
|
|
#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
|
| 4948 |
|
|
#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
|
| 4949 |
|
|
|
| 4950 |
|
|
/****************** Bit definition for SDIO_DCOUNT register *****************/
|
| 4951 |
|
|
#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
|
| 4952 |
|
|
|
| 4953 |
|
|
/****************** Bit definition for SDIO_STA register ********************/
|
| 4954 |
|
|
#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
|
| 4955 |
|
|
#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
|
| 4956 |
|
|
#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
|
| 4957 |
|
|
#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
|
| 4958 |
|
|
#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
|
| 4959 |
|
|
#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
|
| 4960 |
|
|
#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
|
| 4961 |
|
|
#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
|
| 4962 |
|
|
#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
|
| 4963 |
|
|
#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
|
| 4964 |
|
|
#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
|
| 4965 |
|
|
#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
|
| 4966 |
|
|
#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
|
| 4967 |
|
|
#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
|
| 4968 |
|
|
#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
|
| 4969 |
|
|
#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
|
| 4970 |
|
|
#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
|
| 4971 |
|
|
#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
|
| 4972 |
|
|
#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
|
| 4973 |
|
|
#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
|
| 4974 |
|
|
#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
|
| 4975 |
|
|
#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
|
| 4976 |
|
|
#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
|
| 4977 |
|
|
#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
|
| 4978 |
|
|
|
| 4979 |
|
|
/******************* Bit definition for SDIO_ICR register *******************/
|
| 4980 |
|
|
#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
|
| 4981 |
|
|
#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
|
| 4982 |
|
|
#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
|
| 4983 |
|
|
#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
|
| 4984 |
|
|
#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
|
| 4985 |
|
|
#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
|
| 4986 |
|
|
#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
|
| 4987 |
|
|
#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
|
| 4988 |
|
|
#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
|
| 4989 |
|
|
#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
|
| 4990 |
|
|
#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
|
| 4991 |
|
|
#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
|
| 4992 |
|
|
#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
|
| 4993 |
|
|
|
| 4994 |
|
|
/****************** Bit definition for SDIO_MASK register *******************/
|
| 4995 |
|
|
#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
|
| 4996 |
|
|
#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
|
| 4997 |
|
|
#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
|
| 4998 |
|
|
#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
|
| 4999 |
|
|
#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
|
| 5000 |
|
|
#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
|
| 5001 |
|
|
#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
|
| 5002 |
|
|
#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
|
| 5003 |
|
|
#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
|
| 5004 |
|
|
#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
|
| 5005 |
|
|
#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
|
| 5006 |
|
|
#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
|
| 5007 |
|
|
#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
|
| 5008 |
|
|
#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
|
| 5009 |
|
|
#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
|
| 5010 |
|
|
#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
|
| 5011 |
|
|
#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
|
| 5012 |
|
|
#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
|
| 5013 |
|
|
#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
|
| 5014 |
|
|
#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
|
| 5015 |
|
|
#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
|
| 5016 |
|
|
#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
|
| 5017 |
|
|
#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
|
| 5018 |
|
|
#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
|
| 5019 |
|
|
|
| 5020 |
|
|
/***************** Bit definition for SDIO_FIFOCNT register *****************/
|
| 5021 |
|
|
#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
|
| 5022 |
|
|
|
| 5023 |
|
|
/****************** Bit definition for SDIO_FIFO register *******************/
|
| 5024 |
|
|
#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
|
| 5025 |
|
|
|
| 5026 |
|
|
/******************************************************************************/
|
| 5027 |
|
|
/* */
|
| 5028 |
|
|
/* USB Device FS */
|
| 5029 |
|
|
/* */
|
| 5030 |
|
|
/******************************************************************************/
|
| 5031 |
|
|
|
| 5032 |
|
|
/*!<Endpoint-specific registers */
|
| 5033 |
|
|
/******************* Bit definition for USB_EP0R register *******************/
|
| 5034 |
|
|
#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 5035 |
|
|
|
| 5036 |
|
|
#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 5037 |
|
|
#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 5038 |
|
|
#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 5039 |
|
|
|
| 5040 |
|
|
#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 5041 |
|
|
#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 5042 |
|
|
#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 5043 |
|
|
|
| 5044 |
|
|
#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 5045 |
|
|
#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 5046 |
|
|
#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 5047 |
|
|
|
| 5048 |
|
|
#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 5049 |
|
|
|
| 5050 |
|
|
#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 5051 |
|
|
#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 5052 |
|
|
#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 5053 |
|
|
|
| 5054 |
|
|
#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 5055 |
|
|
#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 5056 |
|
|
|
| 5057 |
|
|
/******************* Bit definition for USB_EP1R register *******************/
|
| 5058 |
|
|
#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 5059 |
|
|
|
| 5060 |
|
|
#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 5061 |
|
|
#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 5062 |
|
|
#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 5063 |
|
|
|
| 5064 |
|
|
#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 5065 |
|
|
#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 5066 |
|
|
#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 5067 |
|
|
|
| 5068 |
|
|
#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 5069 |
|
|
#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 5070 |
|
|
#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 5071 |
|
|
|
| 5072 |
|
|
#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 5073 |
|
|
|
| 5074 |
|
|
#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 5075 |
|
|
#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 5076 |
|
|
#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 5077 |
|
|
|
| 5078 |
|
|
#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 5079 |
|
|
#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 5080 |
|
|
|
| 5081 |
|
|
/******************* Bit definition for USB_EP2R register *******************/
|
| 5082 |
|
|
#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 5083 |
|
|
|
| 5084 |
|
|
#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 5085 |
|
|
#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 5086 |
|
|
#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 5087 |
|
|
|
| 5088 |
|
|
#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 5089 |
|
|
#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 5090 |
|
|
#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 5091 |
|
|
|
| 5092 |
|
|
#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 5093 |
|
|
#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 5094 |
|
|
#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 5095 |
|
|
|
| 5096 |
|
|
#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 5097 |
|
|
|
| 5098 |
|
|
#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 5099 |
|
|
#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 5100 |
|
|
#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 5101 |
|
|
|
| 5102 |
|
|
#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 5103 |
|
|
#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 5104 |
|
|
|
| 5105 |
|
|
/******************* Bit definition for USB_EP3R register *******************/
|
| 5106 |
|
|
#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 5107 |
|
|
|
| 5108 |
|
|
#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 5109 |
|
|
#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 5110 |
|
|
#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 5111 |
|
|
|
| 5112 |
|
|
#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 5113 |
|
|
#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 5114 |
|
|
#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 5115 |
|
|
|
| 5116 |
|
|
#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 5117 |
|
|
#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 5118 |
|
|
#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 5119 |
|
|
|
| 5120 |
|
|
#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 5121 |
|
|
|
| 5122 |
|
|
#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 5123 |
|
|
#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 5124 |
|
|
#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 5125 |
|
|
|
| 5126 |
|
|
#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 5127 |
|
|
#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 5128 |
|
|
|
| 5129 |
|
|
/******************* Bit definition for USB_EP4R register *******************/
|
| 5130 |
|
|
#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 5131 |
|
|
|
| 5132 |
|
|
#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 5133 |
|
|
#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 5134 |
|
|
#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 5135 |
|
|
|
| 5136 |
|
|
#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 5137 |
|
|
#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 5138 |
|
|
#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 5139 |
|
|
|
| 5140 |
|
|
#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 5141 |
|
|
#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 5142 |
|
|
#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 5143 |
|
|
|
| 5144 |
|
|
#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 5145 |
|
|
|
| 5146 |
|
|
#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 5147 |
|
|
#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 5148 |
|
|
#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 5149 |
|
|
|
| 5150 |
|
|
#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 5151 |
|
|
#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 5152 |
|
|
|
| 5153 |
|
|
/******************* Bit definition for USB_EP5R register *******************/
|
| 5154 |
|
|
#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 5155 |
|
|
|
| 5156 |
|
|
#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 5157 |
|
|
#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 5158 |
|
|
#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 5159 |
|
|
|
| 5160 |
|
|
#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 5161 |
|
|
#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 5162 |
|
|
#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 5163 |
|
|
|
| 5164 |
|
|
#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 5165 |
|
|
#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 5166 |
|
|
#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 5167 |
|
|
|
| 5168 |
|
|
#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 5169 |
|
|
|
| 5170 |
|
|
#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 5171 |
|
|
#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 5172 |
|
|
#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 5173 |
|
|
|
| 5174 |
|
|
#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 5175 |
|
|
#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 5176 |
|
|
|
| 5177 |
|
|
/******************* Bit definition for USB_EP6R register *******************/
|
| 5178 |
|
|
#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 5179 |
|
|
|
| 5180 |
|
|
#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 5181 |
|
|
#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 5182 |
|
|
#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 5183 |
|
|
|
| 5184 |
|
|
#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 5185 |
|
|
#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 5186 |
|
|
#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 5187 |
|
|
|
| 5188 |
|
|
#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 5189 |
|
|
#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 5190 |
|
|
#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 5191 |
|
|
|
| 5192 |
|
|
#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 5193 |
|
|
|
| 5194 |
|
|
#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 5195 |
|
|
#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 5196 |
|
|
#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 5197 |
|
|
|
| 5198 |
|
|
#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 5199 |
|
|
#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 5200 |
|
|
|
| 5201 |
|
|
/******************* Bit definition for USB_EP7R register *******************/
|
| 5202 |
|
|
#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 5203 |
|
|
|
| 5204 |
|
|
#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 5205 |
|
|
#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 5206 |
|
|
#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 5207 |
|
|
|
| 5208 |
|
|
#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 5209 |
|
|
#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 5210 |
|
|
#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 5211 |
|
|
|
| 5212 |
|
|
#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 5213 |
|
|
#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 5214 |
|
|
#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 5215 |
|
|
|
| 5216 |
|
|
#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 5217 |
|
|
|
| 5218 |
|
|
#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 5219 |
|
|
#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 5220 |
|
|
#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 5221 |
|
|
|
| 5222 |
|
|
#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 5223 |
|
|
#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 5224 |
|
|
|
| 5225 |
|
|
/*!<Common registers */
|
| 5226 |
|
|
/******************* Bit definition for USB_CNTR register *******************/
|
| 5227 |
|
|
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
|
| 5228 |
|
|
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
|
| 5229 |
|
|
#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
|
| 5230 |
|
|
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
|
| 5231 |
|
|
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
|
| 5232 |
|
|
#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
|
| 5233 |
|
|
#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
|
| 5234 |
|
|
#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
|
| 5235 |
|
|
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
|
| 5236 |
|
|
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
|
| 5237 |
|
|
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
|
| 5238 |
|
|
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
|
| 5239 |
|
|
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
|
| 5240 |
|
|
|
| 5241 |
|
|
/******************* Bit definition for USB_ISTR register *******************/
|
| 5242 |
|
|
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
|
| 5243 |
|
|
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
|
| 5244 |
|
|
#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
|
| 5245 |
|
|
#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
|
| 5246 |
|
|
#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
|
| 5247 |
|
|
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
|
| 5248 |
|
|
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
|
| 5249 |
|
|
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
|
| 5250 |
|
|
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
|
| 5251 |
|
|
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
|
| 5252 |
|
|
|
| 5253 |
|
|
/******************* Bit definition for USB_FNR register ********************/
|
| 5254 |
|
|
#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
|
| 5255 |
|
|
#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
|
| 5256 |
|
|
#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
|
| 5257 |
|
|
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
|
| 5258 |
|
|
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
|
| 5259 |
|
|
|
| 5260 |
|
|
/****************** Bit definition for USB_DADDR register *******************/
|
| 5261 |
|
|
#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
|
| 5262 |
|
|
#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
|
| 5263 |
|
|
#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
|
| 5264 |
|
|
#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
|
| 5265 |
|
|
#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
|
| 5266 |
|
|
#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
|
| 5267 |
|
|
#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
|
| 5268 |
|
|
#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
|
| 5269 |
|
|
|
| 5270 |
|
|
#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
|
| 5271 |
|
|
|
| 5272 |
|
|
/****************** Bit definition for USB_BTABLE register ******************/
|
| 5273 |
|
|
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
|
| 5274 |
|
|
|
| 5275 |
|
|
/*!<Buffer descriptor table */
|
| 5276 |
|
|
/***************** Bit definition for USB_ADDR0_TX register *****************/
|
| 5277 |
|
|
#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */
|
| 5278 |
|
|
|
| 5279 |
|
|
/***************** Bit definition for USB_ADDR1_TX register *****************/
|
| 5280 |
|
|
#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */
|
| 5281 |
|
|
|
| 5282 |
|
|
/***************** Bit definition for USB_ADDR2_TX register *****************/
|
| 5283 |
|
|
#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */
|
| 5284 |
|
|
|
| 5285 |
|
|
/***************** Bit definition for USB_ADDR3_TX register *****************/
|
| 5286 |
|
|
#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */
|
| 5287 |
|
|
|
| 5288 |
|
|
/***************** Bit definition for USB_ADDR4_TX register *****************/
|
| 5289 |
|
|
#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */
|
| 5290 |
|
|
|
| 5291 |
|
|
/***************** Bit definition for USB_ADDR5_TX register *****************/
|
| 5292 |
|
|
#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */
|
| 5293 |
|
|
|
| 5294 |
|
|
/***************** Bit definition for USB_ADDR6_TX register *****************/
|
| 5295 |
|
|
#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */
|
| 5296 |
|
|
|
| 5297 |
|
|
/***************** Bit definition for USB_ADDR7_TX register *****************/
|
| 5298 |
|
|
#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */
|
| 5299 |
|
|
|
| 5300 |
|
|
/*----------------------------------------------------------------------------*/
|
| 5301 |
|
|
|
| 5302 |
|
|
/***************** Bit definition for USB_COUNT0_TX register ****************/
|
| 5303 |
|
|
#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */
|
| 5304 |
|
|
|
| 5305 |
|
|
/***************** Bit definition for USB_COUNT1_TX register ****************/
|
| 5306 |
|
|
#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */
|
| 5307 |
|
|
|
| 5308 |
|
|
/***************** Bit definition for USB_COUNT2_TX register ****************/
|
| 5309 |
|
|
#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */
|
| 5310 |
|
|
|
| 5311 |
|
|
/***************** Bit definition for USB_COUNT3_TX register ****************/
|
| 5312 |
|
|
#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */
|
| 5313 |
|
|
|
| 5314 |
|
|
/***************** Bit definition for USB_COUNT4_TX register ****************/
|
| 5315 |
|
|
#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */
|
| 5316 |
|
|
|
| 5317 |
|
|
/***************** Bit definition for USB_COUNT5_TX register ****************/
|
| 5318 |
|
|
#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */
|
| 5319 |
|
|
|
| 5320 |
|
|
/***************** Bit definition for USB_COUNT6_TX register ****************/
|
| 5321 |
|
|
#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */
|
| 5322 |
|
|
|
| 5323 |
|
|
/***************** Bit definition for USB_COUNT7_TX register ****************/
|
| 5324 |
|
|
#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */
|
| 5325 |
|
|
|
| 5326 |
|
|
/*----------------------------------------------------------------------------*/
|
| 5327 |
|
|
|
| 5328 |
|
|
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
|
| 5329 |
|
|
#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */
|
| 5330 |
|
|
|
| 5331 |
|
|
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
|
| 5332 |
|
|
#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */
|
| 5333 |
|
|
|
| 5334 |
|
|
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
|
| 5335 |
|
|
#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */
|
| 5336 |
|
|
|
| 5337 |
|
|
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
|
| 5338 |
|
|
#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */
|
| 5339 |
|
|
|
| 5340 |
|
|
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
|
| 5341 |
|
|
#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */
|
| 5342 |
|
|
|
| 5343 |
|
|
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
|
| 5344 |
|
|
#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */
|
| 5345 |
|
|
|
| 5346 |
|
|
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
|
| 5347 |
|
|
#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */
|
| 5348 |
|
|
|
| 5349 |
|
|
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
|
| 5350 |
|
|
#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */
|
| 5351 |
|
|
|
| 5352 |
|
|
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
|
| 5353 |
|
|
#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */
|
| 5354 |
|
|
|
| 5355 |
|
|
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
|
| 5356 |
|
|
#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */
|
| 5357 |
|
|
|
| 5358 |
|
|
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
|
| 5359 |
|
|
#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */
|
| 5360 |
|
|
|
| 5361 |
|
|
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
|
| 5362 |
|
|
#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */
|
| 5363 |
|
|
|
| 5364 |
|
|
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
|
| 5365 |
|
|
#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */
|
| 5366 |
|
|
|
| 5367 |
|
|
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
|
| 5368 |
|
|
#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */
|
| 5369 |
|
|
|
| 5370 |
|
|
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
|
| 5371 |
|
|
#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */
|
| 5372 |
|
|
|
| 5373 |
|
|
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
|
| 5374 |
|
|
#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */
|
| 5375 |
|
|
|
| 5376 |
|
|
/*----------------------------------------------------------------------------*/
|
| 5377 |
|
|
|
| 5378 |
|
|
/***************** Bit definition for USB_ADDR0_RX register *****************/
|
| 5379 |
|
|
#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */
|
| 5380 |
|
|
|
| 5381 |
|
|
/***************** Bit definition for USB_ADDR1_RX register *****************/
|
| 5382 |
|
|
#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */
|
| 5383 |
|
|
|
| 5384 |
|
|
/***************** Bit definition for USB_ADDR2_RX register *****************/
|
| 5385 |
|
|
#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */
|
| 5386 |
|
|
|
| 5387 |
|
|
/***************** Bit definition for USB_ADDR3_RX register *****************/
|
| 5388 |
|
|
#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */
|
| 5389 |
|
|
|
| 5390 |
|
|
/***************** Bit definition for USB_ADDR4_RX register *****************/
|
| 5391 |
|
|
#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */
|
| 5392 |
|
|
|
| 5393 |
|
|
/***************** Bit definition for USB_ADDR5_RX register *****************/
|
| 5394 |
|
|
#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */
|
| 5395 |
|
|
|
| 5396 |
|
|
/***************** Bit definition for USB_ADDR6_RX register *****************/
|
| 5397 |
|
|
#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */
|
| 5398 |
|
|
|
| 5399 |
|
|
/***************** Bit definition for USB_ADDR7_RX register *****************/
|
| 5400 |
|
|
#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */
|
| 5401 |
|
|
|
| 5402 |
|
|
/*----------------------------------------------------------------------------*/
|
| 5403 |
|
|
|
| 5404 |
|
|
/***************** Bit definition for USB_COUNT0_RX register ****************/
|
| 5405 |
|
|
#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
|
| 5406 |
|
|
|
| 5407 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 5408 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 5409 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 5410 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
|
| 5411 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
|
| 5412 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
|
| 5413 |
|
|
|
| 5414 |
|
|
#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
|
| 5415 |
|
|
|
| 5416 |
|
|
/***************** Bit definition for USB_COUNT1_RX register ****************/
|
| 5417 |
|
|
#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
|
| 5418 |
|
|
|
| 5419 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 5420 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 5421 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 5422 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
|
| 5423 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
|
| 5424 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
|
| 5425 |
|
|
|
| 5426 |
|
|
#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
|
| 5427 |
|
|
|
| 5428 |
|
|
/***************** Bit definition for USB_COUNT2_RX register ****************/
|
| 5429 |
|
|
#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
|
| 5430 |
|
|
|
| 5431 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 5432 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 5433 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 5434 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
|
| 5435 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
|
| 5436 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
|
| 5437 |
|
|
|
| 5438 |
|
|
#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
|
| 5439 |
|
|
|
| 5440 |
|
|
/***************** Bit definition for USB_COUNT3_RX register ****************/
|
| 5441 |
|
|
#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
|
| 5442 |
|
|
|
| 5443 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 5444 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 5445 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 5446 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
|
| 5447 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
|
| 5448 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
|
| 5449 |
|
|
|
| 5450 |
|
|
#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
|
| 5451 |
|
|
|
| 5452 |
|
|
/***************** Bit definition for USB_COUNT4_RX register ****************/
|
| 5453 |
|
|
#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
|
| 5454 |
|
|
|
| 5455 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 5456 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 5457 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 5458 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
|
| 5459 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
|
| 5460 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
|
| 5461 |
|
|
|
| 5462 |
|
|
#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
|
| 5463 |
|
|
|
| 5464 |
|
|
/***************** Bit definition for USB_COUNT5_RX register ****************/
|
| 5465 |
|
|
#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
|
| 5466 |
|
|
|
| 5467 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 5468 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 5469 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 5470 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
|
| 5471 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
|
| 5472 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
|
| 5473 |
|
|
|
| 5474 |
|
|
#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
|
| 5475 |
|
|
|
| 5476 |
|
|
/***************** Bit definition for USB_COUNT6_RX register ****************/
|
| 5477 |
|
|
#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
|
| 5478 |
|
|
|
| 5479 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 5480 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 5481 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 5482 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
|
| 5483 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
|
| 5484 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
|
| 5485 |
|
|
|
| 5486 |
|
|
#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
|
| 5487 |
|
|
|
| 5488 |
|
|
/***************** Bit definition for USB_COUNT7_RX register ****************/
|
| 5489 |
|
|
#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
|
| 5490 |
|
|
|
| 5491 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 5492 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 5493 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 5494 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
|
| 5495 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
|
| 5496 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
|
| 5497 |
|
|
|
| 5498 |
|
|
#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
|
| 5499 |
|
|
|
| 5500 |
|
|
/*----------------------------------------------------------------------------*/
|
| 5501 |
|
|
|
| 5502 |
|
|
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
|
| 5503 |
|
|
#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
|
| 5504 |
|
|
|
| 5505 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 5506 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 5507 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 5508 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 5509 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 5510 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 5511 |
|
|
|
| 5512 |
|
|
#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
|
| 5513 |
|
|
|
| 5514 |
|
|
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
|
| 5515 |
|
|
#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
|
| 5516 |
|
|
|
| 5517 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 5518 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */
|
| 5519 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
|
| 5520 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
|
| 5521 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
|
| 5522 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
|
| 5523 |
|
|
|
| 5524 |
|
|
#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
|
| 5525 |
|
|
|
| 5526 |
|
|
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
|
| 5527 |
|
|
#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
|
| 5528 |
|
|
|
| 5529 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 5530 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 5531 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 5532 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 5533 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 5534 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 5535 |
|
|
|
| 5536 |
|
|
#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
|
| 5537 |
|
|
|
| 5538 |
|
|
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
|
| 5539 |
|
|
#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
|
| 5540 |
|
|
|
| 5541 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 5542 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
|
| 5543 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
|
| 5544 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
|
| 5545 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
|
| 5546 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
|
| 5547 |
|
|
|
| 5548 |
|
|
#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
|
| 5549 |
|
|
|
| 5550 |
|
|
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
|
| 5551 |
|
|
#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
|
| 5552 |
|
|
|
| 5553 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 5554 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 5555 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 5556 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 5557 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 5558 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 5559 |
|
|
|
| 5560 |
|
|
#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
|
| 5561 |
|
|
|
| 5562 |
|
|
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
|
| 5563 |
|
|
#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
|
| 5564 |
|
|
|
| 5565 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 5566 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
|
| 5567 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
|
| 5568 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
|
| 5569 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
|
| 5570 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
|
| 5571 |
|
|
|
| 5572 |
|
|
#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
|
| 5573 |
|
|
|
| 5574 |
|
|
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
|
| 5575 |
|
|
#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
|
| 5576 |
|
|
|
| 5577 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 5578 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 5579 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 5580 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 5581 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 5582 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 5583 |
|
|
|
| 5584 |
|
|
#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
|
| 5585 |
|
|
|
| 5586 |
|
|
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
|
| 5587 |
|
|
#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
|
| 5588 |
|
|
|
| 5589 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 5590 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
|
| 5591 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
|
| 5592 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
|
| 5593 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
|
| 5594 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
|
| 5595 |
|
|
|
| 5596 |
|
|
#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
|
| 5597 |
|
|
|
| 5598 |
|
|
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
|
| 5599 |
|
|
#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
|
| 5600 |
|
|
|
| 5601 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 5602 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 5603 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 5604 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 5605 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 5606 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 5607 |
|
|
|
| 5608 |
|
|
#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
|
| 5609 |
|
|
|
| 5610 |
|
|
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
|
| 5611 |
|
|
#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
|
| 5612 |
|
|
|
| 5613 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 5614 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
|
| 5615 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
|
| 5616 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
|
| 5617 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
|
| 5618 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
|
| 5619 |
|
|
|
| 5620 |
|
|
#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
|
| 5621 |
|
|
|
| 5622 |
|
|
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
|
| 5623 |
|
|
#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
|
| 5624 |
|
|
|
| 5625 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 5626 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 5627 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 5628 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 5629 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 5630 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 5631 |
|
|
|
| 5632 |
|
|
#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
|
| 5633 |
|
|
|
| 5634 |
|
|
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
|
| 5635 |
|
|
#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
|
| 5636 |
|
|
|
| 5637 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 5638 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
|
| 5639 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
|
| 5640 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
|
| 5641 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
|
| 5642 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
|
| 5643 |
|
|
|
| 5644 |
|
|
#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
|
| 5645 |
|
|
|
| 5646 |
|
|
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
|
| 5647 |
|
|
#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
|
| 5648 |
|
|
|
| 5649 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 5650 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 5651 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 5652 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 5653 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 5654 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 5655 |
|
|
|
| 5656 |
|
|
#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
|
| 5657 |
|
|
|
| 5658 |
|
|
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
|
| 5659 |
|
|
#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
|
| 5660 |
|
|
|
| 5661 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 5662 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
|
| 5663 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
|
| 5664 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
|
| 5665 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
|
| 5666 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
|
| 5667 |
|
|
|
| 5668 |
|
|
#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
|
| 5669 |
|
|
|
| 5670 |
|
|
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
|
| 5671 |
|
|
#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
|
| 5672 |
|
|
|
| 5673 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 5674 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
| 5675 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
| 5676 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
| 5677 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
| 5678 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
| 5679 |
|
|
|
| 5680 |
|
|
#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
|
| 5681 |
|
|
|
| 5682 |
|
|
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
|
| 5683 |
|
|
#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
|
| 5684 |
|
|
|
| 5685 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 5686 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
|
| 5687 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
|
| 5688 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
|
| 5689 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
|
| 5690 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
|
| 5691 |
|
|
|
| 5692 |
|
|
#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
|
| 5693 |
|
|
|
| 5694 |
|
|
/******************************************************************************/
|
| 5695 |
|
|
/* */
|
| 5696 |
|
|
/* Controller Area Network */
|
| 5697 |
|
|
/* */
|
| 5698 |
|
|
/******************************************************************************/
|
| 5699 |
|
|
|
| 5700 |
|
|
/*!<CAN control and status registers */
|
| 5701 |
|
|
/******************* Bit definition for CAN_MCR register ********************/
|
| 5702 |
|
|
#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
|
| 5703 |
|
|
#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
|
| 5704 |
|
|
#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
|
| 5705 |
|
|
#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
|
| 5706 |
|
|
#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
|
| 5707 |
|
|
#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
|
| 5708 |
|
|
#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
|
| 5709 |
|
|
#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
|
| 5710 |
|
|
#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
|
| 5711 |
|
|
|
| 5712 |
|
|
/******************* Bit definition for CAN_MSR register ********************/
|
| 5713 |
|
|
#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
|
| 5714 |
|
|
#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
|
| 5715 |
|
|
#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
|
| 5716 |
|
|
#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
|
| 5717 |
|
|
#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
|
| 5718 |
|
|
#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
|
| 5719 |
|
|
#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
|
| 5720 |
|
|
#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
|
| 5721 |
|
|
#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
|
| 5722 |
|
|
|
| 5723 |
|
|
/******************* Bit definition for CAN_TSR register ********************/
|
| 5724 |
|
|
#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
|
| 5725 |
|
|
#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
|
| 5726 |
|
|
#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
|
| 5727 |
|
|
#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
|
| 5728 |
|
|
#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
|
| 5729 |
|
|
#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
|
| 5730 |
|
|
#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
|
| 5731 |
|
|
#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
|
| 5732 |
|
|
#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
|
| 5733 |
|
|
#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
|
| 5734 |
|
|
#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
|
| 5735 |
|
|
#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
|
| 5736 |
|
|
#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
|
| 5737 |
|
|
#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
|
| 5738 |
|
|
#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
|
| 5739 |
|
|
#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
|
| 5740 |
|
|
|
| 5741 |
|
|
#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
|
| 5742 |
|
|
#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
|
| 5743 |
|
|
#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
|
| 5744 |
|
|
#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
|
| 5745 |
|
|
|
| 5746 |
|
|
#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
|
| 5747 |
|
|
#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
|
| 5748 |
|
|
#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
|
| 5749 |
|
|
#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
|
| 5750 |
|
|
|
| 5751 |
|
|
/******************* Bit definition for CAN_RF0R register *******************/
|
| 5752 |
|
|
#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
|
| 5753 |
|
|
#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
|
| 5754 |
|
|
#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
|
| 5755 |
|
|
#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
|
| 5756 |
|
|
|
| 5757 |
|
|
/******************* Bit definition for CAN_RF1R register *******************/
|
| 5758 |
|
|
#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
|
| 5759 |
|
|
#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
|
| 5760 |
|
|
#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
|
| 5761 |
|
|
#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
|
| 5762 |
|
|
|
| 5763 |
|
|
/******************** Bit definition for CAN_IER register *******************/
|
| 5764 |
|
|
#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
|
| 5765 |
|
|
#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
|
| 5766 |
|
|
#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
|
| 5767 |
|
|
#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
|
| 5768 |
|
|
#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
|
| 5769 |
|
|
#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
|
| 5770 |
|
|
#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
|
| 5771 |
|
|
#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
|
| 5772 |
|
|
#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
|
| 5773 |
|
|
#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
|
| 5774 |
|
|
#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
|
| 5775 |
|
|
#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
|
| 5776 |
|
|
#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
|
| 5777 |
|
|
#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
|
| 5778 |
|
|
|
| 5779 |
|
|
/******************** Bit definition for CAN_ESR register *******************/
|
| 5780 |
|
|
#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
|
| 5781 |
|
|
#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
|
| 5782 |
|
|
#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
|
| 5783 |
|
|
|
| 5784 |
|
|
#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
|
| 5785 |
|
|
#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
| 5786 |
|
|
#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
| 5787 |
|
|
#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
| 5788 |
|
|
|
| 5789 |
|
|
#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
|
| 5790 |
|
|
#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
|
| 5791 |
|
|
|
| 5792 |
|
|
/******************* Bit definition for CAN_BTR register ********************/
|
| 5793 |
|
|
#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
|
| 5794 |
|
|
#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
|
| 5795 |
|
|
#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
|
| 5796 |
|
|
#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
|
| 5797 |
|
|
#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
|
| 5798 |
|
|
#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
|
| 5799 |
|
|
|
| 5800 |
|
|
/*!<Mailbox registers */
|
| 5801 |
|
|
/****************** Bit definition for CAN_TI0R register ********************/
|
| 5802 |
|
|
#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
| 5803 |
|
|
#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
| 5804 |
|
|
#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
| 5805 |
|
|
#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
| 5806 |
|
|
#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
| 5807 |
|
|
|
| 5808 |
|
|
/****************** Bit definition for CAN_TDT0R register *******************/
|
| 5809 |
|
|
#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
| 5810 |
|
|
#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
| 5811 |
|
|
#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
| 5812 |
|
|
|
| 5813 |
|
|
/****************** Bit definition for CAN_TDL0R register *******************/
|
| 5814 |
|
|
#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
| 5815 |
|
|
#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
| 5816 |
|
|
#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
| 5817 |
|
|
#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
| 5818 |
|
|
|
| 5819 |
|
|
/****************** Bit definition for CAN_TDH0R register *******************/
|
| 5820 |
|
|
#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
| 5821 |
|
|
#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
| 5822 |
|
|
#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
| 5823 |
|
|
#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
| 5824 |
|
|
|
| 5825 |
|
|
/******************* Bit definition for CAN_TI1R register *******************/
|
| 5826 |
|
|
#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
| 5827 |
|
|
#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
| 5828 |
|
|
#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
| 5829 |
|
|
#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
| 5830 |
|
|
#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
| 5831 |
|
|
|
| 5832 |
|
|
/******************* Bit definition for CAN_TDT1R register ******************/
|
| 5833 |
|
|
#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
| 5834 |
|
|
#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
| 5835 |
|
|
#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
| 5836 |
|
|
|
| 5837 |
|
|
/******************* Bit definition for CAN_TDL1R register ******************/
|
| 5838 |
|
|
#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
| 5839 |
|
|
#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
| 5840 |
|
|
#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
| 5841 |
|
|
#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
| 5842 |
|
|
|
| 5843 |
|
|
/******************* Bit definition for CAN_TDH1R register ******************/
|
| 5844 |
|
|
#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
| 5845 |
|
|
#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
| 5846 |
|
|
#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
| 5847 |
|
|
#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
| 5848 |
|
|
|
| 5849 |
|
|
/******************* Bit definition for CAN_TI2R register *******************/
|
| 5850 |
|
|
#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
| 5851 |
|
|
#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
| 5852 |
|
|
#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
| 5853 |
|
|
#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
|
| 5854 |
|
|
#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
| 5855 |
|
|
|
| 5856 |
|
|
/******************* Bit definition for CAN_TDT2R register ******************/
|
| 5857 |
|
|
#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
| 5858 |
|
|
#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
| 5859 |
|
|
#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
| 5860 |
|
|
|
| 5861 |
|
|
/******************* Bit definition for CAN_TDL2R register ******************/
|
| 5862 |
|
|
#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
| 5863 |
|
|
#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
| 5864 |
|
|
#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
| 5865 |
|
|
#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
| 5866 |
|
|
|
| 5867 |
|
|
/******************* Bit definition for CAN_TDH2R register ******************/
|
| 5868 |
|
|
#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
| 5869 |
|
|
#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
| 5870 |
|
|
#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
| 5871 |
|
|
#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
| 5872 |
|
|
|
| 5873 |
|
|
/******************* Bit definition for CAN_RI0R register *******************/
|
| 5874 |
|
|
#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
| 5875 |
|
|
#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
| 5876 |
|
|
#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
| 5877 |
|
|
#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
| 5878 |
|
|
|
| 5879 |
|
|
/******************* Bit definition for CAN_RDT0R register ******************/
|
| 5880 |
|
|
#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
| 5881 |
|
|
#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
|
| 5882 |
|
|
#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
| 5883 |
|
|
|
| 5884 |
|
|
/******************* Bit definition for CAN_RDL0R register ******************/
|
| 5885 |
|
|
#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
| 5886 |
|
|
#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
| 5887 |
|
|
#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
| 5888 |
|
|
#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
| 5889 |
|
|
|
| 5890 |
|
|
/******************* Bit definition for CAN_RDH0R register ******************/
|
| 5891 |
|
|
#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
| 5892 |
|
|
#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
| 5893 |
|
|
#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
| 5894 |
|
|
#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
| 5895 |
|
|
|
| 5896 |
|
|
/******************* Bit definition for CAN_RI1R register *******************/
|
| 5897 |
|
|
#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
| 5898 |
|
|
#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
| 5899 |
|
|
#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
|
| 5900 |
|
|
#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
| 5901 |
|
|
|
| 5902 |
|
|
/******************* Bit definition for CAN_RDT1R register ******************/
|
| 5903 |
|
|
#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
| 5904 |
|
|
#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
|
| 5905 |
|
|
#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
| 5906 |
|
|
|
| 5907 |
|
|
/******************* Bit definition for CAN_RDL1R register ******************/
|
| 5908 |
|
|
#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
| 5909 |
|
|
#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
| 5910 |
|
|
#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
| 5911 |
|
|
#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
| 5912 |
|
|
|
| 5913 |
|
|
/******************* Bit definition for CAN_RDH1R register ******************/
|
| 5914 |
|
|
#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
| 5915 |
|
|
#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
| 5916 |
|
|
#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
| 5917 |
|
|
#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
| 5918 |
|
|
|
| 5919 |
|
|
/*!<CAN filter registers */
|
| 5920 |
|
|
/******************* Bit definition for CAN_FMR register ********************/
|
| 5921 |
|
|
#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
|
| 5922 |
|
|
|
| 5923 |
|
|
/******************* Bit definition for CAN_FM1R register *******************/
|
| 5924 |
|
|
#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
|
| 5925 |
|
|
#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
|
| 5926 |
|
|
#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
|
| 5927 |
|
|
#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
|
| 5928 |
|
|
#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
|
| 5929 |
|
|
#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
|
| 5930 |
|
|
#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
|
| 5931 |
|
|
#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
|
| 5932 |
|
|
#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
|
| 5933 |
|
|
#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
|
| 5934 |
|
|
#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
|
| 5935 |
|
|
#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
|
| 5936 |
|
|
#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
|
| 5937 |
|
|
#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
|
| 5938 |
|
|
#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
|
| 5939 |
|
|
|
| 5940 |
|
|
/******************* Bit definition for CAN_FS1R register *******************/
|
| 5941 |
|
|
#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
|
| 5942 |
|
|
#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
|
| 5943 |
|
|
#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
|
| 5944 |
|
|
#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
|
| 5945 |
|
|
#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
|
| 5946 |
|
|
#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
|
| 5947 |
|
|
#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
|
| 5948 |
|
|
#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
|
| 5949 |
|
|
#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
|
| 5950 |
|
|
#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
|
| 5951 |
|
|
#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
|
| 5952 |
|
|
#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
|
| 5953 |
|
|
#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
|
| 5954 |
|
|
#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
|
| 5955 |
|
|
#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
|
| 5956 |
|
|
|
| 5957 |
|
|
/****************** Bit definition for CAN_FFA1R register *******************/
|
| 5958 |
|
|
#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
|
| 5959 |
|
|
#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
|
| 5960 |
|
|
#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
|
| 5961 |
|
|
#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
|
| 5962 |
|
|
#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
|
| 5963 |
|
|
#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
|
| 5964 |
|
|
#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
|
| 5965 |
|
|
#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
|
| 5966 |
|
|
#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
|
| 5967 |
|
|
#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
|
| 5968 |
|
|
#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
|
| 5969 |
|
|
#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
|
| 5970 |
|
|
#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
|
| 5971 |
|
|
#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
|
| 5972 |
|
|
#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
|
| 5973 |
|
|
|
| 5974 |
|
|
/******************* Bit definition for CAN_FA1R register *******************/
|
| 5975 |
|
|
#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
|
| 5976 |
|
|
#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
|
| 5977 |
|
|
#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
|
| 5978 |
|
|
#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
|
| 5979 |
|
|
#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
|
| 5980 |
|
|
#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
|
| 5981 |
|
|
#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
|
| 5982 |
|
|
#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
|
| 5983 |
|
|
#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
|
| 5984 |
|
|
#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
|
| 5985 |
|
|
#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
|
| 5986 |
|
|
#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
|
| 5987 |
|
|
#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
|
| 5988 |
|
|
#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
|
| 5989 |
|
|
#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
|
| 5990 |
|
|
|
| 5991 |
|
|
/******************* Bit definition for CAN_F0R1 register *******************/
|
| 5992 |
|
|
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 5993 |
|
|
#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 5994 |
|
|
#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 5995 |
|
|
#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 5996 |
|
|
#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 5997 |
|
|
#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 5998 |
|
|
#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 5999 |
|
|
#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6000 |
|
|
#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6001 |
|
|
#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6002 |
|
|
#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6003 |
|
|
#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6004 |
|
|
#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6005 |
|
|
#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6006 |
|
|
#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6007 |
|
|
#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6008 |
|
|
#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6009 |
|
|
#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6010 |
|
|
#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6011 |
|
|
#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6012 |
|
|
#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6013 |
|
|
#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6014 |
|
|
#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6015 |
|
|
#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6016 |
|
|
#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6017 |
|
|
#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6018 |
|
|
#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6019 |
|
|
#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6020 |
|
|
#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6021 |
|
|
#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6022 |
|
|
#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6023 |
|
|
#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6024 |
|
|
|
| 6025 |
|
|
/******************* Bit definition for CAN_F1R1 register *******************/
|
| 6026 |
|
|
#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6027 |
|
|
#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6028 |
|
|
#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6029 |
|
|
#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6030 |
|
|
#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6031 |
|
|
#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6032 |
|
|
#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6033 |
|
|
#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6034 |
|
|
#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6035 |
|
|
#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6036 |
|
|
#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6037 |
|
|
#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6038 |
|
|
#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6039 |
|
|
#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6040 |
|
|
#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6041 |
|
|
#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6042 |
|
|
#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6043 |
|
|
#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6044 |
|
|
#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6045 |
|
|
#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6046 |
|
|
#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6047 |
|
|
#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6048 |
|
|
#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6049 |
|
|
#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6050 |
|
|
#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6051 |
|
|
#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6052 |
|
|
#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6053 |
|
|
#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6054 |
|
|
#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6055 |
|
|
#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6056 |
|
|
#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6057 |
|
|
#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6058 |
|
|
|
| 6059 |
|
|
/******************* Bit definition for CAN_F2R1 register *******************/
|
| 6060 |
|
|
#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6061 |
|
|
#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6062 |
|
|
#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6063 |
|
|
#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6064 |
|
|
#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6065 |
|
|
#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6066 |
|
|
#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6067 |
|
|
#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6068 |
|
|
#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6069 |
|
|
#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6070 |
|
|
#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6071 |
|
|
#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6072 |
|
|
#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6073 |
|
|
#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6074 |
|
|
#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6075 |
|
|
#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6076 |
|
|
#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6077 |
|
|
#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6078 |
|
|
#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6079 |
|
|
#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6080 |
|
|
#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6081 |
|
|
#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6082 |
|
|
#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6083 |
|
|
#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6084 |
|
|
#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6085 |
|
|
#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6086 |
|
|
#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6087 |
|
|
#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6088 |
|
|
#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6089 |
|
|
#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6090 |
|
|
#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6091 |
|
|
#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6092 |
|
|
|
| 6093 |
|
|
/******************* Bit definition for CAN_F3R1 register *******************/
|
| 6094 |
|
|
#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6095 |
|
|
#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6096 |
|
|
#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6097 |
|
|
#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6098 |
|
|
#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6099 |
|
|
#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6100 |
|
|
#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6101 |
|
|
#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6102 |
|
|
#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6103 |
|
|
#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6104 |
|
|
#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6105 |
|
|
#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6106 |
|
|
#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6107 |
|
|
#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6108 |
|
|
#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6109 |
|
|
#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6110 |
|
|
#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6111 |
|
|
#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6112 |
|
|
#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6113 |
|
|
#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6114 |
|
|
#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6115 |
|
|
#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6116 |
|
|
#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6117 |
|
|
#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6118 |
|
|
#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6119 |
|
|
#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6120 |
|
|
#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6121 |
|
|
#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6122 |
|
|
#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6123 |
|
|
#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6124 |
|
|
#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6125 |
|
|
#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6126 |
|
|
|
| 6127 |
|
|
/******************* Bit definition for CAN_F4R1 register *******************/
|
| 6128 |
|
|
#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6129 |
|
|
#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6130 |
|
|
#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6131 |
|
|
#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6132 |
|
|
#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6133 |
|
|
#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6134 |
|
|
#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6135 |
|
|
#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6136 |
|
|
#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6137 |
|
|
#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6138 |
|
|
#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6139 |
|
|
#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6140 |
|
|
#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6141 |
|
|
#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6142 |
|
|
#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6143 |
|
|
#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6144 |
|
|
#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6145 |
|
|
#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6146 |
|
|
#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6147 |
|
|
#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6148 |
|
|
#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6149 |
|
|
#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6150 |
|
|
#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6151 |
|
|
#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6152 |
|
|
#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6153 |
|
|
#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6154 |
|
|
#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6155 |
|
|
#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6156 |
|
|
#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6157 |
|
|
#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6158 |
|
|
#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6159 |
|
|
#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6160 |
|
|
|
| 6161 |
|
|
/******************* Bit definition for CAN_F5R1 register *******************/
|
| 6162 |
|
|
#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6163 |
|
|
#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6164 |
|
|
#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6165 |
|
|
#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6166 |
|
|
#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6167 |
|
|
#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6168 |
|
|
#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6169 |
|
|
#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6170 |
|
|
#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6171 |
|
|
#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6172 |
|
|
#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6173 |
|
|
#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6174 |
|
|
#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6175 |
|
|
#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6176 |
|
|
#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6177 |
|
|
#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6178 |
|
|
#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6179 |
|
|
#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6180 |
|
|
#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6181 |
|
|
#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6182 |
|
|
#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6183 |
|
|
#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6184 |
|
|
#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6185 |
|
|
#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6186 |
|
|
#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6187 |
|
|
#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6188 |
|
|
#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6189 |
|
|
#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6190 |
|
|
#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6191 |
|
|
#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6192 |
|
|
#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6193 |
|
|
#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6194 |
|
|
|
| 6195 |
|
|
/******************* Bit definition for CAN_F6R1 register *******************/
|
| 6196 |
|
|
#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6197 |
|
|
#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6198 |
|
|
#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6199 |
|
|
#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6200 |
|
|
#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6201 |
|
|
#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6202 |
|
|
#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6203 |
|
|
#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6204 |
|
|
#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6205 |
|
|
#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6206 |
|
|
#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6207 |
|
|
#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6208 |
|
|
#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6209 |
|
|
#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6210 |
|
|
#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6211 |
|
|
#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6212 |
|
|
#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6213 |
|
|
#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6214 |
|
|
#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6215 |
|
|
#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6216 |
|
|
#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6217 |
|
|
#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6218 |
|
|
#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6219 |
|
|
#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6220 |
|
|
#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6221 |
|
|
#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6222 |
|
|
#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6223 |
|
|
#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6224 |
|
|
#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6225 |
|
|
#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6226 |
|
|
#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6227 |
|
|
#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6228 |
|
|
|
| 6229 |
|
|
/******************* Bit definition for CAN_F7R1 register *******************/
|
| 6230 |
|
|
#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6231 |
|
|
#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6232 |
|
|
#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6233 |
|
|
#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6234 |
|
|
#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6235 |
|
|
#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6236 |
|
|
#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6237 |
|
|
#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6238 |
|
|
#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6239 |
|
|
#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6240 |
|
|
#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6241 |
|
|
#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6242 |
|
|
#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6243 |
|
|
#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6244 |
|
|
#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6245 |
|
|
#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6246 |
|
|
#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6247 |
|
|
#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6248 |
|
|
#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6249 |
|
|
#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6250 |
|
|
#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6251 |
|
|
#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6252 |
|
|
#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6253 |
|
|
#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6254 |
|
|
#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6255 |
|
|
#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6256 |
|
|
#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6257 |
|
|
#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6258 |
|
|
#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6259 |
|
|
#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6260 |
|
|
#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6261 |
|
|
#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6262 |
|
|
|
| 6263 |
|
|
/******************* Bit definition for CAN_F8R1 register *******************/
|
| 6264 |
|
|
#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6265 |
|
|
#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6266 |
|
|
#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6267 |
|
|
#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6268 |
|
|
#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6269 |
|
|
#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6270 |
|
|
#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6271 |
|
|
#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6272 |
|
|
#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6273 |
|
|
#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6274 |
|
|
#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6275 |
|
|
#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6276 |
|
|
#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6277 |
|
|
#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6278 |
|
|
#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6279 |
|
|
#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6280 |
|
|
#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6281 |
|
|
#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6282 |
|
|
#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6283 |
|
|
#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6284 |
|
|
#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6285 |
|
|
#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6286 |
|
|
#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6287 |
|
|
#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6288 |
|
|
#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6289 |
|
|
#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6290 |
|
|
#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6291 |
|
|
#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6292 |
|
|
#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6293 |
|
|
#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6294 |
|
|
#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6295 |
|
|
#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6296 |
|
|
|
| 6297 |
|
|
/******************* Bit definition for CAN_F9R1 register *******************/
|
| 6298 |
|
|
#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6299 |
|
|
#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6300 |
|
|
#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6301 |
|
|
#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6302 |
|
|
#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6303 |
|
|
#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6304 |
|
|
#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6305 |
|
|
#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6306 |
|
|
#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6307 |
|
|
#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6308 |
|
|
#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6309 |
|
|
#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6310 |
|
|
#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6311 |
|
|
#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6312 |
|
|
#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6313 |
|
|
#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6314 |
|
|
#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6315 |
|
|
#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6316 |
|
|
#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6317 |
|
|
#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6318 |
|
|
#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6319 |
|
|
#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6320 |
|
|
#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6321 |
|
|
#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6322 |
|
|
#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6323 |
|
|
#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6324 |
|
|
#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6325 |
|
|
#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6326 |
|
|
#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6327 |
|
|
#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6328 |
|
|
#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6329 |
|
|
#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6330 |
|
|
|
| 6331 |
|
|
/******************* Bit definition for CAN_F10R1 register ******************/
|
| 6332 |
|
|
#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6333 |
|
|
#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6334 |
|
|
#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6335 |
|
|
#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6336 |
|
|
#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6337 |
|
|
#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6338 |
|
|
#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6339 |
|
|
#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6340 |
|
|
#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6341 |
|
|
#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6342 |
|
|
#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6343 |
|
|
#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6344 |
|
|
#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6345 |
|
|
#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6346 |
|
|
#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6347 |
|
|
#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6348 |
|
|
#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6349 |
|
|
#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6350 |
|
|
#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6351 |
|
|
#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6352 |
|
|
#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6353 |
|
|
#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6354 |
|
|
#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6355 |
|
|
#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6356 |
|
|
#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6357 |
|
|
#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6358 |
|
|
#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6359 |
|
|
#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6360 |
|
|
#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6361 |
|
|
#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6362 |
|
|
#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6363 |
|
|
#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6364 |
|
|
|
| 6365 |
|
|
/******************* Bit definition for CAN_F11R1 register ******************/
|
| 6366 |
|
|
#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6367 |
|
|
#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6368 |
|
|
#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6369 |
|
|
#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6370 |
|
|
#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6371 |
|
|
#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6372 |
|
|
#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6373 |
|
|
#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6374 |
|
|
#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6375 |
|
|
#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6376 |
|
|
#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6377 |
|
|
#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6378 |
|
|
#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6379 |
|
|
#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6380 |
|
|
#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6381 |
|
|
#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6382 |
|
|
#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6383 |
|
|
#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6384 |
|
|
#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6385 |
|
|
#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6386 |
|
|
#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6387 |
|
|
#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6388 |
|
|
#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6389 |
|
|
#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6390 |
|
|
#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6391 |
|
|
#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6392 |
|
|
#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6393 |
|
|
#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6394 |
|
|
#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6395 |
|
|
#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6396 |
|
|
#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6397 |
|
|
#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6398 |
|
|
|
| 6399 |
|
|
/******************* Bit definition for CAN_F12R1 register ******************/
|
| 6400 |
|
|
#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6401 |
|
|
#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6402 |
|
|
#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6403 |
|
|
#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6404 |
|
|
#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6405 |
|
|
#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6406 |
|
|
#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6407 |
|
|
#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6408 |
|
|
#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6409 |
|
|
#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6410 |
|
|
#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6411 |
|
|
#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6412 |
|
|
#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6413 |
|
|
#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6414 |
|
|
#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6415 |
|
|
#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6416 |
|
|
#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6417 |
|
|
#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6418 |
|
|
#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6419 |
|
|
#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6420 |
|
|
#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6421 |
|
|
#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6422 |
|
|
#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6423 |
|
|
#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6424 |
|
|
#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6425 |
|
|
#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6426 |
|
|
#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6427 |
|
|
#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6428 |
|
|
#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6429 |
|
|
#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6430 |
|
|
#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6431 |
|
|
#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6432 |
|
|
|
| 6433 |
|
|
/******************* Bit definition for CAN_F13R1 register ******************/
|
| 6434 |
|
|
#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6435 |
|
|
#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6436 |
|
|
#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6437 |
|
|
#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6438 |
|
|
#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6439 |
|
|
#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6440 |
|
|
#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6441 |
|
|
#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6442 |
|
|
#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6443 |
|
|
#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6444 |
|
|
#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6445 |
|
|
#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6446 |
|
|
#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6447 |
|
|
#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6448 |
|
|
#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6449 |
|
|
#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6450 |
|
|
#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6451 |
|
|
#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6452 |
|
|
#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6453 |
|
|
#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6454 |
|
|
#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6455 |
|
|
#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6456 |
|
|
#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6457 |
|
|
#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6458 |
|
|
#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6459 |
|
|
#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6460 |
|
|
#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6461 |
|
|
#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6462 |
|
|
#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6463 |
|
|
#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6464 |
|
|
#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6465 |
|
|
#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6466 |
|
|
|
| 6467 |
|
|
/******************* Bit definition for CAN_F0R2 register *******************/
|
| 6468 |
|
|
#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6469 |
|
|
#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6470 |
|
|
#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6471 |
|
|
#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6472 |
|
|
#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6473 |
|
|
#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6474 |
|
|
#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6475 |
|
|
#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6476 |
|
|
#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6477 |
|
|
#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6478 |
|
|
#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6479 |
|
|
#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6480 |
|
|
#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6481 |
|
|
#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6482 |
|
|
#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6483 |
|
|
#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6484 |
|
|
#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6485 |
|
|
#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6486 |
|
|
#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6487 |
|
|
#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6488 |
|
|
#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6489 |
|
|
#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6490 |
|
|
#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6491 |
|
|
#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6492 |
|
|
#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6493 |
|
|
#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6494 |
|
|
#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6495 |
|
|
#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6496 |
|
|
#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6497 |
|
|
#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6498 |
|
|
#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6499 |
|
|
#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6500 |
|
|
|
| 6501 |
|
|
/******************* Bit definition for CAN_F1R2 register *******************/
|
| 6502 |
|
|
#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6503 |
|
|
#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6504 |
|
|
#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6505 |
|
|
#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6506 |
|
|
#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6507 |
|
|
#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6508 |
|
|
#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6509 |
|
|
#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6510 |
|
|
#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6511 |
|
|
#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6512 |
|
|
#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6513 |
|
|
#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6514 |
|
|
#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6515 |
|
|
#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6516 |
|
|
#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6517 |
|
|
#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6518 |
|
|
#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6519 |
|
|
#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6520 |
|
|
#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6521 |
|
|
#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6522 |
|
|
#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6523 |
|
|
#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6524 |
|
|
#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6525 |
|
|
#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6526 |
|
|
#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6527 |
|
|
#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6528 |
|
|
#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6529 |
|
|
#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6530 |
|
|
#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6531 |
|
|
#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6532 |
|
|
#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6533 |
|
|
#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6534 |
|
|
|
| 6535 |
|
|
/******************* Bit definition for CAN_F2R2 register *******************/
|
| 6536 |
|
|
#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6537 |
|
|
#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6538 |
|
|
#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6539 |
|
|
#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6540 |
|
|
#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6541 |
|
|
#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6542 |
|
|
#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6543 |
|
|
#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6544 |
|
|
#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6545 |
|
|
#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6546 |
|
|
#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6547 |
|
|
#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6548 |
|
|
#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6549 |
|
|
#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6550 |
|
|
#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6551 |
|
|
#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6552 |
|
|
#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6553 |
|
|
#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6554 |
|
|
#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6555 |
|
|
#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6556 |
|
|
#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6557 |
|
|
#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6558 |
|
|
#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6559 |
|
|
#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6560 |
|
|
#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6561 |
|
|
#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6562 |
|
|
#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6563 |
|
|
#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6564 |
|
|
#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6565 |
|
|
#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6566 |
|
|
#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6567 |
|
|
#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6568 |
|
|
|
| 6569 |
|
|
/******************* Bit definition for CAN_F3R2 register *******************/
|
| 6570 |
|
|
#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6571 |
|
|
#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6572 |
|
|
#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6573 |
|
|
#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6574 |
|
|
#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6575 |
|
|
#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6576 |
|
|
#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6577 |
|
|
#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6578 |
|
|
#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6579 |
|
|
#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6580 |
|
|
#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6581 |
|
|
#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6582 |
|
|
#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6583 |
|
|
#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6584 |
|
|
#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6585 |
|
|
#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6586 |
|
|
#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6587 |
|
|
#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6588 |
|
|
#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6589 |
|
|
#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6590 |
|
|
#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6591 |
|
|
#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6592 |
|
|
#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6593 |
|
|
#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6594 |
|
|
#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6595 |
|
|
#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6596 |
|
|
#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6597 |
|
|
#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6598 |
|
|
#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6599 |
|
|
#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6600 |
|
|
#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6601 |
|
|
#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6602 |
|
|
|
| 6603 |
|
|
/******************* Bit definition for CAN_F4R2 register *******************/
|
| 6604 |
|
|
#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6605 |
|
|
#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6606 |
|
|
#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6607 |
|
|
#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6608 |
|
|
#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6609 |
|
|
#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6610 |
|
|
#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6611 |
|
|
#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6612 |
|
|
#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6613 |
|
|
#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6614 |
|
|
#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6615 |
|
|
#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6616 |
|
|
#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6617 |
|
|
#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6618 |
|
|
#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6619 |
|
|
#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6620 |
|
|
#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6621 |
|
|
#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6622 |
|
|
#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6623 |
|
|
#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6624 |
|
|
#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6625 |
|
|
#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6626 |
|
|
#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6627 |
|
|
#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6628 |
|
|
#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6629 |
|
|
#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6630 |
|
|
#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6631 |
|
|
#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6632 |
|
|
#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6633 |
|
|
#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6634 |
|
|
#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6635 |
|
|
#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6636 |
|
|
|
| 6637 |
|
|
/******************* Bit definition for CAN_F5R2 register *******************/
|
| 6638 |
|
|
#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6639 |
|
|
#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6640 |
|
|
#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6641 |
|
|
#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6642 |
|
|
#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6643 |
|
|
#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6644 |
|
|
#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6645 |
|
|
#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6646 |
|
|
#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6647 |
|
|
#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6648 |
|
|
#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6649 |
|
|
#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6650 |
|
|
#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6651 |
|
|
#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6652 |
|
|
#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6653 |
|
|
#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6654 |
|
|
#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6655 |
|
|
#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6656 |
|
|
#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6657 |
|
|
#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6658 |
|
|
#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6659 |
|
|
#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6660 |
|
|
#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6661 |
|
|
#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6662 |
|
|
#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6663 |
|
|
#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6664 |
|
|
#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6665 |
|
|
#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6666 |
|
|
#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6667 |
|
|
#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6668 |
|
|
#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6669 |
|
|
#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6670 |
|
|
|
| 6671 |
|
|
/******************* Bit definition for CAN_F6R2 register *******************/
|
| 6672 |
|
|
#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6673 |
|
|
#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6674 |
|
|
#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6675 |
|
|
#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6676 |
|
|
#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6677 |
|
|
#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6678 |
|
|
#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6679 |
|
|
#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6680 |
|
|
#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6681 |
|
|
#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6682 |
|
|
#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6683 |
|
|
#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6684 |
|
|
#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6685 |
|
|
#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6686 |
|
|
#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6687 |
|
|
#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6688 |
|
|
#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6689 |
|
|
#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6690 |
|
|
#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6691 |
|
|
#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6692 |
|
|
#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6693 |
|
|
#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6694 |
|
|
#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6695 |
|
|
#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6696 |
|
|
#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6697 |
|
|
#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6698 |
|
|
#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6699 |
|
|
#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6700 |
|
|
#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6701 |
|
|
#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6702 |
|
|
#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6703 |
|
|
#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6704 |
|
|
|
| 6705 |
|
|
/******************* Bit definition for CAN_F7R2 register *******************/
|
| 6706 |
|
|
#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6707 |
|
|
#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6708 |
|
|
#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6709 |
|
|
#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6710 |
|
|
#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6711 |
|
|
#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6712 |
|
|
#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6713 |
|
|
#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6714 |
|
|
#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6715 |
|
|
#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6716 |
|
|
#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6717 |
|
|
#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6718 |
|
|
#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6719 |
|
|
#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6720 |
|
|
#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6721 |
|
|
#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6722 |
|
|
#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6723 |
|
|
#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6724 |
|
|
#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6725 |
|
|
#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6726 |
|
|
#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6727 |
|
|
#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6728 |
|
|
#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6729 |
|
|
#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6730 |
|
|
#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6731 |
|
|
#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6732 |
|
|
#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6733 |
|
|
#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6734 |
|
|
#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6735 |
|
|
#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6736 |
|
|
#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6737 |
|
|
#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6738 |
|
|
|
| 6739 |
|
|
/******************* Bit definition for CAN_F8R2 register *******************/
|
| 6740 |
|
|
#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6741 |
|
|
#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6742 |
|
|
#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6743 |
|
|
#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6744 |
|
|
#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6745 |
|
|
#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6746 |
|
|
#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6747 |
|
|
#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6748 |
|
|
#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6749 |
|
|
#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6750 |
|
|
#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6751 |
|
|
#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6752 |
|
|
#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6753 |
|
|
#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6754 |
|
|
#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6755 |
|
|
#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6756 |
|
|
#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6757 |
|
|
#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6758 |
|
|
#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6759 |
|
|
#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6760 |
|
|
#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6761 |
|
|
#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6762 |
|
|
#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6763 |
|
|
#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6764 |
|
|
#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6765 |
|
|
#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6766 |
|
|
#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6767 |
|
|
#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6768 |
|
|
#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6769 |
|
|
#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6770 |
|
|
#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6771 |
|
|
#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6772 |
|
|
|
| 6773 |
|
|
/******************* Bit definition for CAN_F9R2 register *******************/
|
| 6774 |
|
|
#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6775 |
|
|
#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6776 |
|
|
#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6777 |
|
|
#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6778 |
|
|
#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6779 |
|
|
#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6780 |
|
|
#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6781 |
|
|
#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6782 |
|
|
#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6783 |
|
|
#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6784 |
|
|
#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6785 |
|
|
#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6786 |
|
|
#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6787 |
|
|
#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6788 |
|
|
#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6789 |
|
|
#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6790 |
|
|
#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6791 |
|
|
#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6792 |
|
|
#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6793 |
|
|
#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6794 |
|
|
#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6795 |
|
|
#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6796 |
|
|
#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6797 |
|
|
#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6798 |
|
|
#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6799 |
|
|
#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6800 |
|
|
#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6801 |
|
|
#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6802 |
|
|
#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6803 |
|
|
#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6804 |
|
|
#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6805 |
|
|
#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6806 |
|
|
|
| 6807 |
|
|
/******************* Bit definition for CAN_F10R2 register ******************/
|
| 6808 |
|
|
#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6809 |
|
|
#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6810 |
|
|
#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6811 |
|
|
#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6812 |
|
|
#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6813 |
|
|
#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6814 |
|
|
#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6815 |
|
|
#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6816 |
|
|
#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6817 |
|
|
#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6818 |
|
|
#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6819 |
|
|
#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6820 |
|
|
#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6821 |
|
|
#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6822 |
|
|
#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6823 |
|
|
#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6824 |
|
|
#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6825 |
|
|
#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6826 |
|
|
#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6827 |
|
|
#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6828 |
|
|
#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6829 |
|
|
#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6830 |
|
|
#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6831 |
|
|
#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6832 |
|
|
#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6833 |
|
|
#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6834 |
|
|
#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6835 |
|
|
#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6836 |
|
|
#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6837 |
|
|
#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6838 |
|
|
#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6839 |
|
|
#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6840 |
|
|
|
| 6841 |
|
|
/******************* Bit definition for CAN_F11R2 register ******************/
|
| 6842 |
|
|
#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6843 |
|
|
#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6844 |
|
|
#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6845 |
|
|
#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6846 |
|
|
#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6847 |
|
|
#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6848 |
|
|
#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6849 |
|
|
#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6850 |
|
|
#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6851 |
|
|
#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6852 |
|
|
#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6853 |
|
|
#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6854 |
|
|
#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6855 |
|
|
#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6856 |
|
|
#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6857 |
|
|
#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6858 |
|
|
#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6859 |
|
|
#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6860 |
|
|
#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6861 |
|
|
#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6862 |
|
|
#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6863 |
|
|
#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6864 |
|
|
#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6865 |
|
|
#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6866 |
|
|
#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6867 |
|
|
#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6868 |
|
|
#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6869 |
|
|
#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6870 |
|
|
#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6871 |
|
|
#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6872 |
|
|
#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6873 |
|
|
#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6874 |
|
|
|
| 6875 |
|
|
/******************* Bit definition for CAN_F12R2 register ******************/
|
| 6876 |
|
|
#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6877 |
|
|
#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6878 |
|
|
#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6879 |
|
|
#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6880 |
|
|
#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6881 |
|
|
#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6882 |
|
|
#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6883 |
|
|
#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6884 |
|
|
#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6885 |
|
|
#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6886 |
|
|
#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6887 |
|
|
#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6888 |
|
|
#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6889 |
|
|
#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6890 |
|
|
#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6891 |
|
|
#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6892 |
|
|
#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6893 |
|
|
#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6894 |
|
|
#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6895 |
|
|
#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6896 |
|
|
#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6897 |
|
|
#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6898 |
|
|
#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6899 |
|
|
#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6900 |
|
|
#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6901 |
|
|
#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6902 |
|
|
#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6903 |
|
|
#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6904 |
|
|
#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6905 |
|
|
#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6906 |
|
|
#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6907 |
|
|
#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6908 |
|
|
|
| 6909 |
|
|
/******************* Bit definition for CAN_F13R2 register ******************/
|
| 6910 |
|
|
#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
| 6911 |
|
|
#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
| 6912 |
|
|
#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
| 6913 |
|
|
#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
| 6914 |
|
|
#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
| 6915 |
|
|
#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
| 6916 |
|
|
#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
| 6917 |
|
|
#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
| 6918 |
|
|
#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
| 6919 |
|
|
#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
| 6920 |
|
|
#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
| 6921 |
|
|
#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
| 6922 |
|
|
#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
| 6923 |
|
|
#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
| 6924 |
|
|
#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
| 6925 |
|
|
#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
| 6926 |
|
|
#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
| 6927 |
|
|
#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
| 6928 |
|
|
#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
| 6929 |
|
|
#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
| 6930 |
|
|
#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
| 6931 |
|
|
#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
| 6932 |
|
|
#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
| 6933 |
|
|
#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
| 6934 |
|
|
#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
| 6935 |
|
|
#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
| 6936 |
|
|
#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
| 6937 |
|
|
#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
| 6938 |
|
|
#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
| 6939 |
|
|
#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
| 6940 |
|
|
#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
| 6941 |
|
|
#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
| 6942 |
|
|
|
| 6943 |
|
|
/******************************************************************************/
|
| 6944 |
|
|
/* */
|
| 6945 |
|
|
/* Serial Peripheral Interface */
|
| 6946 |
|
|
/* */
|
| 6947 |
|
|
/******************************************************************************/
|
| 6948 |
|
|
|
| 6949 |
|
|
/******************* Bit definition for SPI_CR1 register ********************/
|
| 6950 |
|
|
#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
|
| 6951 |
|
|
#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
|
| 6952 |
|
|
#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
|
| 6953 |
|
|
|
| 6954 |
|
|
#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
|
| 6955 |
|
|
#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
|
| 6956 |
|
|
#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
|
| 6957 |
|
|
#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
|
| 6958 |
|
|
|
| 6959 |
|
|
#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
|
| 6960 |
|
|
#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
|
| 6961 |
|
|
#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
|
| 6962 |
|
|
#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
|
| 6963 |
|
|
#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
|
| 6964 |
|
|
#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
|
| 6965 |
|
|
#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
|
| 6966 |
|
|
#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
|
| 6967 |
|
|
#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
|
| 6968 |
|
|
#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
|
| 6969 |
|
|
|
| 6970 |
|
|
/******************* Bit definition for SPI_CR2 register ********************/
|
| 6971 |
|
|
#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
|
| 6972 |
|
|
#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
|
| 6973 |
|
|
#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
|
| 6974 |
|
|
#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
|
| 6975 |
|
|
#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
|
| 6976 |
|
|
#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
|
| 6977 |
|
|
|
| 6978 |
|
|
/******************** Bit definition for SPI_SR register ********************/
|
| 6979 |
|
|
#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
|
| 6980 |
|
|
#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
|
| 6981 |
|
|
#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
|
| 6982 |
|
|
#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
|
| 6983 |
|
|
#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
|
| 6984 |
|
|
#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
|
| 6985 |
|
|
#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
|
| 6986 |
|
|
#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
|
| 6987 |
|
|
|
| 6988 |
|
|
/******************** Bit definition for SPI_DR register ********************/
|
| 6989 |
|
|
#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
|
| 6990 |
|
|
|
| 6991 |
|
|
/******************* Bit definition for SPI_CRCPR register ******************/
|
| 6992 |
|
|
#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
|
| 6993 |
|
|
|
| 6994 |
|
|
/****************** Bit definition for SPI_RXCRCR register ******************/
|
| 6995 |
|
|
#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
|
| 6996 |
|
|
|
| 6997 |
|
|
/****************** Bit definition for SPI_TXCRCR register ******************/
|
| 6998 |
|
|
#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
|
| 6999 |
|
|
|
| 7000 |
|
|
/****************** Bit definition for SPI_I2SCFGR register *****************/
|
| 7001 |
|
|
#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
|
| 7002 |
|
|
|
| 7003 |
|
|
#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
|
| 7004 |
|
|
#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
|
| 7005 |
|
|
#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
|
| 7006 |
|
|
|
| 7007 |
|
|
#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
|
| 7008 |
|
|
|
| 7009 |
|
|
#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
|
| 7010 |
|
|
#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 7011 |
|
|
#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 7012 |
|
|
|
| 7013 |
|
|
#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
|
| 7014 |
|
|
|
| 7015 |
|
|
#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
|
| 7016 |
|
|
#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 7017 |
|
|
#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 7018 |
|
|
|
| 7019 |
|
|
#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
|
| 7020 |
|
|
#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
|
| 7021 |
|
|
|
| 7022 |
|
|
/****************** Bit definition for SPI_I2SPR register *******************/
|
| 7023 |
|
|
#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
|
| 7024 |
|
|
#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
|
| 7025 |
|
|
#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
|
| 7026 |
|
|
|
| 7027 |
|
|
/******************************************************************************/
|
| 7028 |
|
|
/* */
|
| 7029 |
|
|
/* Inter-integrated Circuit Interface */
|
| 7030 |
|
|
/* */
|
| 7031 |
|
|
/******************************************************************************/
|
| 7032 |
|
|
|
| 7033 |
|
|
/******************* Bit definition for I2C_CR1 register ********************/
|
| 7034 |
|
|
#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
|
| 7035 |
|
|
#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
|
| 7036 |
|
|
#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
|
| 7037 |
|
|
#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
|
| 7038 |
|
|
#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
|
| 7039 |
|
|
#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
|
| 7040 |
|
|
#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
|
| 7041 |
|
|
#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
|
| 7042 |
|
|
#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
|
| 7043 |
|
|
#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
|
| 7044 |
|
|
#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
|
| 7045 |
|
|
#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
|
| 7046 |
|
|
#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
|
| 7047 |
|
|
#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
|
| 7048 |
|
|
|
| 7049 |
|
|
/******************* Bit definition for I2C_CR2 register ********************/
|
| 7050 |
|
|
#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
|
| 7051 |
|
|
#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 7052 |
|
|
#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 7053 |
|
|
#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
|
| 7054 |
|
|
#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
|
| 7055 |
|
|
#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
|
| 7056 |
|
|
#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
|
| 7057 |
|
|
|
| 7058 |
|
|
#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
|
| 7059 |
|
|
#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
|
| 7060 |
|
|
#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
|
| 7061 |
|
|
#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
|
| 7062 |
|
|
#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
|
| 7063 |
|
|
|
| 7064 |
|
|
/******************* Bit definition for I2C_OAR1 register *******************/
|
| 7065 |
|
|
#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
|
| 7066 |
|
|
#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
|
| 7067 |
|
|
|
| 7068 |
|
|
#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 7069 |
|
|
#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 7070 |
|
|
#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
|
| 7071 |
|
|
#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
|
| 7072 |
|
|
#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
|
| 7073 |
|
|
#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
|
| 7074 |
|
|
#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
|
| 7075 |
|
|
#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
|
| 7076 |
|
|
#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
|
| 7077 |
|
|
#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
|
| 7078 |
|
|
|
| 7079 |
|
|
#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
|
| 7080 |
|
|
|
| 7081 |
|
|
/******************* Bit definition for I2C_OAR2 register *******************/
|
| 7082 |
|
|
#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
|
| 7083 |
|
|
#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
|
| 7084 |
|
|
|
| 7085 |
|
|
/******************** Bit definition for I2C_DR register ********************/
|
| 7086 |
|
|
#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
|
| 7087 |
|
|
|
| 7088 |
|
|
/******************* Bit definition for I2C_SR1 register ********************/
|
| 7089 |
|
|
#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
|
| 7090 |
|
|
#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
|
| 7091 |
|
|
#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
|
| 7092 |
|
|
#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
|
| 7093 |
|
|
#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
|
| 7094 |
|
|
#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
|
| 7095 |
|
|
#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
|
| 7096 |
|
|
#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
|
| 7097 |
|
|
#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
|
| 7098 |
|
|
#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
|
| 7099 |
|
|
#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
|
| 7100 |
|
|
#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
|
| 7101 |
|
|
#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
|
| 7102 |
|
|
#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
|
| 7103 |
|
|
|
| 7104 |
|
|
/******************* Bit definition for I2C_SR2 register ********************/
|
| 7105 |
|
|
#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
|
| 7106 |
|
|
#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
|
| 7107 |
|
|
#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
|
| 7108 |
|
|
#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
|
| 7109 |
|
|
#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
|
| 7110 |
|
|
#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
|
| 7111 |
|
|
#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
|
| 7112 |
|
|
#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
|
| 7113 |
|
|
|
| 7114 |
|
|
/******************* Bit definition for I2C_CCR register ********************/
|
| 7115 |
|
|
#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
|
| 7116 |
|
|
#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
|
| 7117 |
|
|
#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
|
| 7118 |
|
|
|
| 7119 |
|
|
/****************** Bit definition for I2C_TRISE register *******************/
|
| 7120 |
|
|
#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
|
| 7121 |
|
|
|
| 7122 |
|
|
/******************************************************************************/
|
| 7123 |
|
|
/* */
|
| 7124 |
|
|
/* Universal Synchronous Asynchronous Receiver Transmitter */
|
| 7125 |
|
|
/* */
|
| 7126 |
|
|
/******************************************************************************/
|
| 7127 |
|
|
|
| 7128 |
|
|
/******************* Bit definition for USART_SR register *******************/
|
| 7129 |
|
|
#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
|
| 7130 |
|
|
#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
|
| 7131 |
|
|
#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
|
| 7132 |
|
|
#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
|
| 7133 |
|
|
#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
|
| 7134 |
|
|
#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
|
| 7135 |
|
|
#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
|
| 7136 |
|
|
#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
|
| 7137 |
|
|
#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
|
| 7138 |
|
|
#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
|
| 7139 |
|
|
|
| 7140 |
|
|
/******************* Bit definition for USART_DR register *******************/
|
| 7141 |
|
|
#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
|
| 7142 |
|
|
|
| 7143 |
|
|
/****************** Bit definition for USART_BRR register *******************/
|
| 7144 |
|
|
#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
|
| 7145 |
|
|
#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
|
| 7146 |
|
|
|
| 7147 |
|
|
/****************** Bit definition for USART_CR1 register *******************/
|
| 7148 |
|
|
#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
|
| 7149 |
|
|
#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
|
| 7150 |
|
|
#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
|
| 7151 |
|
|
#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
|
| 7152 |
|
|
#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
|
| 7153 |
|
|
#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
|
| 7154 |
|
|
#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
|
| 7155 |
|
|
#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
|
| 7156 |
|
|
#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
|
| 7157 |
|
|
#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
|
| 7158 |
|
|
#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
|
| 7159 |
|
|
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
|
| 7160 |
|
|
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
|
| 7161 |
|
|
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
|
| 7162 |
|
|
|
| 7163 |
|
|
/****************** Bit definition for USART_CR2 register *******************/
|
| 7164 |
|
|
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
|
| 7165 |
|
|
#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
|
| 7166 |
|
|
#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
|
| 7167 |
|
|
#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
|
| 7168 |
|
|
#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
|
| 7169 |
|
|
#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
|
| 7170 |
|
|
#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
|
| 7171 |
|
|
|
| 7172 |
|
|
#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
|
| 7173 |
|
|
#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 7174 |
|
|
#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 7175 |
|
|
|
| 7176 |
|
|
#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
|
| 7177 |
|
|
|
| 7178 |
|
|
/****************** Bit definition for USART_CR3 register *******************/
|
| 7179 |
|
|
#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
|
| 7180 |
|
|
#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
|
| 7181 |
|
|
#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
|
| 7182 |
|
|
#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
|
| 7183 |
|
|
#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
|
| 7184 |
|
|
#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
|
| 7185 |
|
|
#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
|
| 7186 |
|
|
#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
|
| 7187 |
|
|
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
|
| 7188 |
|
|
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
|
| 7189 |
|
|
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
|
| 7190 |
|
|
|
| 7191 |
|
|
/****************** Bit definition for USART_GTPR register ******************/
|
| 7192 |
|
|
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
|
| 7193 |
|
|
#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 7194 |
|
|
#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 7195 |
|
|
#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
|
| 7196 |
|
|
#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
|
| 7197 |
|
|
#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
|
| 7198 |
|
|
#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
|
| 7199 |
|
|
#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
|
| 7200 |
|
|
#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
|
| 7201 |
|
|
|
| 7202 |
|
|
#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
|
| 7203 |
|
|
|
| 7204 |
|
|
/******************************************************************************/
|
| 7205 |
|
|
/* */
|
| 7206 |
|
|
/* Debug MCU */
|
| 7207 |
|
|
/* */
|
| 7208 |
|
|
/******************************************************************************/
|
| 7209 |
|
|
|
| 7210 |
|
|
/**************** Bit definition for DBGMCU_IDCODE register *****************/
|
| 7211 |
|
|
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */
|
| 7212 |
|
|
|
| 7213 |
|
|
#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */
|
| 7214 |
|
|
#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
| 7215 |
|
|
#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
| 7216 |
|
|
#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
| 7217 |
|
|
#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
| 7218 |
|
|
#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
| 7219 |
|
|
#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
| 7220 |
|
|
#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
| 7221 |
|
|
#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
| 7222 |
|
|
#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */
|
| 7223 |
|
|
#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */
|
| 7224 |
|
|
#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */
|
| 7225 |
|
|
#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */
|
| 7226 |
|
|
#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */
|
| 7227 |
|
|
#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */
|
| 7228 |
|
|
#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */
|
| 7229 |
|
|
#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */
|
| 7230 |
|
|
|
| 7231 |
|
|
/****************** Bit definition for DBGMCU_CR register *******************/
|
| 7232 |
|
|
#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */
|
| 7233 |
|
|
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */
|
| 7234 |
|
|
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */
|
| 7235 |
|
|
#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */
|
| 7236 |
|
|
|
| 7237 |
|
|
#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
|
| 7238 |
|
|
#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
| 7239 |
|
|
#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
| 7240 |
|
|
|
| 7241 |
|
|
#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */
|
| 7242 |
|
|
#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */
|
| 7243 |
|
|
#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */
|
| 7244 |
|
|
#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */
|
| 7245 |
|
|
#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */
|
| 7246 |
|
|
#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */
|
| 7247 |
|
|
#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */
|
| 7248 |
|
|
#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */
|
| 7249 |
|
|
#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */
|
| 7250 |
|
|
#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */
|
| 7251 |
|
|
#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */
|
| 7252 |
|
|
#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */
|
| 7253 |
|
|
#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */
|
| 7254 |
|
|
#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */
|
| 7255 |
|
|
|
| 7256 |
|
|
/******************************************************************************/
|
| 7257 |
|
|
/* */
|
| 7258 |
|
|
/* FLASH and Option Bytes Registers */
|
| 7259 |
|
|
/* */
|
| 7260 |
|
|
/******************************************************************************/
|
| 7261 |
|
|
|
| 7262 |
|
|
/******************* Bit definition for FLASH_ACR register ******************/
|
| 7263 |
|
|
#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */
|
| 7264 |
|
|
#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */
|
| 7265 |
|
|
#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */
|
| 7266 |
|
|
#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */
|
| 7267 |
|
|
|
| 7268 |
|
|
#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */
|
| 7269 |
|
|
#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */
|
| 7270 |
|
|
#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */
|
| 7271 |
|
|
|
| 7272 |
|
|
/****************** Bit definition for FLASH_KEYR register ******************/
|
| 7273 |
|
|
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */
|
| 7274 |
|
|
|
| 7275 |
|
|
/***************** Bit definition for FLASH_OPTKEYR register ****************/
|
| 7276 |
|
|
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */
|
| 7277 |
|
|
|
| 7278 |
|
|
/****************** Bit definition for FLASH_SR register *******************/
|
| 7279 |
|
|
#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */
|
| 7280 |
|
|
#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */
|
| 7281 |
|
|
#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */
|
| 7282 |
|
|
#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */
|
| 7283 |
|
|
|
| 7284 |
|
|
/******************* Bit definition for FLASH_CR register *******************/
|
| 7285 |
|
|
#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */
|
| 7286 |
|
|
#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */
|
| 7287 |
|
|
#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */
|
| 7288 |
|
|
#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */
|
| 7289 |
|
|
#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */
|
| 7290 |
|
|
#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */
|
| 7291 |
|
|
#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */
|
| 7292 |
|
|
#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */
|
| 7293 |
|
|
#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */
|
| 7294 |
|
|
#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */
|
| 7295 |
|
|
|
| 7296 |
|
|
/******************* Bit definition for FLASH_AR register *******************/
|
| 7297 |
|
|
#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */
|
| 7298 |
|
|
|
| 7299 |
|
|
/****************** Bit definition for FLASH_OBR register *******************/
|
| 7300 |
|
|
#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */
|
| 7301 |
|
|
#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */
|
| 7302 |
|
|
|
| 7303 |
|
|
#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */
|
| 7304 |
|
|
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */
|
| 7305 |
|
|
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */
|
| 7306 |
|
|
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */
|
| 7307 |
|
|
#define FLASH_OBR_Notused ((uint16_t)0x03E0) /*!<Not used */
|
| 7308 |
|
|
|
| 7309 |
|
|
/****************** Bit definition for FLASH_WRPR register ******************/
|
| 7310 |
|
|
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */
|
| 7311 |
|
|
|
| 7312 |
|
|
/*----------------------------------------------------------------------------*/
|
| 7313 |
|
|
|
| 7314 |
|
|
/****************** Bit definition for FLASH_RDP register *******************/
|
| 7315 |
|
|
#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */
|
| 7316 |
|
|
#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */
|
| 7317 |
|
|
|
| 7318 |
|
|
/****************** Bit definition for FLASH_USER register ******************/
|
| 7319 |
|
|
#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */
|
| 7320 |
|
|
#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */
|
| 7321 |
|
|
|
| 7322 |
|
|
/****************** Bit definition for FLASH_Data0 register *****************/
|
| 7323 |
|
|
#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */
|
| 7324 |
|
|
#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */
|
| 7325 |
|
|
|
| 7326 |
|
|
/****************** Bit definition for FLASH_Data1 register *****************/
|
| 7327 |
|
|
#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */
|
| 7328 |
|
|
#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */
|
| 7329 |
|
|
|
| 7330 |
|
|
/****************** Bit definition for FLASH_WRP0 register ******************/
|
| 7331 |
|
|
#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
|
| 7332 |
|
|
#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
|
| 7333 |
|
|
|
| 7334 |
|
|
/****************** Bit definition for FLASH_WRP1 register ******************/
|
| 7335 |
|
|
#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
|
| 7336 |
|
|
#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
|
| 7337 |
|
|
|
| 7338 |
|
|
/****************** Bit definition for FLASH_WRP2 register ******************/
|
| 7339 |
|
|
#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
|
| 7340 |
|
|
#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
|
| 7341 |
|
|
|
| 7342 |
|
|
/****************** Bit definition for FLASH_WRP3 register ******************/
|
| 7343 |
|
|
#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
|
| 7344 |
|
|
#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
|
| 7345 |
|
|
|
| 7346 |
|
|
#ifdef STM32F10X_CL
|
| 7347 |
|
|
/******************************************************************************/
|
| 7348 |
|
|
/* Ethernet MAC Registers bits definitions */
|
| 7349 |
|
|
/******************************************************************************/
|
| 7350 |
|
|
/* Bit definition for Ethernet MAC Control Register register */
|
| 7351 |
|
|
#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
|
| 7352 |
|
|
#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
|
| 7353 |
|
|
#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
|
| 7354 |
|
|
#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
|
| 7355 |
|
|
#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
|
| 7356 |
|
|
#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
|
| 7357 |
|
|
#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
|
| 7358 |
|
|
#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
|
| 7359 |
|
|
#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
|
| 7360 |
|
|
#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
|
| 7361 |
|
|
#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
|
| 7362 |
|
|
#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
|
| 7363 |
|
|
#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
|
| 7364 |
|
|
#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
|
| 7365 |
|
|
#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
|
| 7366 |
|
|
#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
|
| 7367 |
|
|
#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
|
| 7368 |
|
|
#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
|
| 7369 |
|
|
#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
|
| 7370 |
|
|
#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
|
| 7371 |
|
|
a transmission attempt during retries after a collision: 0 =< r <2^k */
|
| 7372 |
|
|
#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
|
| 7373 |
|
|
#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
|
| 7374 |
|
|
#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
|
| 7375 |
|
|
#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
|
| 7376 |
|
|
#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
|
| 7377 |
|
|
#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
|
| 7378 |
|
|
#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
|
| 7379 |
|
|
|
| 7380 |
|
|
/* Bit definition for Ethernet MAC Frame Filter Register */
|
| 7381 |
|
|
#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
|
| 7382 |
|
|
#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
|
| 7383 |
|
|
#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
|
| 7384 |
|
|
#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
|
| 7385 |
|
|
#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
|
| 7386 |
|
|
#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
|
| 7387 |
|
|
#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
|
| 7388 |
|
|
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
|
| 7389 |
|
|
#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
|
| 7390 |
|
|
#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
|
| 7391 |
|
|
#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
|
| 7392 |
|
|
#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
|
| 7393 |
|
|
#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
|
| 7394 |
|
|
#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
|
| 7395 |
|
|
|
| 7396 |
|
|
/* Bit definition for Ethernet MAC Hash Table High Register */
|
| 7397 |
|
|
#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
|
| 7398 |
|
|
|
| 7399 |
|
|
/* Bit definition for Ethernet MAC Hash Table Low Register */
|
| 7400 |
|
|
#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
|
| 7401 |
|
|
|
| 7402 |
|
|
/* Bit definition for Ethernet MAC MII Address Register */
|
| 7403 |
|
|
#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
|
| 7404 |
|
|
#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
|
| 7405 |
|
|
#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
|
| 7406 |
|
|
#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
|
| 7407 |
|
|
#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
|
| 7408 |
|
|
#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
|
| 7409 |
|
|
#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
|
| 7410 |
|
|
#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
|
| 7411 |
|
|
|
| 7412 |
|
|
/* Bit definition for Ethernet MAC MII Data Register */
|
| 7413 |
|
|
#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
|
| 7414 |
|
|
|
| 7415 |
|
|
/* Bit definition for Ethernet MAC Flow Control Register */
|
| 7416 |
|
|
#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
|
| 7417 |
|
|
#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
|
| 7418 |
|
|
#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
|
| 7419 |
|
|
#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
| 7420 |
|
|
#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
|
| 7421 |
|
|
#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
|
| 7422 |
|
|
#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
|
| 7423 |
|
|
#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
|
| 7424 |
|
|
#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
|
| 7425 |
|
|
#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
|
| 7426 |
|
|
#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
|
| 7427 |
|
|
|
| 7428 |
|
|
/* Bit definition for Ethernet MAC VLAN Tag Register */
|
| 7429 |
|
|
#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
|
| 7430 |
|
|
#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
|
| 7431 |
|
|
|
| 7432 |
|
|
/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
|
| 7433 |
|
|
#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
|
| 7434 |
|
|
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
|
| 7435 |
|
|
Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
|
| 7436 |
|
|
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
|
| 7437 |
|
|
Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
|
| 7438 |
|
|
Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
|
| 7439 |
|
|
Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
|
| 7440 |
|
|
Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
|
| 7441 |
|
|
RSVD - Filter1 Command - RSVD - Filter0 Command
|
| 7442 |
|
|
Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
|
| 7443 |
|
|
Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
|
| 7444 |
|
|
Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
|
| 7445 |
|
|
|
| 7446 |
|
|
/* Bit definition for Ethernet MAC PMT Control and Status Register */
|
| 7447 |
|
|
#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
|
| 7448 |
|
|
#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
|
| 7449 |
|
|
#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
|
| 7450 |
|
|
#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
|
| 7451 |
|
|
#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
|
| 7452 |
|
|
#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
|
| 7453 |
|
|
#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
|
| 7454 |
|
|
|
| 7455 |
|
|
/* Bit definition for Ethernet MAC Status Register */
|
| 7456 |
|
|
#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
|
| 7457 |
|
|
#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
|
| 7458 |
|
|
#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
|
| 7459 |
|
|
#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
|
| 7460 |
|
|
#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
|
| 7461 |
|
|
|
| 7462 |
|
|
/* Bit definition for Ethernet MAC Interrupt Mask Register */
|
| 7463 |
|
|
#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
|
| 7464 |
|
|
#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
|
| 7465 |
|
|
|
| 7466 |
|
|
/* Bit definition for Ethernet MAC Address0 High Register */
|
| 7467 |
|
|
#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
|
| 7468 |
|
|
|
| 7469 |
|
|
/* Bit definition for Ethernet MAC Address0 Low Register */
|
| 7470 |
|
|
#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
|
| 7471 |
|
|
|
| 7472 |
|
|
/* Bit definition for Ethernet MAC Address1 High Register */
|
| 7473 |
|
|
#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
|
| 7474 |
|
|
#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
|
| 7475 |
|
|
#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
| 7476 |
|
|
#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
| 7477 |
|
|
#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
| 7478 |
|
|
#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
| 7479 |
|
|
#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
| 7480 |
|
|
#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
| 7481 |
|
|
#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
| 7482 |
|
|
#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
|
| 7483 |
|
|
|
| 7484 |
|
|
/* Bit definition for Ethernet MAC Address1 Low Register */
|
| 7485 |
|
|
#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
|
| 7486 |
|
|
|
| 7487 |
|
|
/* Bit definition for Ethernet MAC Address2 High Register */
|
| 7488 |
|
|
#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
|
| 7489 |
|
|
#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
|
| 7490 |
|
|
#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
|
| 7491 |
|
|
#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
| 7492 |
|
|
#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
| 7493 |
|
|
#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
| 7494 |
|
|
#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
| 7495 |
|
|
#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
| 7496 |
|
|
#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
|
| 7497 |
|
|
#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
|
| 7498 |
|
|
|
| 7499 |
|
|
/* Bit definition for Ethernet MAC Address2 Low Register */
|
| 7500 |
|
|
#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
|
| 7501 |
|
|
|
| 7502 |
|
|
/* Bit definition for Ethernet MAC Address3 High Register */
|
| 7503 |
|
|
#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
|
| 7504 |
|
|
#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
|
| 7505 |
|
|
#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
|
| 7506 |
|
|
#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
| 7507 |
|
|
#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
| 7508 |
|
|
#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
| 7509 |
|
|
#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
| 7510 |
|
|
#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
| 7511 |
|
|
#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
|
| 7512 |
|
|
#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
|
| 7513 |
|
|
|
| 7514 |
|
|
/* Bit definition for Ethernet MAC Address3 Low Register */
|
| 7515 |
|
|
#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
|
| 7516 |
|
|
|
| 7517 |
|
|
/******************************************************************************/
|
| 7518 |
|
|
/* Ethernet MMC Registers bits definition */
|
| 7519 |
|
|
/******************************************************************************/
|
| 7520 |
|
|
|
| 7521 |
|
|
/* Bit definition for Ethernet MMC Contol Register */
|
| 7522 |
|
|
#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
|
| 7523 |
|
|
#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
|
| 7524 |
|
|
#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
|
| 7525 |
|
|
#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
|
| 7526 |
|
|
|
| 7527 |
|
|
/* Bit definition for Ethernet MMC Receive Interrupt Register */
|
| 7528 |
|
|
#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
|
| 7529 |
|
|
#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
|
| 7530 |
|
|
#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
|
| 7531 |
|
|
|
| 7532 |
|
|
/* Bit definition for Ethernet MMC Transmit Interrupt Register */
|
| 7533 |
|
|
#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
|
| 7534 |
|
|
#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
|
| 7535 |
|
|
#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
|
| 7536 |
|
|
|
| 7537 |
|
|
/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
|
| 7538 |
|
|
#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
|
| 7539 |
|
|
#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
|
| 7540 |
|
|
#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
|
| 7541 |
|
|
|
| 7542 |
|
|
/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
|
| 7543 |
|
|
#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
|
| 7544 |
|
|
#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
|
| 7545 |
|
|
#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
|
| 7546 |
|
|
|
| 7547 |
|
|
/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
|
| 7548 |
|
|
#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
|
| 7549 |
|
|
|
| 7550 |
|
|
/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
|
| 7551 |
|
|
#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
|
| 7552 |
|
|
|
| 7553 |
|
|
/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
|
| 7554 |
|
|
#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
|
| 7555 |
|
|
|
| 7556 |
|
|
/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
|
| 7557 |
|
|
#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
|
| 7558 |
|
|
|
| 7559 |
|
|
/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
| 7560 |
|
|
#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
|
| 7561 |
|
|
|
| 7562 |
|
|
/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
|
| 7563 |
|
|
#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
|
| 7564 |
|
|
|
| 7565 |
|
|
/******************************************************************************/
|
| 7566 |
|
|
/* Ethernet PTP Registers bits definition */
|
| 7567 |
|
|
/******************************************************************************/
|
| 7568 |
|
|
|
| 7569 |
|
|
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
| 7570 |
|
|
#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
|
| 7571 |
|
|
#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
|
| 7572 |
|
|
#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
|
| 7573 |
|
|
#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
|
| 7574 |
|
|
#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
|
| 7575 |
|
|
#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
|
| 7576 |
|
|
|
| 7577 |
|
|
/* Bit definition for Ethernet PTP Sub-Second Increment Register */
|
| 7578 |
|
|
#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
|
| 7579 |
|
|
|
| 7580 |
|
|
/* Bit definition for Ethernet PTP Time Stamp High Register */
|
| 7581 |
|
|
#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
|
| 7582 |
|
|
|
| 7583 |
|
|
/* Bit definition for Ethernet PTP Time Stamp Low Register */
|
| 7584 |
|
|
#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
|
| 7585 |
|
|
#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
|
| 7586 |
|
|
|
| 7587 |
|
|
/* Bit definition for Ethernet PTP Time Stamp High Update Register */
|
| 7588 |
|
|
#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
|
| 7589 |
|
|
|
| 7590 |
|
|
/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
|
| 7591 |
|
|
#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
|
| 7592 |
|
|
#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
|
| 7593 |
|
|
|
| 7594 |
|
|
/* Bit definition for Ethernet PTP Time Stamp Addend Register */
|
| 7595 |
|
|
#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
|
| 7596 |
|
|
|
| 7597 |
|
|
/* Bit definition for Ethernet PTP Target Time High Register */
|
| 7598 |
|
|
#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
|
| 7599 |
|
|
|
| 7600 |
|
|
/* Bit definition for Ethernet PTP Target Time Low Register */
|
| 7601 |
|
|
#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
|
| 7602 |
|
|
|
| 7603 |
|
|
/******************************************************************************/
|
| 7604 |
|
|
/* Ethernet DMA Registers bits definition */
|
| 7605 |
|
|
/******************************************************************************/
|
| 7606 |
|
|
|
| 7607 |
|
|
/* Bit definition for Ethernet DMA Bus Mode Register */
|
| 7608 |
|
|
#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
|
| 7609 |
|
|
#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
|
| 7610 |
|
|
#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
|
| 7611 |
|
|
#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
|
| 7612 |
|
|
#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
|
| 7613 |
|
|
#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
|
| 7614 |
|
|
#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
| 7615 |
|
|
#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
| 7616 |
|
|
#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
| 7617 |
|
|
#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
| 7618 |
|
|
#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
| 7619 |
|
|
#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
| 7620 |
|
|
#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
| 7621 |
|
|
#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
| 7622 |
|
|
#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
|
| 7623 |
|
|
#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
|
| 7624 |
|
|
#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
|
| 7625 |
|
|
#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
|
| 7626 |
|
|
#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
|
| 7627 |
|
|
#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
|
| 7628 |
|
|
#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
|
| 7629 |
|
|
#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
|
| 7630 |
|
|
#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
|
| 7631 |
|
|
#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
|
| 7632 |
|
|
#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
|
| 7633 |
|
|
#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
| 7634 |
|
|
#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
| 7635 |
|
|
#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
| 7636 |
|
|
#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
| 7637 |
|
|
#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
| 7638 |
|
|
#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
| 7639 |
|
|
#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
| 7640 |
|
|
#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
| 7641 |
|
|
#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
|
| 7642 |
|
|
#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
|
| 7643 |
|
|
#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
|
| 7644 |
|
|
#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
|
| 7645 |
|
|
#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
|
| 7646 |
|
|
|
| 7647 |
|
|
/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
|
| 7648 |
|
|
#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
|
| 7649 |
|
|
|
| 7650 |
|
|
/* Bit definition for Ethernet DMA Receive Poll Demand Register */
|
| 7651 |
|
|
#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
|
| 7652 |
|
|
|
| 7653 |
|
|
/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
|
| 7654 |
|
|
#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
|
| 7655 |
|
|
|
| 7656 |
|
|
/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
|
| 7657 |
|
|
#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
|
| 7658 |
|
|
|
| 7659 |
|
|
/* Bit definition for Ethernet DMA Status Register */
|
| 7660 |
|
|
#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
|
| 7661 |
|
|
#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
|
| 7662 |
|
|
#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
|
| 7663 |
|
|
#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
|
| 7664 |
|
|
/* combination with EBS[2:0] for GetFlagStatus function */
|
| 7665 |
|
|
#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
|
| 7666 |
|
|
#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
|
| 7667 |
|
|
#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
|
| 7668 |
|
|
#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
|
| 7669 |
|
|
#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
|
| 7670 |
|
|
#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
|
| 7671 |
|
|
#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
|
| 7672 |
|
|
#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
|
| 7673 |
|
|
#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
|
| 7674 |
|
|
#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
|
| 7675 |
|
|
#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
|
| 7676 |
|
|
#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
|
| 7677 |
|
|
#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
|
| 7678 |
|
|
#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
|
| 7679 |
|
|
#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
|
| 7680 |
|
|
#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
|
| 7681 |
|
|
#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
|
| 7682 |
|
|
#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
|
| 7683 |
|
|
#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
|
| 7684 |
|
|
#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
|
| 7685 |
|
|
#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
|
| 7686 |
|
|
#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
|
| 7687 |
|
|
#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
|
| 7688 |
|
|
#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
|
| 7689 |
|
|
#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
|
| 7690 |
|
|
#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
|
| 7691 |
|
|
#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
|
| 7692 |
|
|
#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
|
| 7693 |
|
|
#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
|
| 7694 |
|
|
#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
|
| 7695 |
|
|
#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
|
| 7696 |
|
|
#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
|
| 7697 |
|
|
|
| 7698 |
|
|
/* Bit definition for Ethernet DMA Operation Mode Register */
|
| 7699 |
|
|
#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
|
| 7700 |
|
|
#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
|
| 7701 |
|
|
#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
|
| 7702 |
|
|
#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
|
| 7703 |
|
|
#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
|
| 7704 |
|
|
#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
|
| 7705 |
|
|
#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
|
| 7706 |
|
|
#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
|
| 7707 |
|
|
#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
|
| 7708 |
|
|
#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
|
| 7709 |
|
|
#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
|
| 7710 |
|
|
#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
|
| 7711 |
|
|
#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
|
| 7712 |
|
|
#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
|
| 7713 |
|
|
#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
|
| 7714 |
|
|
#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
|
| 7715 |
|
|
#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
|
| 7716 |
|
|
#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
|
| 7717 |
|
|
#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
|
| 7718 |
|
|
#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
|
| 7719 |
|
|
#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
|
| 7720 |
|
|
#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
|
| 7721 |
|
|
#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
|
| 7722 |
|
|
#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
|
| 7723 |
|
|
|
| 7724 |
|
|
/* Bit definition for Ethernet DMA Interrupt Enable Register */
|
| 7725 |
|
|
#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
|
| 7726 |
|
|
#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
|
| 7727 |
|
|
#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
|
| 7728 |
|
|
#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
|
| 7729 |
|
|
#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
|
| 7730 |
|
|
#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
|
| 7731 |
|
|
#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
|
| 7732 |
|
|
#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
|
| 7733 |
|
|
#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
|
| 7734 |
|
|
#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
|
| 7735 |
|
|
#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
|
| 7736 |
|
|
#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
|
| 7737 |
|
|
#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
|
| 7738 |
|
|
#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
|
| 7739 |
|
|
#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
|
| 7740 |
|
|
|
| 7741 |
|
|
/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
|
| 7742 |
|
|
#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
|
| 7743 |
|
|
#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
|
| 7744 |
|
|
#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
|
| 7745 |
|
|
#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
|
| 7746 |
|
|
|
| 7747 |
|
|
/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
|
| 7748 |
|
|
#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
|
| 7749 |
|
|
|
| 7750 |
|
|
/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
|
| 7751 |
|
|
#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
|
| 7752 |
|
|
|
| 7753 |
|
|
/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
|
| 7754 |
|
|
#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
|
| 7755 |
|
|
|
| 7756 |
|
|
/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
|
| 7757 |
|
|
#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
|
| 7758 |
|
|
#endif /* STM32F10X_CL */
|
| 7759 |
|
|
|
| 7760 |
|
|
/**
|
| 7761 |
|
|
* @}
|
| 7762 |
|
|
*/
|
| 7763 |
|
|
|
| 7764 |
|
|
/**
|
| 7765 |
|
|
* @}
|
| 7766 |
|
|
*/
|
| 7767 |
|
|
|
| 7768 |
|
|
#ifdef USE_STDPERIPH_DRIVER
|
| 7769 |
|
|
#include "stm32f10x_conf.h"
|
| 7770 |
|
|
#endif
|
| 7771 |
|
|
|
| 7772 |
|
|
/** @addtogroup Exported_macro
|
| 7773 |
|
|
* @{
|
| 7774 |
|
|
*/
|
| 7775 |
|
|
|
| 7776 |
|
|
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
| 7777 |
|
|
|
| 7778 |
|
|
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
| 7779 |
|
|
|
| 7780 |
|
|
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
| 7781 |
|
|
|
| 7782 |
|
|
#define CLEAR_REG(REG) ((REG) = (0x0))
|
| 7783 |
|
|
|
| 7784 |
|
|
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
| 7785 |
|
|
|
| 7786 |
|
|
#define READ_REG(REG) ((REG))
|
| 7787 |
|
|
|
| 7788 |
|
|
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK)))
|
| 7789 |
|
|
|
| 7790 |
|
|
/**
|
| 7791 |
|
|
* @}
|
| 7792 |
|
|
*/
|
| 7793 |
|
|
|
| 7794 |
|
|
#endif /* __STM32F10x_H */
|
| 7795 |
|
|
|
| 7796 |
|
|
/**
|
| 7797 |
|
|
* @}
|
| 7798 |
|
|
*/
|
| 7799 |
|
|
|
| 7800 |
|
|
/**
|
| 7801 |
|
|
* @}
|
| 7802 |
|
|
*/
|
| 7803 |
|
|
|
| 7804 |
|
|
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
|
