OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_STM32L152_IAR/] [settings/] [RTOSDemo.dbgdt] - Blame information for rev 637

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 582 jeremybenn
2
 
3
4
  
5
    
6
      
7
 
8
 
9
      300201622
10
      
11
        20
12
        1216
13
        324
14
        81
15
      300Debug-Log
16
      
17
        
18
 
19
 
20
 
21
 
22
        332272727
23
      
24
      
25
        
26
 
27
 
28
 
29
 
30
        200
31
 
32
 
33
 
34
      111
35
    {W}Watch-0:tmppre1200151148100100200208100100100200110$PROJ_DIR$\TermIOInput.txt102001001001001001001001503001001001001001001002001001
36
    
37
 
38
 
39
    
40
        
41
          
42
            TabID-15530-21362
43
            Workspace
44
            Workspace
45
            
46
 
47
            RTOSDemoRTOSDemo/FreeRTOS_SourceRTOSDemo/FreeRTOS_Source/PortableRTOSDemo/Standard_Demo_Code
48
          
49
        
50
 
51
      0TabID-10464-23570TasksTASKVIEW0TabID-31438-23586QueuesQUEUEVIEW0TabID-15541-875Terminal I/OTerminalIO0
52
    
53
 
54
 
55
 
56
 
57
    TextEditor$WS_DIR$\main.c021910728107280TextEditor$WS_DIR$\..\..\Source\queue.c0103535647356470100000010000001
58
    
59
 
60
 
61
 
62
 
63
 
64
    iaridepm.enu1debuggergui.enu1armjlink.enu1-2-2659406-2-2200200119048203666242857673116-2-2659436-2-2200200119048203666260714673116-2-21721682-2-216841741002381177189119048203666170-22551682-2170168485100238186558119048203666
65
  
66
67
 
68
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.