URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_STM32L152_IAR/] [settings/] [RTOSDemo_Debug.jlink] - Blame information for rev 800

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[BREAKPOINTS]
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ADUC7020X62"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
[SWO]
SWOLogFile=""

Line No.	Rev	Author	Line
1	582	jeremybenn	`[BREAKPOINTS]`
2			`ShowInfoWin = 1`
3			`EnableFlashBP = 2`
4			`BPDuringExecution = 0`
5			`[CFI]`
6			`CFISize = 0x00`
7			`CFIAddr = 0x00`
8			`[CPU]`
9			`OverrideMemMap = 0`
10			`AllowSimulation = 1`
11			`ScriptFile=""`
12			`[FLASH]`
13			`SkipProgOnCRCMatch = 1`
14			`VerifyDownload = 1`
15			`AllowCaching = 1`
16			`EnableFlashDL = 2`
17			`Override = 0`
18			`Device="ADUC7020X62"`
19			`[GENERAL]`
20			`WorkRAMSize = 0x00`
21			`WorkRAMAddr = 0x00`
22			`[SWO]`
23			`SWOLogFile=""`

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_STM32L152_IAR/] [settings/] [RTOSDemo_Debug.jlink] - Blame information for rev 800