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jeremybenn |
/**
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******************************************************************************
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* @file stm32l1xx.h
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* @author STMicroelectronics - MCD Application Team
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* @version V1.0.0RC1
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* @date 07/02/2010
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32L1xx devices.
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******************************************************************************
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32l1xx
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* @{
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*/
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#ifndef __STM32L1XX_H
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#define __STM32L1XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/* Uncomment the line below according to the target STM32L device used in your
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application
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*/
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#if !defined (STM32L1XX_MD)
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#define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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- Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx
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microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
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*/
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#if !defined USE_STDPERIPH_DRIVER
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_STDPERIPH_DRIVER*/
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#endif
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/**
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* @brief In the following line adjust the value of External High Speed oscillator (HSE)
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used in your application
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Tip: To avoid modifying this file each time you need to use different HSE, you
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can define the HSE value in your toolchain compiler preprocessor.
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*/
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#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
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/**
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
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Timeout value
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*/
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
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#define MSI_VALUE ((uint32_t)2000000) /*!< Default value of the Internal Multi Speed oscillator in Hz */
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz */
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#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz */
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#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
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/**
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* @brief STM32L1xx Standard Peripheral Library version number
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*/
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#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:16] STM32L1xx Standard Peripheral Library main version */
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#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [15:8] STM32L1xx Standard Peripheral Library sub1 version */
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#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32L1xx Standard Peripheral Library sub2 version */
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#define __STM32L1XX_STDPERIPH_VERSION ((__STM32L1XX_STDPERIPH_VERSION_MAIN << 16)\
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| (__STM32L1XX_STDPERIPH_VERSION_SUB1 << 8)\
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| __STM32L1XX_STDPERIPH_VERSION_SUB2)
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/**
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* @}
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*/
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/** @addtogroup Configuration_section_for_CMSIS
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* @{
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*/
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/**
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* @brief STM32L1xx Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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#define __MPU_PRESENT 1 /*!< STM32L provide a MPU present */
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#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/*!< Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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/****** STM32L specific Interrupt Numbers ********************************************************/
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WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */
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RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
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FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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RCC_IRQn = 5, /*!< RCC global Interrupt */
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EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
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DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
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DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
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DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
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DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
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DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
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DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
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ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
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USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
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USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
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DAC_IRQn = 21, /*!< DAC Interrupt */
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COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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LCD_IRQn = 24, /*!< LCD Interrupt */
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TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
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TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
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TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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USART1_IRQn = 37, /*!< USART1 global Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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USART3_IRQn = 39, /*!< USART3 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
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TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
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TIM7_IRQn = 44 /*!< TIM7 global Interrupt */
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} IRQn_Type;
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/**
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* @}
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*/
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#include "core_cm3.h"
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#include "system_stm32l1xx.h"
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#include <stdint.h>
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum {FALSE = 0, TRUE = !FALSE} bool;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Peripheral_registers_structures
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* @{
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*/
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/**
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* @brief Analog to Digital Converter
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*/
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typedef struct
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{
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__IO uint32_t SR;
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__IO uint32_t CR1;
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__IO uint32_t CR2;
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__IO uint32_t SMPR1;
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__IO uint32_t SMPR2;
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__IO uint32_t SMPR3;
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__IO uint32_t JOFR1;
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__IO uint32_t JOFR2;
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__IO uint32_t JOFR3;
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__IO uint32_t JOFR4;
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__IO uint32_t HTR;
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__IO uint32_t LTR;
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__IO uint32_t SQR1;
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__IO uint32_t SQR2;
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__IO uint32_t SQR3;
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__IO uint32_t SQR4;
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__IO uint32_t SQR5;
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__IO uint32_t JSQR;
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__IO uint32_t JDR1;
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__IO uint32_t JDR2;
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__IO uint32_t JDR3;
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__IO uint32_t JDR4;
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__IO uint32_t DR;
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} ADC_TypeDef;
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typedef struct
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{
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__IO uint32_t CSR;
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__IO uint32_t CCR;
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} ADC_Common_TypeDef;
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/**
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* @brief Comparator
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*/
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typedef struct
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{
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__IO uint32_t CSR;
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} COMP_TypeDef;
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/**
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* @brief CRC calculation unit
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*/
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typedef struct
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{
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__IO uint32_t DR;
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__IO uint8_t IDR;
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uint8_t RESERVED0;
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uint16_t RESERVED1;
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__IO uint32_t CR;
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} CRC_TypeDef;
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/**
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* @brief Digital to Analog Converter
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*/
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typedef struct
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{
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__IO uint32_t CR;
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__IO uint32_t SWTRIGR;
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__IO uint32_t DHR12R1;
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__IO uint32_t DHR12L1;
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__IO uint32_t DHR8R1;
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__IO uint32_t DHR12R2;
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__IO uint32_t DHR12L2;
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__IO uint32_t DHR8R2;
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__IO uint32_t DHR12RD;
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__IO uint32_t DHR12LD;
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__IO uint32_t DHR8RD;
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__IO uint32_t DOR1;
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__IO uint32_t DOR2;
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__IO uint32_t SR;
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} DAC_TypeDef;
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/**
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* @brief Debug MCU
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*/
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typedef struct
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{
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__IO uint32_t IDCODE;
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__IO uint32_t CR;
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__IO uint32_t APB1FZ;
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__IO uint32_t APB2FZ;
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}DBGMCU_TypeDef;
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/**
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* @brief DMA Controller
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*/
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typedef struct
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{
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__IO uint32_t CCR;
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__IO uint32_t CNDTR;
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__IO uint32_t CPAR;
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__IO uint32_t CMAR;
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} DMA_Channel_TypeDef;
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typedef struct
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{
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__IO uint32_t ISR;
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__IO uint32_t IFCR;
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} DMA_TypeDef;
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/**
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* @brief External Interrupt/Event Controller
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*/
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typedef struct
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{
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__IO uint32_t IMR;
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__IO uint32_t EMR;
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__IO uint32_t RTSR;
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__IO uint32_t FTSR;
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__IO uint32_t SWIER;
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__IO uint32_t PR;
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} EXTI_TypeDef;
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/**
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* @brief FLASH Registers
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*/
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| 332 |
|
|
typedef struct
|
| 333 |
|
|
{
|
| 334 |
|
|
__IO uint32_t ACR;
|
| 335 |
|
|
__IO uint32_t PECR;
|
| 336 |
|
|
__IO uint32_t PDKEYR;
|
| 337 |
|
|
__IO uint32_t PEKEYR;
|
| 338 |
|
|
__IO uint32_t PRGKEYR;
|
| 339 |
|
|
__IO uint32_t OPTKEYR;
|
| 340 |
|
|
__IO uint32_t SR;
|
| 341 |
|
|
__IO uint32_t OBR;
|
| 342 |
|
|
__IO uint32_t WRPR;
|
| 343 |
|
|
} FLASH_TypeDef;
|
| 344 |
|
|
|
| 345 |
|
|
/**
|
| 346 |
|
|
* @brief Option Bytes Registers
|
| 347 |
|
|
*/
|
| 348 |
|
|
|
| 349 |
|
|
typedef struct
|
| 350 |
|
|
{
|
| 351 |
|
|
__IO uint32_t RDP;
|
| 352 |
|
|
__IO uint32_t USER;
|
| 353 |
|
|
__IO uint32_t WRP01;
|
| 354 |
|
|
__IO uint32_t WRP23;
|
| 355 |
|
|
} OB_TypeDef;
|
| 356 |
|
|
|
| 357 |
|
|
/**
|
| 358 |
|
|
* @brief General Purpose IO
|
| 359 |
|
|
*/
|
| 360 |
|
|
|
| 361 |
|
|
typedef struct
|
| 362 |
|
|
{
|
| 363 |
|
|
__IO uint32_t MODER;
|
| 364 |
|
|
__IO uint16_t OTYPER;
|
| 365 |
|
|
uint16_t RESERVED0;
|
| 366 |
|
|
__IO uint32_t OSPEEDR;
|
| 367 |
|
|
__IO uint32_t PUPDR;
|
| 368 |
|
|
__IO uint16_t IDR;
|
| 369 |
|
|
uint16_t RESERVED1;
|
| 370 |
|
|
__IO uint16_t ODR;
|
| 371 |
|
|
uint16_t RESERVED2;
|
| 372 |
|
|
__IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */
|
| 373 |
|
|
__IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */
|
| 374 |
|
|
__IO uint32_t LCKR;
|
| 375 |
|
|
__IO uint32_t AFR[2];
|
| 376 |
|
|
} GPIO_TypeDef;
|
| 377 |
|
|
|
| 378 |
|
|
/**
|
| 379 |
|
|
* @brief SysTem Configuration
|
| 380 |
|
|
*/
|
| 381 |
|
|
|
| 382 |
|
|
typedef struct
|
| 383 |
|
|
{
|
| 384 |
|
|
__IO uint32_t MEMRMP;
|
| 385 |
|
|
__IO uint32_t PMC;
|
| 386 |
|
|
__IO uint32_t EXTICR[4];
|
| 387 |
|
|
} SYSCFG_TypeDef;
|
| 388 |
|
|
|
| 389 |
|
|
/**
|
| 390 |
|
|
* @brief Inter-integrated Circuit Interface
|
| 391 |
|
|
*/
|
| 392 |
|
|
|
| 393 |
|
|
typedef struct
|
| 394 |
|
|
{
|
| 395 |
|
|
__IO uint16_t CR1;
|
| 396 |
|
|
uint16_t RESERVED0;
|
| 397 |
|
|
__IO uint16_t CR2;
|
| 398 |
|
|
uint16_t RESERVED1;
|
| 399 |
|
|
__IO uint16_t OAR1;
|
| 400 |
|
|
uint16_t RESERVED2;
|
| 401 |
|
|
__IO uint16_t OAR2;
|
| 402 |
|
|
uint16_t RESERVED3;
|
| 403 |
|
|
__IO uint16_t DR;
|
| 404 |
|
|
uint16_t RESERVED4;
|
| 405 |
|
|
__IO uint16_t SR1;
|
| 406 |
|
|
uint16_t RESERVED5;
|
| 407 |
|
|
__IO uint16_t SR2;
|
| 408 |
|
|
uint16_t RESERVED6;
|
| 409 |
|
|
__IO uint16_t CCR;
|
| 410 |
|
|
uint16_t RESERVED7;
|
| 411 |
|
|
__IO uint16_t TRISE;
|
| 412 |
|
|
uint16_t RESERVED8;
|
| 413 |
|
|
} I2C_TypeDef;
|
| 414 |
|
|
|
| 415 |
|
|
/**
|
| 416 |
|
|
* @brief Independent WATCHDOG
|
| 417 |
|
|
*/
|
| 418 |
|
|
|
| 419 |
|
|
typedef struct
|
| 420 |
|
|
{
|
| 421 |
|
|
__IO uint32_t KR;
|
| 422 |
|
|
__IO uint32_t PR;
|
| 423 |
|
|
__IO uint32_t RLR;
|
| 424 |
|
|
__IO uint32_t SR;
|
| 425 |
|
|
} IWDG_TypeDef;
|
| 426 |
|
|
|
| 427 |
|
|
|
| 428 |
|
|
/**
|
| 429 |
|
|
* @brief LCD
|
| 430 |
|
|
*/
|
| 431 |
|
|
|
| 432 |
|
|
typedef struct
|
| 433 |
|
|
{
|
| 434 |
|
|
__IO uint32_t CR;
|
| 435 |
|
|
__IO uint32_t FCR;
|
| 436 |
|
|
__IO uint32_t SR;
|
| 437 |
|
|
__IO uint32_t CLR;
|
| 438 |
|
|
uint32_t RESERVED;
|
| 439 |
|
|
__IO uint32_t RAM[16];
|
| 440 |
|
|
} LCD_TypeDef;
|
| 441 |
|
|
|
| 442 |
|
|
/**
|
| 443 |
|
|
* @brief Power Control
|
| 444 |
|
|
*/
|
| 445 |
|
|
|
| 446 |
|
|
typedef struct
|
| 447 |
|
|
{
|
| 448 |
|
|
__IO uint32_t CR;
|
| 449 |
|
|
__IO uint32_t CSR;
|
| 450 |
|
|
} PWR_TypeDef;
|
| 451 |
|
|
|
| 452 |
|
|
/**
|
| 453 |
|
|
* @brief Reset and Clock Control
|
| 454 |
|
|
*/
|
| 455 |
|
|
|
| 456 |
|
|
typedef struct
|
| 457 |
|
|
{
|
| 458 |
|
|
__IO uint32_t CR;
|
| 459 |
|
|
__IO uint32_t ICSCR;
|
| 460 |
|
|
__IO uint32_t CFGR;
|
| 461 |
|
|
__IO uint32_t CIR;
|
| 462 |
|
|
__IO uint32_t AHBRSTR;
|
| 463 |
|
|
__IO uint32_t APB2RSTR;
|
| 464 |
|
|
__IO uint32_t APB1RSTR;
|
| 465 |
|
|
__IO uint32_t AHBENR;
|
| 466 |
|
|
__IO uint32_t APB2ENR;
|
| 467 |
|
|
__IO uint32_t APB1ENR;
|
| 468 |
|
|
__IO uint32_t AHBLPENR;
|
| 469 |
|
|
__IO uint32_t APB2LPENR;
|
| 470 |
|
|
__IO uint32_t APB1LPENR;
|
| 471 |
|
|
__IO uint32_t CSR;
|
| 472 |
|
|
} RCC_TypeDef;
|
| 473 |
|
|
|
| 474 |
|
|
/**
|
| 475 |
|
|
* @brief Routing Interface
|
| 476 |
|
|
*/
|
| 477 |
|
|
|
| 478 |
|
|
typedef struct
|
| 479 |
|
|
{
|
| 480 |
|
|
__IO uint32_t ICR;
|
| 481 |
|
|
__IO uint32_t ASCR1;
|
| 482 |
|
|
__IO uint32_t ASCR2;
|
| 483 |
|
|
__IO uint32_t HYSCR1;
|
| 484 |
|
|
__IO uint32_t HYSCR2;
|
| 485 |
|
|
__IO uint32_t HYSCR3;
|
| 486 |
|
|
} RI_TypeDef;
|
| 487 |
|
|
|
| 488 |
|
|
/**
|
| 489 |
|
|
* @brief Real-Time Clock
|
| 490 |
|
|
*/
|
| 491 |
|
|
|
| 492 |
|
|
typedef struct
|
| 493 |
|
|
{
|
| 494 |
|
|
__IO uint32_t TR;
|
| 495 |
|
|
__IO uint32_t DR;
|
| 496 |
|
|
__IO uint32_t CR;
|
| 497 |
|
|
__IO uint32_t ISR;
|
| 498 |
|
|
__IO uint32_t PRER;
|
| 499 |
|
|
__IO uint32_t WUTR;
|
| 500 |
|
|
__IO uint32_t CALIBR;
|
| 501 |
|
|
__IO uint32_t ALRMAR;
|
| 502 |
|
|
__IO uint32_t ALRMBR;
|
| 503 |
|
|
__IO uint32_t WRP;
|
| 504 |
|
|
uint32_t RESERVED1;
|
| 505 |
|
|
uint32_t RESERVED2;
|
| 506 |
|
|
__IO uint32_t TSTR;
|
| 507 |
|
|
__IO uint32_t TSDR;
|
| 508 |
|
|
uint32_t RESERVED3;
|
| 509 |
|
|
uint32_t RESERVED4;
|
| 510 |
|
|
__IO uint32_t TAFCR;
|
| 511 |
|
|
uint32_t RESERVED5;
|
| 512 |
|
|
uint32_t RESERVED6;
|
| 513 |
|
|
uint32_t RESERVED7;
|
| 514 |
|
|
__IO uint32_t BK0R;
|
| 515 |
|
|
__IO uint32_t BK1R;
|
| 516 |
|
|
__IO uint32_t BK2R;
|
| 517 |
|
|
__IO uint32_t BK3R;
|
| 518 |
|
|
__IO uint32_t BK4R;
|
| 519 |
|
|
__IO uint32_t BK5R;
|
| 520 |
|
|
__IO uint32_t BK6R;
|
| 521 |
|
|
__IO uint32_t BK7R;
|
| 522 |
|
|
__IO uint32_t BK8R;
|
| 523 |
|
|
__IO uint32_t BK9R;
|
| 524 |
|
|
__IO uint32_t BK10R;
|
| 525 |
|
|
__IO uint32_t BK11R;
|
| 526 |
|
|
__IO uint32_t BK12R;
|
| 527 |
|
|
__IO uint32_t BK13R;
|
| 528 |
|
|
__IO uint32_t BK14R;
|
| 529 |
|
|
__IO uint32_t BK15R;
|
| 530 |
|
|
__IO uint32_t BK16R;
|
| 531 |
|
|
__IO uint32_t BK17R;
|
| 532 |
|
|
__IO uint32_t BK18R;
|
| 533 |
|
|
__IO uint32_t BK19R;
|
| 534 |
|
|
} RTC_TypeDef;
|
| 535 |
|
|
|
| 536 |
|
|
/**
|
| 537 |
|
|
* @brief Serial Peripheral Interface
|
| 538 |
|
|
*/
|
| 539 |
|
|
|
| 540 |
|
|
typedef struct
|
| 541 |
|
|
{
|
| 542 |
|
|
__IO uint16_t CR1;
|
| 543 |
|
|
uint16_t RESERVED0;
|
| 544 |
|
|
__IO uint16_t CR2;
|
| 545 |
|
|
uint16_t RESERVED1;
|
| 546 |
|
|
__IO uint16_t SR;
|
| 547 |
|
|
uint16_t RESERVED2;
|
| 548 |
|
|
__IO uint16_t DR;
|
| 549 |
|
|
uint16_t RESERVED3;
|
| 550 |
|
|
__IO uint16_t CRCPR;
|
| 551 |
|
|
uint16_t RESERVED4;
|
| 552 |
|
|
__IO uint16_t RXCRCR;
|
| 553 |
|
|
uint16_t RESERVED5;
|
| 554 |
|
|
__IO uint16_t TXCRCR;
|
| 555 |
|
|
uint16_t RESERVED6;
|
| 556 |
|
|
} SPI_TypeDef;
|
| 557 |
|
|
|
| 558 |
|
|
/**
|
| 559 |
|
|
* @brief TIM
|
| 560 |
|
|
*/
|
| 561 |
|
|
|
| 562 |
|
|
typedef struct
|
| 563 |
|
|
{
|
| 564 |
|
|
__IO uint16_t CR1;
|
| 565 |
|
|
uint16_t RESERVED0;
|
| 566 |
|
|
__IO uint16_t CR2;
|
| 567 |
|
|
uint16_t RESERVED1;
|
| 568 |
|
|
__IO uint16_t SMCR;
|
| 569 |
|
|
uint16_t RESERVED2;
|
| 570 |
|
|
__IO uint16_t DIER;
|
| 571 |
|
|
uint16_t RESERVED3;
|
| 572 |
|
|
__IO uint16_t SR;
|
| 573 |
|
|
uint16_t RESERVED4;
|
| 574 |
|
|
__IO uint16_t EGR;
|
| 575 |
|
|
uint16_t RESERVED5;
|
| 576 |
|
|
__IO uint16_t CCMR1;
|
| 577 |
|
|
uint16_t RESERVED6;
|
| 578 |
|
|
__IO uint16_t CCMR2;
|
| 579 |
|
|
uint16_t RESERVED7;
|
| 580 |
|
|
__IO uint16_t CCER;
|
| 581 |
|
|
uint16_t RESERVED8;
|
| 582 |
|
|
__IO uint16_t CNT;
|
| 583 |
|
|
uint16_t RESERVED9;
|
| 584 |
|
|
__IO uint16_t PSC;
|
| 585 |
|
|
uint16_t RESERVED10;
|
| 586 |
|
|
__IO uint16_t ARR;
|
| 587 |
|
|
uint16_t RESERVED11;
|
| 588 |
|
|
uint32_t RESERVED12;
|
| 589 |
|
|
__IO uint16_t CCR1;
|
| 590 |
|
|
uint16_t RESERVED13;
|
| 591 |
|
|
__IO uint16_t CCR2;
|
| 592 |
|
|
uint16_t RESERVED14;
|
| 593 |
|
|
__IO uint16_t CCR3;
|
| 594 |
|
|
uint16_t RESERVED15;
|
| 595 |
|
|
__IO uint16_t CCR4;
|
| 596 |
|
|
uint16_t RESERVED16;
|
| 597 |
|
|
uint32_t RESERVED17;
|
| 598 |
|
|
__IO uint16_t DCR;
|
| 599 |
|
|
uint16_t RESERVED18;
|
| 600 |
|
|
__IO uint16_t DMAR;
|
| 601 |
|
|
uint16_t RESERVED19;
|
| 602 |
|
|
__IO uint16_t OR;
|
| 603 |
|
|
uint16_t RESERVED20;
|
| 604 |
|
|
} TIM_TypeDef;
|
| 605 |
|
|
|
| 606 |
|
|
/**
|
| 607 |
|
|
* @brief Universal Synchronous Asynchronous Receiver Transmitter
|
| 608 |
|
|
*/
|
| 609 |
|
|
|
| 610 |
|
|
typedef struct
|
| 611 |
|
|
{
|
| 612 |
|
|
__IO uint16_t SR;
|
| 613 |
|
|
uint16_t RESERVED0;
|
| 614 |
|
|
__IO uint16_t DR;
|
| 615 |
|
|
uint16_t RESERVED1;
|
| 616 |
|
|
__IO uint16_t BRR;
|
| 617 |
|
|
uint16_t RESERVED2;
|
| 618 |
|
|
__IO uint16_t CR1;
|
| 619 |
|
|
uint16_t RESERVED3;
|
| 620 |
|
|
__IO uint16_t CR2;
|
| 621 |
|
|
uint16_t RESERVED4;
|
| 622 |
|
|
__IO uint16_t CR3;
|
| 623 |
|
|
uint16_t RESERVED5;
|
| 624 |
|
|
__IO uint16_t GTPR;
|
| 625 |
|
|
uint16_t RESERVED6;
|
| 626 |
|
|
} USART_TypeDef;
|
| 627 |
|
|
|
| 628 |
|
|
/**
|
| 629 |
|
|
* @brief Window WATCHDOG
|
| 630 |
|
|
*/
|
| 631 |
|
|
|
| 632 |
|
|
typedef struct
|
| 633 |
|
|
{
|
| 634 |
|
|
__IO uint32_t CR;
|
| 635 |
|
|
__IO uint32_t CFR;
|
| 636 |
|
|
__IO uint32_t SR;
|
| 637 |
|
|
} WWDG_TypeDef;
|
| 638 |
|
|
|
| 639 |
|
|
/**
|
| 640 |
|
|
* @}
|
| 641 |
|
|
*/
|
| 642 |
|
|
|
| 643 |
|
|
/** @addtogroup Peripheral_memory_map
|
| 644 |
|
|
* @{
|
| 645 |
|
|
*/
|
| 646 |
|
|
|
| 647 |
|
|
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
|
| 648 |
|
|
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
|
| 649 |
|
|
|
| 650 |
|
|
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */
|
| 651 |
|
|
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */
|
| 652 |
|
|
|
| 653 |
|
|
/*!< Peripheral memory map */
|
| 654 |
|
|
#define APB1PERIPH_BASE PERIPH_BASE
|
| 655 |
|
|
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
| 656 |
|
|
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
| 657 |
|
|
|
| 658 |
|
|
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
|
| 659 |
|
|
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
|
| 660 |
|
|
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
|
| 661 |
|
|
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
|
| 662 |
|
|
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
|
| 663 |
|
|
#define LCD_BASE (APB1PERIPH_BASE + 0x2400)
|
| 664 |
|
|
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
| 665 |
|
|
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
|
| 666 |
|
|
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
|
| 667 |
|
|
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
|
| 668 |
|
|
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
|
| 669 |
|
|
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
|
| 670 |
|
|
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
|
| 671 |
|
|
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
|
| 672 |
|
|
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
|
| 673 |
|
|
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
|
| 674 |
|
|
#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)
|
| 675 |
|
|
#define RI_BASE (APB1PERIPH_BASE + 0x7C04)
|
| 676 |
|
|
|
| 677 |
|
|
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
|
| 678 |
|
|
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
|
| 679 |
|
|
#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)
|
| 680 |
|
|
#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)
|
| 681 |
|
|
#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)
|
| 682 |
|
|
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
|
| 683 |
|
|
#define ADC_BASE (APB2PERIPH_BASE + 0x2700)
|
| 684 |
|
|
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
|
| 685 |
|
|
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
|
| 686 |
|
|
|
| 687 |
|
|
#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)
|
| 688 |
|
|
#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)
|
| 689 |
|
|
#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
|
| 690 |
|
|
#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)
|
| 691 |
|
|
#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)
|
| 692 |
|
|
#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)
|
| 693 |
|
|
#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
|
| 694 |
|
|
#define RCC_BASE (AHBPERIPH_BASE + 0x3800)
|
| 695 |
|
|
|
| 696 |
|
|
|
| 697 |
|
|
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
|
| 698 |
|
|
#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
|
| 699 |
|
|
|
| 700 |
|
|
#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)
|
| 701 |
|
|
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
|
| 702 |
|
|
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
|
| 703 |
|
|
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
|
| 704 |
|
|
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
|
| 705 |
|
|
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
|
| 706 |
|
|
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
|
| 707 |
|
|
#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
|
| 708 |
|
|
|
| 709 |
|
|
|
| 710 |
|
|
#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
|
| 711 |
|
|
|
| 712 |
|
|
/**
|
| 713 |
|
|
* @}
|
| 714 |
|
|
*/
|
| 715 |
|
|
|
| 716 |
|
|
/** @addtogroup Peripheral_declaration
|
| 717 |
|
|
* @{
|
| 718 |
|
|
*/
|
| 719 |
|
|
|
| 720 |
|
|
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
|
| 721 |
|
|
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
| 722 |
|
|
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
|
| 723 |
|
|
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
|
| 724 |
|
|
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
|
| 725 |
|
|
#define LCD ((LCD_TypeDef *) LCD_BASE)
|
| 726 |
|
|
#define RTC ((RTC_TypeDef *) RTC_BASE)
|
| 727 |
|
|
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
| 728 |
|
|
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
| 729 |
|
|
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
|
| 730 |
|
|
#define USART2 ((USART_TypeDef *) USART2_BASE)
|
| 731 |
|
|
#define USART3 ((USART_TypeDef *) USART3_BASE)
|
| 732 |
|
|
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
| 733 |
|
|
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
| 734 |
|
|
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
| 735 |
|
|
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
| 736 |
|
|
#define COMP ((COMP_TypeDef *) COMP_BASE)
|
| 737 |
|
|
#define RI ((RI_TypeDef *) RI_BASE)
|
| 738 |
|
|
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
| 739 |
|
|
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
| 740 |
|
|
|
| 741 |
|
|
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
| 742 |
|
|
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
|
| 743 |
|
|
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
|
| 744 |
|
|
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
|
| 745 |
|
|
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
|
| 746 |
|
|
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
| 747 |
|
|
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
| 748 |
|
|
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
| 749 |
|
|
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
|
| 750 |
|
|
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
|
| 751 |
|
|
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
|
| 752 |
|
|
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
|
| 753 |
|
|
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
|
| 754 |
|
|
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
|
| 755 |
|
|
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
|
| 756 |
|
|
#define RCC ((RCC_TypeDef *) RCC_BASE)
|
| 757 |
|
|
#define CRC ((CRC_TypeDef *) CRC_BASE)
|
| 758 |
|
|
|
| 759 |
|
|
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
| 760 |
|
|
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
| 761 |
|
|
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
| 762 |
|
|
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
| 763 |
|
|
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
| 764 |
|
|
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
|
| 765 |
|
|
|
| 766 |
|
|
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
| 767 |
|
|
#define OB ((OB_TypeDef *) OB_BASE)
|
| 768 |
|
|
|
| 769 |
|
|
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
| 770 |
|
|
|
| 771 |
|
|
/**
|
| 772 |
|
|
* @}
|
| 773 |
|
|
*/
|
| 774 |
|
|
|
| 775 |
|
|
/** @addtogroup Exported_constants
|
| 776 |
|
|
* @{
|
| 777 |
|
|
*/
|
| 778 |
|
|
|
| 779 |
|
|
/** @addtogroup Peripheral_Registers_Bits_Definition
|
| 780 |
|
|
* @{
|
| 781 |
|
|
*/
|
| 782 |
|
|
|
| 783 |
|
|
/******************************************************************************/
|
| 784 |
|
|
/* Peripheral Registers_Bits_Definition */
|
| 785 |
|
|
/******************************************************************************/
|
| 786 |
|
|
/******************************************************************************/
|
| 787 |
|
|
/* */
|
| 788 |
|
|
/* Analog to Digital Converter */
|
| 789 |
|
|
/* */
|
| 790 |
|
|
/******************************************************************************/
|
| 791 |
|
|
|
| 792 |
|
|
/******************** Bit definition for ADC_SR register ********************/
|
| 793 |
|
|
#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
|
| 794 |
|
|
#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
|
| 795 |
|
|
#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
|
| 796 |
|
|
#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
|
| 797 |
|
|
#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
|
| 798 |
|
|
#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
|
| 799 |
|
|
#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
|
| 800 |
|
|
#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
|
| 801 |
|
|
#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
|
| 802 |
|
|
|
| 803 |
|
|
/******************* Bit definition for ADC_CR1 register ********************/
|
| 804 |
|
|
#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
|
| 805 |
|
|
#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 806 |
|
|
#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 807 |
|
|
#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 808 |
|
|
#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 809 |
|
|
#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 810 |
|
|
|
| 811 |
|
|
#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
|
| 812 |
|
|
#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
|
| 813 |
|
|
#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
|
| 814 |
|
|
#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
|
| 815 |
|
|
#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
|
| 816 |
|
|
#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
|
| 817 |
|
|
#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
|
| 818 |
|
|
#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
|
| 819 |
|
|
|
| 820 |
|
|
#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
|
| 821 |
|
|
#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
|
| 822 |
|
|
#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
|
| 823 |
|
|
#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
|
| 824 |
|
|
|
| 825 |
|
|
#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
|
| 826 |
|
|
#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
|
| 827 |
|
|
|
| 828 |
|
|
#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
|
| 829 |
|
|
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
|
| 830 |
|
|
|
| 831 |
|
|
#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
|
| 832 |
|
|
#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
| 833 |
|
|
#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
| 834 |
|
|
|
| 835 |
|
|
#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
|
| 836 |
|
|
|
| 837 |
|
|
/******************* Bit definition for ADC_CR2 register ********************/
|
| 838 |
|
|
#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
|
| 839 |
|
|
#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
|
| 840 |
|
|
|
| 841 |
|
|
#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
|
| 842 |
|
|
#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
| 843 |
|
|
#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
| 844 |
|
|
#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
| 845 |
|
|
|
| 846 |
|
|
#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
|
| 847 |
|
|
#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
|
| 848 |
|
|
#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
|
| 849 |
|
|
#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
|
| 850 |
|
|
|
| 851 |
|
|
#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
|
| 852 |
|
|
#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
| 853 |
|
|
#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
| 854 |
|
|
#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
|
| 855 |
|
|
#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
|
| 856 |
|
|
|
| 857 |
|
|
#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
|
| 858 |
|
|
#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
| 859 |
|
|
#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
| 860 |
|
|
|
| 861 |
|
|
#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
|
| 862 |
|
|
|
| 863 |
|
|
#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
|
| 864 |
|
|
#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
| 865 |
|
|
#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
| 866 |
|
|
#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
| 867 |
|
|
#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
|
| 868 |
|
|
|
| 869 |
|
|
#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
|
| 870 |
|
|
#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
|
| 871 |
|
|
#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
|
| 872 |
|
|
|
| 873 |
|
|
#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
|
| 874 |
|
|
|
| 875 |
|
|
/****************** Bit definition for ADC_SMPR1 register *******************/
|
| 876 |
|
|
#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
|
| 877 |
|
|
#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 878 |
|
|
#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 879 |
|
|
#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 880 |
|
|
|
| 881 |
|
|
#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
|
| 882 |
|
|
#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
|
| 883 |
|
|
#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
|
| 884 |
|
|
#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
|
| 885 |
|
|
|
| 886 |
|
|
#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
|
| 887 |
|
|
#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
|
| 888 |
|
|
#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
|
| 889 |
|
|
#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
|
| 890 |
|
|
|
| 891 |
|
|
#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
|
| 892 |
|
|
#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
|
| 893 |
|
|
#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
|
| 894 |
|
|
#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
|
| 895 |
|
|
|
| 896 |
|
|
#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
|
| 897 |
|
|
#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
|
| 898 |
|
|
#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
|
| 899 |
|
|
#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
|
| 900 |
|
|
|
| 901 |
|
|
#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
|
| 902 |
|
|
#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
|
| 903 |
|
|
#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
|
| 904 |
|
|
#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
|
| 905 |
|
|
|
| 906 |
|
|
/****************** Bit definition for ADC_SMPR2 register *******************/
|
| 907 |
|
|
#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
|
| 908 |
|
|
#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 909 |
|
|
#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 910 |
|
|
#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 911 |
|
|
|
| 912 |
|
|
#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
|
| 913 |
|
|
#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
|
| 914 |
|
|
#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
|
| 915 |
|
|
#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
|
| 916 |
|
|
|
| 917 |
|
|
#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
|
| 918 |
|
|
#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
|
| 919 |
|
|
#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
|
| 920 |
|
|
#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
|
| 921 |
|
|
|
| 922 |
|
|
#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
|
| 923 |
|
|
#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
|
| 924 |
|
|
#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
|
| 925 |
|
|
#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
|
| 926 |
|
|
|
| 927 |
|
|
#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
|
| 928 |
|
|
#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
|
| 929 |
|
|
#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
|
| 930 |
|
|
#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
|
| 931 |
|
|
|
| 932 |
|
|
#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
|
| 933 |
|
|
#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
|
| 934 |
|
|
#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
|
| 935 |
|
|
#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
|
| 936 |
|
|
|
| 937 |
|
|
#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
|
| 938 |
|
|
#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
| 939 |
|
|
#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
| 940 |
|
|
#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
|
| 941 |
|
|
|
| 942 |
|
|
#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
|
| 943 |
|
|
#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
|
| 944 |
|
|
#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
|
| 945 |
|
|
#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
|
| 946 |
|
|
|
| 947 |
|
|
#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
|
| 948 |
|
|
#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
| 949 |
|
|
#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
| 950 |
|
|
#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
| 951 |
|
|
|
| 952 |
|
|
#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
|
| 953 |
|
|
#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
|
| 954 |
|
|
#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
|
| 955 |
|
|
#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
|
| 956 |
|
|
|
| 957 |
|
|
/****************** Bit definition for ADC_SMPR3 register *******************/
|
| 958 |
|
|
#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
|
| 959 |
|
|
#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 960 |
|
|
#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 961 |
|
|
#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 962 |
|
|
|
| 963 |
|
|
#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
|
| 964 |
|
|
#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
|
| 965 |
|
|
#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
|
| 966 |
|
|
#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
|
| 967 |
|
|
|
| 968 |
|
|
#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
|
| 969 |
|
|
#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
|
| 970 |
|
|
#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
|
| 971 |
|
|
#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
|
| 972 |
|
|
|
| 973 |
|
|
#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
|
| 974 |
|
|
#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
|
| 975 |
|
|
#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
|
| 976 |
|
|
#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
|
| 977 |
|
|
|
| 978 |
|
|
#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
|
| 979 |
|
|
#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
|
| 980 |
|
|
#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
|
| 981 |
|
|
#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
|
| 982 |
|
|
|
| 983 |
|
|
#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
|
| 984 |
|
|
#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
|
| 985 |
|
|
#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
|
| 986 |
|
|
#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
|
| 987 |
|
|
|
| 988 |
|
|
#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
|
| 989 |
|
|
#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
| 990 |
|
|
#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
| 991 |
|
|
#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
|
| 992 |
|
|
|
| 993 |
|
|
#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
|
| 994 |
|
|
#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
|
| 995 |
|
|
#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
|
| 996 |
|
|
#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
|
| 997 |
|
|
|
| 998 |
|
|
#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
|
| 999 |
|
|
#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
| 1000 |
|
|
#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
| 1001 |
|
|
#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
| 1002 |
|
|
|
| 1003 |
|
|
#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
|
| 1004 |
|
|
#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
|
| 1005 |
|
|
#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
|
| 1006 |
|
|
#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
|
| 1007 |
|
|
|
| 1008 |
|
|
|
| 1009 |
|
|
/****************** Bit definition for ADC_JOFR1 register *******************/
|
| 1010 |
|
|
#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
|
| 1011 |
|
|
|
| 1012 |
|
|
/****************** Bit definition for ADC_JOFR2 register *******************/
|
| 1013 |
|
|
#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
|
| 1014 |
|
|
|
| 1015 |
|
|
/****************** Bit definition for ADC_JOFR3 register *******************/
|
| 1016 |
|
|
#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
|
| 1017 |
|
|
|
| 1018 |
|
|
/****************** Bit definition for ADC_JOFR4 register *******************/
|
| 1019 |
|
|
#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
|
| 1020 |
|
|
|
| 1021 |
|
|
/******************* Bit definition for ADC_HTR register ********************/
|
| 1022 |
|
|
#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
|
| 1023 |
|
|
|
| 1024 |
|
|
/******************* Bit definition for ADC_LTR register ********************/
|
| 1025 |
|
|
#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
|
| 1026 |
|
|
|
| 1027 |
|
|
/******************* Bit definition for ADC_SQR1 register *******************/
|
| 1028 |
|
|
#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
|
| 1029 |
|
|
#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 1030 |
|
|
#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 1031 |
|
|
#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 1032 |
|
|
#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 1033 |
|
|
#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 1034 |
|
|
|
| 1035 |
|
|
#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
|
| 1036 |
|
|
#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
|
| 1037 |
|
|
#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
|
| 1038 |
|
|
#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
|
| 1039 |
|
|
#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
|
| 1040 |
|
|
#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
|
| 1041 |
|
|
|
| 1042 |
|
|
#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
|
| 1043 |
|
|
#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 1044 |
|
|
#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 1045 |
|
|
#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 1046 |
|
|
#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 1047 |
|
|
#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 1048 |
|
|
|
| 1049 |
|
|
#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
|
| 1050 |
|
|
#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
| 1051 |
|
|
#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
| 1052 |
|
|
#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
|
| 1053 |
|
|
#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
|
| 1054 |
|
|
|
| 1055 |
|
|
/******************* Bit definition for ADC_SQR2 register *******************/
|
| 1056 |
|
|
#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
|
| 1057 |
|
|
#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 1058 |
|
|
#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 1059 |
|
|
#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 1060 |
|
|
#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 1061 |
|
|
#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 1062 |
|
|
|
| 1063 |
|
|
#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
|
| 1064 |
|
|
#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
|
| 1065 |
|
|
#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
|
| 1066 |
|
|
#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
|
| 1067 |
|
|
#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
|
| 1068 |
|
|
#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
|
| 1069 |
|
|
|
| 1070 |
|
|
#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
|
| 1071 |
|
|
#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 1072 |
|
|
#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 1073 |
|
|
#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 1074 |
|
|
#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 1075 |
|
|
#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 1076 |
|
|
|
| 1077 |
|
|
#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
|
| 1078 |
|
|
#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
|
| 1079 |
|
|
#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
|
| 1080 |
|
|
#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
|
| 1081 |
|
|
#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
|
| 1082 |
|
|
#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
|
| 1083 |
|
|
|
| 1084 |
|
|
#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
|
| 1085 |
|
|
#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
| 1086 |
|
|
#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
| 1087 |
|
|
#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
|
| 1088 |
|
|
#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
|
| 1089 |
|
|
#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
|
| 1090 |
|
|
|
| 1091 |
|
|
#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
|
| 1092 |
|
|
#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
|
| 1093 |
|
|
#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
|
| 1094 |
|
|
#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
|
| 1095 |
|
|
#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
|
| 1096 |
|
|
#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
|
| 1097 |
|
|
|
| 1098 |
|
|
/******************* Bit definition for ADC_SQR3 register *******************/
|
| 1099 |
|
|
#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
|
| 1100 |
|
|
#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 1101 |
|
|
#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 1102 |
|
|
#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 1103 |
|
|
#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 1104 |
|
|
#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 1105 |
|
|
|
| 1106 |
|
|
#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
|
| 1107 |
|
|
#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
|
| 1108 |
|
|
#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
|
| 1109 |
|
|
#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
|
| 1110 |
|
|
#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
|
| 1111 |
|
|
#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
|
| 1112 |
|
|
|
| 1113 |
|
|
#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
|
| 1114 |
|
|
#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 1115 |
|
|
#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 1116 |
|
|
#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 1117 |
|
|
#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 1118 |
|
|
#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 1119 |
|
|
|
| 1120 |
|
|
#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
|
| 1121 |
|
|
#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
|
| 1122 |
|
|
#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
|
| 1123 |
|
|
#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
|
| 1124 |
|
|
#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
|
| 1125 |
|
|
#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
|
| 1126 |
|
|
|
| 1127 |
|
|
#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
|
| 1128 |
|
|
#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
| 1129 |
|
|
#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
| 1130 |
|
|
#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
|
| 1131 |
|
|
#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
|
| 1132 |
|
|
#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
|
| 1133 |
|
|
|
| 1134 |
|
|
#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
|
| 1135 |
|
|
#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
|
| 1136 |
|
|
#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
|
| 1137 |
|
|
#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
|
| 1138 |
|
|
#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
|
| 1139 |
|
|
#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
|
| 1140 |
|
|
|
| 1141 |
|
|
/******************* Bit definition for ADC_SQR4 register *******************/
|
| 1142 |
|
|
#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
|
| 1143 |
|
|
#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 1144 |
|
|
#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 1145 |
|
|
#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 1146 |
|
|
#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 1147 |
|
|
#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 1148 |
|
|
|
| 1149 |
|
|
#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
|
| 1150 |
|
|
#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
|
| 1151 |
|
|
#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
|
| 1152 |
|
|
#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
|
| 1153 |
|
|
#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
|
| 1154 |
|
|
#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
|
| 1155 |
|
|
|
| 1156 |
|
|
#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
|
| 1157 |
|
|
#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 1158 |
|
|
#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 1159 |
|
|
#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 1160 |
|
|
#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 1161 |
|
|
#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 1162 |
|
|
|
| 1163 |
|
|
#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
|
| 1164 |
|
|
#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
|
| 1165 |
|
|
#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
|
| 1166 |
|
|
#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
|
| 1167 |
|
|
#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
|
| 1168 |
|
|
#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
|
| 1169 |
|
|
|
| 1170 |
|
|
#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
|
| 1171 |
|
|
#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
| 1172 |
|
|
#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
| 1173 |
|
|
#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
|
| 1174 |
|
|
#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
|
| 1175 |
|
|
#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
|
| 1176 |
|
|
|
| 1177 |
|
|
#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
|
| 1178 |
|
|
#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
|
| 1179 |
|
|
#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
|
| 1180 |
|
|
#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
|
| 1181 |
|
|
#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
|
| 1182 |
|
|
#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
|
| 1183 |
|
|
|
| 1184 |
|
|
/******************* Bit definition for ADC_SQR5 register *******************/
|
| 1185 |
|
|
#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
|
| 1186 |
|
|
#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 1187 |
|
|
#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 1188 |
|
|
#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 1189 |
|
|
#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 1190 |
|
|
#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 1191 |
|
|
|
| 1192 |
|
|
#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
|
| 1193 |
|
|
#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
|
| 1194 |
|
|
#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
|
| 1195 |
|
|
#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
|
| 1196 |
|
|
#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
|
| 1197 |
|
|
#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
|
| 1198 |
|
|
|
| 1199 |
|
|
#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
|
| 1200 |
|
|
#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 1201 |
|
|
#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 1202 |
|
|
#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 1203 |
|
|
#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 1204 |
|
|
#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 1205 |
|
|
|
| 1206 |
|
|
#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
|
| 1207 |
|
|
#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
|
| 1208 |
|
|
#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
|
| 1209 |
|
|
#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
|
| 1210 |
|
|
#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
|
| 1211 |
|
|
#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
|
| 1212 |
|
|
|
| 1213 |
|
|
#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
|
| 1214 |
|
|
#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
| 1215 |
|
|
#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
| 1216 |
|
|
#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
|
| 1217 |
|
|
#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
|
| 1218 |
|
|
#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
|
| 1219 |
|
|
|
| 1220 |
|
|
#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
|
| 1221 |
|
|
#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
|
| 1222 |
|
|
#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
|
| 1223 |
|
|
#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
|
| 1224 |
|
|
#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
|
| 1225 |
|
|
#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
|
| 1226 |
|
|
|
| 1227 |
|
|
|
| 1228 |
|
|
/******************* Bit definition for ADC_JSQR register *******************/
|
| 1229 |
|
|
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
|
| 1230 |
|
|
#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 1231 |
|
|
#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 1232 |
|
|
#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 1233 |
|
|
#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 1234 |
|
|
#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 1235 |
|
|
|
| 1236 |
|
|
#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
|
| 1237 |
|
|
#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
|
| 1238 |
|
|
#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
|
| 1239 |
|
|
#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
|
| 1240 |
|
|
#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
|
| 1241 |
|
|
#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
|
| 1242 |
|
|
|
| 1243 |
|
|
#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
|
| 1244 |
|
|
#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 1245 |
|
|
#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 1246 |
|
|
#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 1247 |
|
|
#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 1248 |
|
|
#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 1249 |
|
|
|
| 1250 |
|
|
#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
|
| 1251 |
|
|
#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
|
| 1252 |
|
|
#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
|
| 1253 |
|
|
#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
|
| 1254 |
|
|
#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
|
| 1255 |
|
|
#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
|
| 1256 |
|
|
|
| 1257 |
|
|
#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
|
| 1258 |
|
|
#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
| 1259 |
|
|
#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
| 1260 |
|
|
|
| 1261 |
|
|
/******************* Bit definition for ADC_JDR1 register *******************/
|
| 1262 |
|
|
#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
|
| 1263 |
|
|
|
| 1264 |
|
|
/******************* Bit definition for ADC_JDR2 register *******************/
|
| 1265 |
|
|
#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
|
| 1266 |
|
|
|
| 1267 |
|
|
/******************* Bit definition for ADC_JDR3 register *******************/
|
| 1268 |
|
|
#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
|
| 1269 |
|
|
|
| 1270 |
|
|
/******************* Bit definition for ADC_JDR4 register *******************/
|
| 1271 |
|
|
#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
|
| 1272 |
|
|
|
| 1273 |
|
|
/******************** Bit definition for ADC_DR register ********************/
|
| 1274 |
|
|
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
|
| 1275 |
|
|
|
| 1276 |
|
|
|
| 1277 |
|
|
/******************* Bit definition for ADC_CSR register ********************/
|
| 1278 |
|
|
#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
|
| 1279 |
|
|
#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
|
| 1280 |
|
|
#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
|
| 1281 |
|
|
#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
|
| 1282 |
|
|
#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
|
| 1283 |
|
|
#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
|
| 1284 |
|
|
#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
|
| 1285 |
|
|
|
| 1286 |
|
|
/******************* Bit definition for ADC_CCR register ********************/
|
| 1287 |
|
|
#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
|
| 1288 |
|
|
#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
| 1289 |
|
|
#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
| 1290 |
|
|
#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
|
| 1291 |
|
|
|
| 1292 |
|
|
/******************************************************************************/
|
| 1293 |
|
|
/* */
|
| 1294 |
|
|
/* Comparator */
|
| 1295 |
|
|
/* */
|
| 1296 |
|
|
/******************************************************************************/
|
| 1297 |
|
|
|
| 1298 |
|
|
/****************** Bit definition for COMP_CSR register ********************/
|
| 1299 |
|
|
#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
|
| 1300 |
|
|
#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
|
| 1301 |
|
|
#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
|
| 1302 |
|
|
#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
|
| 1303 |
|
|
|
| 1304 |
|
|
#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
|
| 1305 |
|
|
#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
|
| 1306 |
|
|
|
| 1307 |
|
|
#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
|
| 1308 |
|
|
#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
|
| 1309 |
|
|
|
| 1310 |
|
|
#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
|
| 1311 |
|
|
#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
|
| 1312 |
|
|
|
| 1313 |
|
|
#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
|
| 1314 |
|
|
#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
| 1315 |
|
|
#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
| 1316 |
|
|
#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
|
| 1317 |
|
|
|
| 1318 |
|
|
#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
|
| 1319 |
|
|
#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
|
| 1320 |
|
|
#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
|
| 1321 |
|
|
#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
|
| 1322 |
|
|
|
| 1323 |
|
|
/******************************************************************************/
|
| 1324 |
|
|
/* */
|
| 1325 |
|
|
/* CRC calculation unit */
|
| 1326 |
|
|
/* */
|
| 1327 |
|
|
/******************************************************************************/
|
| 1328 |
|
|
|
| 1329 |
|
|
/******************* Bit definition for CRC_DR register *********************/
|
| 1330 |
|
|
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
| 1331 |
|
|
|
| 1332 |
|
|
/******************* Bit definition for CRC_IDR register ********************/
|
| 1333 |
|
|
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
| 1334 |
|
|
|
| 1335 |
|
|
/******************** Bit definition for CRC_CR register ********************/
|
| 1336 |
|
|
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
|
| 1337 |
|
|
|
| 1338 |
|
|
/******************************************************************************/
|
| 1339 |
|
|
/* */
|
| 1340 |
|
|
/* Digital to Analog Converter */
|
| 1341 |
|
|
/* */
|
| 1342 |
|
|
/******************************************************************************/
|
| 1343 |
|
|
|
| 1344 |
|
|
/******************** Bit definition for DAC_CR register ********************/
|
| 1345 |
|
|
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
|
| 1346 |
|
|
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
|
| 1347 |
|
|
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
|
| 1348 |
|
|
|
| 1349 |
|
|
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
|
| 1350 |
|
|
#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
| 1351 |
|
|
#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
| 1352 |
|
|
#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
| 1353 |
|
|
|
| 1354 |
|
|
#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
|
| 1355 |
|
|
#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
| 1356 |
|
|
#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
| 1357 |
|
|
|
| 1358 |
|
|
#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
|
| 1359 |
|
|
#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
| 1360 |
|
|
#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
| 1361 |
|
|
#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
| 1362 |
|
|
#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
| 1363 |
|
|
|
| 1364 |
|
|
#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
|
| 1365 |
|
|
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
|
| 1366 |
|
|
#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
|
| 1367 |
|
|
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
|
| 1368 |
|
|
|
| 1369 |
|
|
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
|
| 1370 |
|
|
#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
|
| 1371 |
|
|
#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
|
| 1372 |
|
|
#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
|
| 1373 |
|
|
|
| 1374 |
|
|
#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
|
| 1375 |
|
|
#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
| 1376 |
|
|
#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
| 1377 |
|
|
|
| 1378 |
|
|
#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
|
| 1379 |
|
|
#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
| 1380 |
|
|
#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
| 1381 |
|
|
#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
| 1382 |
|
|
#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
| 1383 |
|
|
|
| 1384 |
|
|
#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
|
| 1385 |
|
|
|
| 1386 |
|
|
/***************** Bit definition for DAC_SWTRIGR register ******************/
|
| 1387 |
|
|
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
|
| 1388 |
|
|
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
|
| 1389 |
|
|
|
| 1390 |
|
|
/***************** Bit definition for DAC_DHR12R1 register ******************/
|
| 1391 |
|
|
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
|
| 1392 |
|
|
|
| 1393 |
|
|
/***************** Bit definition for DAC_DHR12L1 register ******************/
|
| 1394 |
|
|
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
|
| 1395 |
|
|
|
| 1396 |
|
|
/****************** Bit definition for DAC_DHR8R1 register ******************/
|
| 1397 |
|
|
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
|
| 1398 |
|
|
|
| 1399 |
|
|
/***************** Bit definition for DAC_DHR12R2 register ******************/
|
| 1400 |
|
|
#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
|
| 1401 |
|
|
|
| 1402 |
|
|
/***************** Bit definition for DAC_DHR12L2 register ******************/
|
| 1403 |
|
|
#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
|
| 1404 |
|
|
|
| 1405 |
|
|
/****************** Bit definition for DAC_DHR8R2 register ******************/
|
| 1406 |
|
|
#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
|
| 1407 |
|
|
|
| 1408 |
|
|
/***************** Bit definition for DAC_DHR12RD register ******************/
|
| 1409 |
|
|
#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
|
| 1410 |
|
|
#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
|
| 1411 |
|
|
|
| 1412 |
|
|
/***************** Bit definition for DAC_DHR12LD register ******************/
|
| 1413 |
|
|
#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
|
| 1414 |
|
|
#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
|
| 1415 |
|
|
|
| 1416 |
|
|
/****************** Bit definition for DAC_DHR8RD register ******************/
|
| 1417 |
|
|
#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
|
| 1418 |
|
|
#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
|
| 1419 |
|
|
|
| 1420 |
|
|
/******************* Bit definition for DAC_DOR1 register *******************/
|
| 1421 |
|
|
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
|
| 1422 |
|
|
|
| 1423 |
|
|
/******************* Bit definition for DAC_DOR2 register *******************/
|
| 1424 |
|
|
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
|
| 1425 |
|
|
|
| 1426 |
|
|
/******************** Bit definition for DAC_SR register ********************/
|
| 1427 |
|
|
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
|
| 1428 |
|
|
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
|
| 1429 |
|
|
|
| 1430 |
|
|
/******************************************************************************/
|
| 1431 |
|
|
/* */
|
| 1432 |
|
|
/* Debug MCU */
|
| 1433 |
|
|
/* */
|
| 1434 |
|
|
/******************************************************************************/
|
| 1435 |
|
|
|
| 1436 |
|
|
/**************** Bit definition for DBGMCU_IDCODE register *****************/
|
| 1437 |
|
|
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
|
| 1438 |
|
|
|
| 1439 |
|
|
#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
|
| 1440 |
|
|
#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
| 1441 |
|
|
#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
| 1442 |
|
|
#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
|
| 1443 |
|
|
#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
|
| 1444 |
|
|
#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
|
| 1445 |
|
|
#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
|
| 1446 |
|
|
#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
|
| 1447 |
|
|
#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
|
| 1448 |
|
|
#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
|
| 1449 |
|
|
#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
|
| 1450 |
|
|
#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
|
| 1451 |
|
|
#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
|
| 1452 |
|
|
#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
|
| 1453 |
|
|
#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
|
| 1454 |
|
|
#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
|
| 1455 |
|
|
#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
|
| 1456 |
|
|
|
| 1457 |
|
|
/****************** Bit definition for DBGMCU_CR register *******************/
|
| 1458 |
|
|
#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
|
| 1459 |
|
|
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
|
| 1460 |
|
|
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
|
| 1461 |
|
|
#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
|
| 1462 |
|
|
|
| 1463 |
|
|
#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
|
| 1464 |
|
|
#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
|
| 1465 |
|
|
#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
|
| 1466 |
|
|
|
| 1467 |
|
|
/****************** Bit definition for DBGMCU_APB1_FZ register **************/
|
| 1468 |
|
|
|
| 1469 |
|
|
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
|
| 1470 |
|
|
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
|
| 1471 |
|
|
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
|
| 1472 |
|
|
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
|
| 1473 |
|
|
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
|
| 1474 |
|
|
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
|
| 1475 |
|
|
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
|
| 1476 |
|
|
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
|
| 1477 |
|
|
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
|
| 1478 |
|
|
|
| 1479 |
|
|
/****************** Bit definition for DBGMCU_APB2_FZ register **************/
|
| 1480 |
|
|
|
| 1481 |
|
|
#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
|
| 1482 |
|
|
#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
|
| 1483 |
|
|
#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
|
| 1484 |
|
|
|
| 1485 |
|
|
/******************************************************************************/
|
| 1486 |
|
|
/* */
|
| 1487 |
|
|
/* DMA Controller */
|
| 1488 |
|
|
/* */
|
| 1489 |
|
|
/******************************************************************************/
|
| 1490 |
|
|
|
| 1491 |
|
|
/******************* Bit definition for DMA_ISR register ********************/
|
| 1492 |
|
|
#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
|
| 1493 |
|
|
#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
|
| 1494 |
|
|
#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
|
| 1495 |
|
|
#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
|
| 1496 |
|
|
#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
|
| 1497 |
|
|
#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
|
| 1498 |
|
|
#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
|
| 1499 |
|
|
#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
|
| 1500 |
|
|
#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
|
| 1501 |
|
|
#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
|
| 1502 |
|
|
#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
|
| 1503 |
|
|
#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
|
| 1504 |
|
|
#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
|
| 1505 |
|
|
#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
|
| 1506 |
|
|
#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
|
| 1507 |
|
|
#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
|
| 1508 |
|
|
#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
|
| 1509 |
|
|
#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
|
| 1510 |
|
|
#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
|
| 1511 |
|
|
#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
|
| 1512 |
|
|
#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
|
| 1513 |
|
|
#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
|
| 1514 |
|
|
#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
|
| 1515 |
|
|
#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
|
| 1516 |
|
|
#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
|
| 1517 |
|
|
#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
|
| 1518 |
|
|
#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
|
| 1519 |
|
|
#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
|
| 1520 |
|
|
|
| 1521 |
|
|
/******************* Bit definition for DMA_IFCR register *******************/
|
| 1522 |
|
|
#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
|
| 1523 |
|
|
#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
|
| 1524 |
|
|
#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
|
| 1525 |
|
|
#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
|
| 1526 |
|
|
#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
|
| 1527 |
|
|
#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
|
| 1528 |
|
|
#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
|
| 1529 |
|
|
#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
|
| 1530 |
|
|
#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
|
| 1531 |
|
|
#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
|
| 1532 |
|
|
#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
|
| 1533 |
|
|
#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
|
| 1534 |
|
|
#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
|
| 1535 |
|
|
#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
|
| 1536 |
|
|
#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
|
| 1537 |
|
|
#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
|
| 1538 |
|
|
#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
|
| 1539 |
|
|
#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
|
| 1540 |
|
|
#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
|
| 1541 |
|
|
#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
|
| 1542 |
|
|
#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
|
| 1543 |
|
|
#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
|
| 1544 |
|
|
#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
|
| 1545 |
|
|
#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
|
| 1546 |
|
|
#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
|
| 1547 |
|
|
#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
|
| 1548 |
|
|
#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
|
| 1549 |
|
|
#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
|
| 1550 |
|
|
|
| 1551 |
|
|
/******************* Bit definition for DMA_CCR1 register *******************/
|
| 1552 |
|
|
#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
|
| 1553 |
|
|
#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
|
| 1554 |
|
|
#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 1555 |
|
|
#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 1556 |
|
|
#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 1557 |
|
|
#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 1558 |
|
|
#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 1559 |
|
|
#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 1560 |
|
|
|
| 1561 |
|
|
#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 1562 |
|
|
#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 1563 |
|
|
#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 1564 |
|
|
|
| 1565 |
|
|
#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 1566 |
|
|
#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 1567 |
|
|
#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 1568 |
|
|
|
| 1569 |
|
|
#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
|
| 1570 |
|
|
#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 1571 |
|
|
#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 1572 |
|
|
|
| 1573 |
|
|
#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
|
| 1574 |
|
|
|
| 1575 |
|
|
/******************* Bit definition for DMA_CCR2 register *******************/
|
| 1576 |
|
|
#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
|
| 1577 |
|
|
#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
|
| 1578 |
|
|
#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 1579 |
|
|
#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 1580 |
|
|
#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 1581 |
|
|
#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 1582 |
|
|
#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 1583 |
|
|
#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 1584 |
|
|
|
| 1585 |
|
|
#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 1586 |
|
|
#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 1587 |
|
|
#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 1588 |
|
|
|
| 1589 |
|
|
#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 1590 |
|
|
#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 1591 |
|
|
#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 1592 |
|
|
|
| 1593 |
|
|
#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
|
| 1594 |
|
|
#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 1595 |
|
|
#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 1596 |
|
|
|
| 1597 |
|
|
#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
|
| 1598 |
|
|
|
| 1599 |
|
|
/******************* Bit definition for DMA_CCR3 register *******************/
|
| 1600 |
|
|
#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
|
| 1601 |
|
|
#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
|
| 1602 |
|
|
#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 1603 |
|
|
#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 1604 |
|
|
#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 1605 |
|
|
#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 1606 |
|
|
#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 1607 |
|
|
#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 1608 |
|
|
|
| 1609 |
|
|
#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 1610 |
|
|
#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 1611 |
|
|
#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 1612 |
|
|
|
| 1613 |
|
|
#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 1614 |
|
|
#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 1615 |
|
|
#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 1616 |
|
|
|
| 1617 |
|
|
#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
|
| 1618 |
|
|
#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 1619 |
|
|
#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 1620 |
|
|
|
| 1621 |
|
|
#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
|
| 1622 |
|
|
|
| 1623 |
|
|
/*!<****************** Bit definition for DMA_CCR4 register *******************/
|
| 1624 |
|
|
#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
|
| 1625 |
|
|
#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
|
| 1626 |
|
|
#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 1627 |
|
|
#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 1628 |
|
|
#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 1629 |
|
|
#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 1630 |
|
|
#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 1631 |
|
|
#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 1632 |
|
|
|
| 1633 |
|
|
#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 1634 |
|
|
#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 1635 |
|
|
#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 1636 |
|
|
|
| 1637 |
|
|
#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 1638 |
|
|
#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 1639 |
|
|
#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 1640 |
|
|
|
| 1641 |
|
|
#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
|
| 1642 |
|
|
#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 1643 |
|
|
#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 1644 |
|
|
|
| 1645 |
|
|
#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
|
| 1646 |
|
|
|
| 1647 |
|
|
/****************** Bit definition for DMA_CCR5 register *******************/
|
| 1648 |
|
|
#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
|
| 1649 |
|
|
#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
|
| 1650 |
|
|
#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 1651 |
|
|
#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 1652 |
|
|
#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 1653 |
|
|
#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 1654 |
|
|
#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 1655 |
|
|
#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 1656 |
|
|
|
| 1657 |
|
|
#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 1658 |
|
|
#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 1659 |
|
|
#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 1660 |
|
|
|
| 1661 |
|
|
#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 1662 |
|
|
#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 1663 |
|
|
#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 1664 |
|
|
|
| 1665 |
|
|
#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
|
| 1666 |
|
|
#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 1667 |
|
|
#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 1668 |
|
|
|
| 1669 |
|
|
#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
|
| 1670 |
|
|
|
| 1671 |
|
|
/******************* Bit definition for DMA_CCR6 register *******************/
|
| 1672 |
|
|
#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
|
| 1673 |
|
|
#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
|
| 1674 |
|
|
#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 1675 |
|
|
#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 1676 |
|
|
#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 1677 |
|
|
#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 1678 |
|
|
#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 1679 |
|
|
#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 1680 |
|
|
|
| 1681 |
|
|
#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 1682 |
|
|
#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 1683 |
|
|
#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 1684 |
|
|
|
| 1685 |
|
|
#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 1686 |
|
|
#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 1687 |
|
|
#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 1688 |
|
|
|
| 1689 |
|
|
#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
|
| 1690 |
|
|
#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 1691 |
|
|
#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 1692 |
|
|
|
| 1693 |
|
|
#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
|
| 1694 |
|
|
|
| 1695 |
|
|
/******************* Bit definition for DMA_CCR7 register *******************/
|
| 1696 |
|
|
#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
|
| 1697 |
|
|
#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
|
| 1698 |
|
|
#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
|
| 1699 |
|
|
#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
|
| 1700 |
|
|
#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
|
| 1701 |
|
|
#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
|
| 1702 |
|
|
#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
|
| 1703 |
|
|
#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
|
| 1704 |
|
|
|
| 1705 |
|
|
#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
| 1706 |
|
|
#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
|
| 1707 |
|
|
#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
|
| 1708 |
|
|
|
| 1709 |
|
|
#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
|
| 1710 |
|
|
#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 1711 |
|
|
#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 1712 |
|
|
|
| 1713 |
|
|
#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
|
| 1714 |
|
|
#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 1715 |
|
|
#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 1716 |
|
|
|
| 1717 |
|
|
#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
|
| 1718 |
|
|
|
| 1719 |
|
|
/****************** Bit definition for DMA_CNDTR1 register ******************/
|
| 1720 |
|
|
#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
|
| 1721 |
|
|
|
| 1722 |
|
|
/****************** Bit definition for DMA_CNDTR2 register ******************/
|
| 1723 |
|
|
#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
|
| 1724 |
|
|
|
| 1725 |
|
|
/****************** Bit definition for DMA_CNDTR3 register ******************/
|
| 1726 |
|
|
#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
|
| 1727 |
|
|
|
| 1728 |
|
|
/****************** Bit definition for DMA_CNDTR4 register ******************/
|
| 1729 |
|
|
#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
|
| 1730 |
|
|
|
| 1731 |
|
|
/****************** Bit definition for DMA_CNDTR5 register ******************/
|
| 1732 |
|
|
#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
|
| 1733 |
|
|
|
| 1734 |
|
|
/****************** Bit definition for DMA_CNDTR6 register ******************/
|
| 1735 |
|
|
#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
|
| 1736 |
|
|
|
| 1737 |
|
|
/****************** Bit definition for DMA_CNDTR7 register ******************/
|
| 1738 |
|
|
#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
|
| 1739 |
|
|
|
| 1740 |
|
|
/****************** Bit definition for DMA_CPAR1 register *******************/
|
| 1741 |
|
|
#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
|
| 1742 |
|
|
|
| 1743 |
|
|
/****************** Bit definition for DMA_CPAR2 register *******************/
|
| 1744 |
|
|
#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
|
| 1745 |
|
|
|
| 1746 |
|
|
/****************** Bit definition for DMA_CPAR3 register *******************/
|
| 1747 |
|
|
#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
|
| 1748 |
|
|
|
| 1749 |
|
|
|
| 1750 |
|
|
/****************** Bit definition for DMA_CPAR4 register *******************/
|
| 1751 |
|
|
#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
|
| 1752 |
|
|
|
| 1753 |
|
|
/****************** Bit definition for DMA_CPAR5 register *******************/
|
| 1754 |
|
|
#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
|
| 1755 |
|
|
|
| 1756 |
|
|
/****************** Bit definition for DMA_CPAR6 register *******************/
|
| 1757 |
|
|
#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
|
| 1758 |
|
|
|
| 1759 |
|
|
|
| 1760 |
|
|
/****************** Bit definition for DMA_CPAR7 register *******************/
|
| 1761 |
|
|
#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
|
| 1762 |
|
|
|
| 1763 |
|
|
/****************** Bit definition for DMA_CMAR1 register *******************/
|
| 1764 |
|
|
#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
| 1765 |
|
|
|
| 1766 |
|
|
/****************** Bit definition for DMA_CMAR2 register *******************/
|
| 1767 |
|
|
#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
| 1768 |
|
|
|
| 1769 |
|
|
/****************** Bit definition for DMA_CMAR3 register *******************/
|
| 1770 |
|
|
#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
| 1771 |
|
|
|
| 1772 |
|
|
|
| 1773 |
|
|
/****************** Bit definition for DMA_CMAR4 register *******************/
|
| 1774 |
|
|
#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
| 1775 |
|
|
|
| 1776 |
|
|
/****************** Bit definition for DMA_CMAR5 register *******************/
|
| 1777 |
|
|
#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
| 1778 |
|
|
|
| 1779 |
|
|
/****************** Bit definition for DMA_CMAR6 register *******************/
|
| 1780 |
|
|
#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
| 1781 |
|
|
|
| 1782 |
|
|
/****************** Bit definition for DMA_CMAR7 register *******************/
|
| 1783 |
|
|
#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
| 1784 |
|
|
|
| 1785 |
|
|
/******************************************************************************/
|
| 1786 |
|
|
/* */
|
| 1787 |
|
|
/* External Interrupt/Event Controller */
|
| 1788 |
|
|
/* */
|
| 1789 |
|
|
/******************************************************************************/
|
| 1790 |
|
|
|
| 1791 |
|
|
/******************* Bit definition for EXTI_IMR register *******************/
|
| 1792 |
|
|
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
| 1793 |
|
|
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
| 1794 |
|
|
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
| 1795 |
|
|
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
|
| 1796 |
|
|
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
|
| 1797 |
|
|
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
|
| 1798 |
|
|
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
|
| 1799 |
|
|
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
|
| 1800 |
|
|
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
|
| 1801 |
|
|
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
|
| 1802 |
|
|
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
|
| 1803 |
|
|
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
|
| 1804 |
|
|
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
|
| 1805 |
|
|
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
|
| 1806 |
|
|
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
|
| 1807 |
|
|
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
|
| 1808 |
|
|
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
|
| 1809 |
|
|
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
|
| 1810 |
|
|
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
|
| 1811 |
|
|
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
|
| 1812 |
|
|
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
|
| 1813 |
|
|
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
|
| 1814 |
|
|
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
|
| 1815 |
|
|
|
| 1816 |
|
|
/******************* Bit definition for EXTI_EMR register *******************/
|
| 1817 |
|
|
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
| 1818 |
|
|
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
| 1819 |
|
|
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
| 1820 |
|
|
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
|
| 1821 |
|
|
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
|
| 1822 |
|
|
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
|
| 1823 |
|
|
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
|
| 1824 |
|
|
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
|
| 1825 |
|
|
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
|
| 1826 |
|
|
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
|
| 1827 |
|
|
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
|
| 1828 |
|
|
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
|
| 1829 |
|
|
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
|
| 1830 |
|
|
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
|
| 1831 |
|
|
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
|
| 1832 |
|
|
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
|
| 1833 |
|
|
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
|
| 1834 |
|
|
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
|
| 1835 |
|
|
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
|
| 1836 |
|
|
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
|
| 1837 |
|
|
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
|
| 1838 |
|
|
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
|
| 1839 |
|
|
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
|
| 1840 |
|
|
|
| 1841 |
|
|
/****************** Bit definition for EXTI_RTSR register *******************/
|
| 1842 |
|
|
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
| 1843 |
|
|
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
| 1844 |
|
|
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
| 1845 |
|
|
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
|
| 1846 |
|
|
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
|
| 1847 |
|
|
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
|
| 1848 |
|
|
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
|
| 1849 |
|
|
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
|
| 1850 |
|
|
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
|
| 1851 |
|
|
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
|
| 1852 |
|
|
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
|
| 1853 |
|
|
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
|
| 1854 |
|
|
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
|
| 1855 |
|
|
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
|
| 1856 |
|
|
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
|
| 1857 |
|
|
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
|
| 1858 |
|
|
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
|
| 1859 |
|
|
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
|
| 1860 |
|
|
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
|
| 1861 |
|
|
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
|
| 1862 |
|
|
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
|
| 1863 |
|
|
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
|
| 1864 |
|
|
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
|
| 1865 |
|
|
|
| 1866 |
|
|
/****************** Bit definition for EXTI_FTSR register *******************/
|
| 1867 |
|
|
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
| 1868 |
|
|
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
| 1869 |
|
|
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
| 1870 |
|
|
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
|
| 1871 |
|
|
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
|
| 1872 |
|
|
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
|
| 1873 |
|
|
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
|
| 1874 |
|
|
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
|
| 1875 |
|
|
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
|
| 1876 |
|
|
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
|
| 1877 |
|
|
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
|
| 1878 |
|
|
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
|
| 1879 |
|
|
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
|
| 1880 |
|
|
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
|
| 1881 |
|
|
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
|
| 1882 |
|
|
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
|
| 1883 |
|
|
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
|
| 1884 |
|
|
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
|
| 1885 |
|
|
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
|
| 1886 |
|
|
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
|
| 1887 |
|
|
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
|
| 1888 |
|
|
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
|
| 1889 |
|
|
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
|
| 1890 |
|
|
|
| 1891 |
|
|
/****************** Bit definition for EXTI_SWIER register ******************/
|
| 1892 |
|
|
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
| 1893 |
|
|
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
| 1894 |
|
|
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
| 1895 |
|
|
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
|
| 1896 |
|
|
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
|
| 1897 |
|
|
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
|
| 1898 |
|
|
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
|
| 1899 |
|
|
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
|
| 1900 |
|
|
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
|
| 1901 |
|
|
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
|
| 1902 |
|
|
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
|
| 1903 |
|
|
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
|
| 1904 |
|
|
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
|
| 1905 |
|
|
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
|
| 1906 |
|
|
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
|
| 1907 |
|
|
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
|
| 1908 |
|
|
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
|
| 1909 |
|
|
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
|
| 1910 |
|
|
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
|
| 1911 |
|
|
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
|
| 1912 |
|
|
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
|
| 1913 |
|
|
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
|
| 1914 |
|
|
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
|
| 1915 |
|
|
|
| 1916 |
|
|
/******************* Bit definition for EXTI_PR register ********************/
|
| 1917 |
|
|
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
|
| 1918 |
|
|
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
|
| 1919 |
|
|
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
|
| 1920 |
|
|
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
|
| 1921 |
|
|
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
|
| 1922 |
|
|
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
|
| 1923 |
|
|
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
|
| 1924 |
|
|
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
|
| 1925 |
|
|
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
|
| 1926 |
|
|
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
|
| 1927 |
|
|
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
|
| 1928 |
|
|
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
|
| 1929 |
|
|
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
|
| 1930 |
|
|
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
|
| 1931 |
|
|
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
|
| 1932 |
|
|
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
|
| 1933 |
|
|
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
|
| 1934 |
|
|
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
|
| 1935 |
|
|
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
|
| 1936 |
|
|
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
|
| 1937 |
|
|
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
|
| 1938 |
|
|
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
|
| 1939 |
|
|
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
|
| 1940 |
|
|
|
| 1941 |
|
|
/******************************************************************************/
|
| 1942 |
|
|
/* */
|
| 1943 |
|
|
/* FLASH and Option Bytes Registers */
|
| 1944 |
|
|
/* */
|
| 1945 |
|
|
/******************************************************************************/
|
| 1946 |
|
|
|
| 1947 |
|
|
/******************* Bit definition for FLASH_ACR register ******************/
|
| 1948 |
|
|
#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
|
| 1949 |
|
|
#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
|
| 1950 |
|
|
#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
|
| 1951 |
|
|
#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
|
| 1952 |
|
|
#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
|
| 1953 |
|
|
|
| 1954 |
|
|
/******************* Bit definition for FLASH_PECR register ******************/
|
| 1955 |
|
|
#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
|
| 1956 |
|
|
#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
|
| 1957 |
|
|
#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
|
| 1958 |
|
|
#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
|
| 1959 |
|
|
#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
|
| 1960 |
|
|
#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
|
| 1961 |
|
|
#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
|
| 1962 |
|
|
#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
|
| 1963 |
|
|
#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
|
| 1964 |
|
|
#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
|
| 1965 |
|
|
#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
|
| 1966 |
|
|
|
| 1967 |
|
|
/****************** Bit definition for FLASH_PDKEYR register ******************/
|
| 1968 |
|
|
#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
|
| 1969 |
|
|
|
| 1970 |
|
|
/****************** Bit definition for FLASH_PEKEYR register ******************/
|
| 1971 |
|
|
#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
|
| 1972 |
|
|
|
| 1973 |
|
|
/****************** Bit definition for FLASH_PRGKEYR register ******************/
|
| 1974 |
|
|
#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
|
| 1975 |
|
|
|
| 1976 |
|
|
/****************** Bit definition for FLASH_OPTKEYR register ******************/
|
| 1977 |
|
|
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
|
| 1978 |
|
|
|
| 1979 |
|
|
/****************** Bit definition for FLASH_SR register *******************/
|
| 1980 |
|
|
#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
|
| 1981 |
|
|
#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
|
| 1982 |
|
|
#define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */
|
| 1983 |
|
|
#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
|
| 1984 |
|
|
|
| 1985 |
|
|
#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
|
| 1986 |
|
|
#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
|
| 1987 |
|
|
#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
|
| 1988 |
|
|
#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
|
| 1989 |
|
|
|
| 1990 |
|
|
/****************** Bit definition for FLASH_OBR register *******************/
|
| 1991 |
|
|
#define FLASH_OBR_RDPRT ((uint16_t)0x000000AA) /*!< Read Protection */
|
| 1992 |
|
|
#define FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
|
| 1993 |
|
|
#define FLASH_OBR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
|
| 1994 |
|
|
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
|
| 1995 |
|
|
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
|
| 1996 |
|
|
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
|
| 1997 |
|
|
|
| 1998 |
|
|
/****************** Bit definition for FLASH_WRPR register ******************/
|
| 1999 |
|
|
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
|
| 2000 |
|
|
|
| 2001 |
|
|
/******************************************************************************/
|
| 2002 |
|
|
/* */
|
| 2003 |
|
|
/* General Purpose IOs */
|
| 2004 |
|
|
/* */
|
| 2005 |
|
|
/******************************************************************************/
|
| 2006 |
|
|
/******************* Bit definition for GPIO_MODER register *****************/
|
| 2007 |
|
|
#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
|
| 2008 |
|
|
#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
|
| 2009 |
|
|
#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
|
| 2010 |
|
|
#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
|
| 2011 |
|
|
#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
|
| 2012 |
|
|
#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
|
| 2013 |
|
|
#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
|
| 2014 |
|
|
#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
|
| 2015 |
|
|
#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
|
| 2016 |
|
|
#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
|
| 2017 |
|
|
#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
|
| 2018 |
|
|
#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
|
| 2019 |
|
|
#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
|
| 2020 |
|
|
#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
|
| 2021 |
|
|
#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
|
| 2022 |
|
|
#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
|
| 2023 |
|
|
#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
|
| 2024 |
|
|
#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
|
| 2025 |
|
|
#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
|
| 2026 |
|
|
#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
|
| 2027 |
|
|
#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
|
| 2028 |
|
|
#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
|
| 2029 |
|
|
#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
|
| 2030 |
|
|
#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
|
| 2031 |
|
|
#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
|
| 2032 |
|
|
#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
|
| 2033 |
|
|
#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
|
| 2034 |
|
|
#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
|
| 2035 |
|
|
#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
|
| 2036 |
|
|
#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
|
| 2037 |
|
|
#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
|
| 2038 |
|
|
#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
|
| 2039 |
|
|
#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
|
| 2040 |
|
|
#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
|
| 2041 |
|
|
#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
|
| 2042 |
|
|
#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
|
| 2043 |
|
|
#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
|
| 2044 |
|
|
#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
|
| 2045 |
|
|
#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
|
| 2046 |
|
|
#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
|
| 2047 |
|
|
#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
|
| 2048 |
|
|
#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
|
| 2049 |
|
|
#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
|
| 2050 |
|
|
#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
|
| 2051 |
|
|
#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
|
| 2052 |
|
|
#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
|
| 2053 |
|
|
#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
|
| 2054 |
|
|
#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
|
| 2055 |
|
|
|
| 2056 |
|
|
/******************* Bit definition for GPIO_OTYPER register ****************/
|
| 2057 |
|
|
#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
|
| 2058 |
|
|
#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
|
| 2059 |
|
|
#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
|
| 2060 |
|
|
#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
|
| 2061 |
|
|
#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
|
| 2062 |
|
|
#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
|
| 2063 |
|
|
#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
|
| 2064 |
|
|
#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
|
| 2065 |
|
|
#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
|
| 2066 |
|
|
#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
|
| 2067 |
|
|
#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
|
| 2068 |
|
|
#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
|
| 2069 |
|
|
#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
|
| 2070 |
|
|
#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
|
| 2071 |
|
|
#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
|
| 2072 |
|
|
#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
|
| 2073 |
|
|
|
| 2074 |
|
|
/******************* Bit definition for GPIO_OSPEEDR register ***************/
|
| 2075 |
|
|
#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
|
| 2076 |
|
|
#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
|
| 2077 |
|
|
#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
|
| 2078 |
|
|
#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
|
| 2079 |
|
|
#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
|
| 2080 |
|
|
#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
|
| 2081 |
|
|
#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
|
| 2082 |
|
|
#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
|
| 2083 |
|
|
#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
|
| 2084 |
|
|
#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
|
| 2085 |
|
|
#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
|
| 2086 |
|
|
#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
|
| 2087 |
|
|
#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
|
| 2088 |
|
|
#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
|
| 2089 |
|
|
#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
|
| 2090 |
|
|
#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
|
| 2091 |
|
|
#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
|
| 2092 |
|
|
#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
|
| 2093 |
|
|
#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
|
| 2094 |
|
|
#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
|
| 2095 |
|
|
#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
|
| 2096 |
|
|
#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
|
| 2097 |
|
|
#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
|
| 2098 |
|
|
#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
|
| 2099 |
|
|
#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
|
| 2100 |
|
|
#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
|
| 2101 |
|
|
#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
|
| 2102 |
|
|
#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
|
| 2103 |
|
|
#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
|
| 2104 |
|
|
#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
|
| 2105 |
|
|
#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
|
| 2106 |
|
|
#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
|
| 2107 |
|
|
#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
|
| 2108 |
|
|
#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
|
| 2109 |
|
|
#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
|
| 2110 |
|
|
#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
|
| 2111 |
|
|
#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
|
| 2112 |
|
|
#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
|
| 2113 |
|
|
#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
|
| 2114 |
|
|
#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
|
| 2115 |
|
|
#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
|
| 2116 |
|
|
#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
|
| 2117 |
|
|
#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
|
| 2118 |
|
|
#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
|
| 2119 |
|
|
#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
|
| 2120 |
|
|
#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
|
| 2121 |
|
|
#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
|
| 2122 |
|
|
#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
|
| 2123 |
|
|
|
| 2124 |
|
|
/******************* Bit definition for GPIO_PUPDR register *****************/
|
| 2125 |
|
|
#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
|
| 2126 |
|
|
#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
|
| 2127 |
|
|
#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
|
| 2128 |
|
|
#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
|
| 2129 |
|
|
#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
|
| 2130 |
|
|
#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
|
| 2131 |
|
|
#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
|
| 2132 |
|
|
#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
|
| 2133 |
|
|
#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
|
| 2134 |
|
|
#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
|
| 2135 |
|
|
#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
|
| 2136 |
|
|
#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
|
| 2137 |
|
|
#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
|
| 2138 |
|
|
#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
|
| 2139 |
|
|
#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
|
| 2140 |
|
|
#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
|
| 2141 |
|
|
#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
|
| 2142 |
|
|
#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
|
| 2143 |
|
|
#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
|
| 2144 |
|
|
#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
|
| 2145 |
|
|
#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
|
| 2146 |
|
|
#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
|
| 2147 |
|
|
#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
|
| 2148 |
|
|
#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
|
| 2149 |
|
|
#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
|
| 2150 |
|
|
#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
|
| 2151 |
|
|
#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
|
| 2152 |
|
|
#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
|
| 2153 |
|
|
#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
|
| 2154 |
|
|
#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
|
| 2155 |
|
|
#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
|
| 2156 |
|
|
#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
|
| 2157 |
|
|
#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
|
| 2158 |
|
|
#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
|
| 2159 |
|
|
#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
|
| 2160 |
|
|
#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
|
| 2161 |
|
|
#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
|
| 2162 |
|
|
#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
|
| 2163 |
|
|
#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
|
| 2164 |
|
|
#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
|
| 2165 |
|
|
#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
|
| 2166 |
|
|
#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
|
| 2167 |
|
|
#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
|
| 2168 |
|
|
#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
|
| 2169 |
|
|
#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
|
| 2170 |
|
|
#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
|
| 2171 |
|
|
#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
|
| 2172 |
|
|
#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
|
| 2173 |
|
|
|
| 2174 |
|
|
/******************* Bit definition for GPIO_IDR register *******************/
|
| 2175 |
|
|
#define GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001)
|
| 2176 |
|
|
#define GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002)
|
| 2177 |
|
|
#define GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004)
|
| 2178 |
|
|
#define GPIO_OTYPER_IDR_3 ((uint32_t)0x00000008)
|
| 2179 |
|
|
#define GPIO_OTYPER_IDR_4 ((uint32_t)0x00000010)
|
| 2180 |
|
|
#define GPIO_OTYPER_IDR_5 ((uint32_t)0x00000020)
|
| 2181 |
|
|
#define GPIO_OTYPER_IDR_6 ((uint32_t)0x00000040)
|
| 2182 |
|
|
#define GPIO_OTYPER_IDR_7 ((uint32_t)0x00000080)
|
| 2183 |
|
|
#define GPIO_OTYPER_IDR_8 ((uint32_t)0x00000100)
|
| 2184 |
|
|
#define GPIO_OTYPER_IDR_9 ((uint32_t)0x00000200)
|
| 2185 |
|
|
#define GPIO_OTYPER_IDR_10 ((uint32_t)0x00000400)
|
| 2186 |
|
|
#define GPIO_OTYPER_IDR_11 ((uint32_t)0x00000800)
|
| 2187 |
|
|
#define GPIO_OTYPER_IDR_12 ((uint32_t)0x00001000)
|
| 2188 |
|
|
#define GPIO_OTYPER_IDR_13 ((uint32_t)0x00002000)
|
| 2189 |
|
|
#define GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000)
|
| 2190 |
|
|
#define GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000)
|
| 2191 |
|
|
|
| 2192 |
|
|
/******************* Bit definition for GPIO_ODR register *******************/
|
| 2193 |
|
|
#define GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001)
|
| 2194 |
|
|
#define GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002)
|
| 2195 |
|
|
#define GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004)
|
| 2196 |
|
|
#define GPIO_OTYPER_ODR_3 ((uint32_t)0x00000008)
|
| 2197 |
|
|
#define GPIO_OTYPER_ODR_4 ((uint32_t)0x00000010)
|
| 2198 |
|
|
#define GPIO_OTYPER_ODR_5 ((uint32_t)0x00000020)
|
| 2199 |
|
|
#define GPIO_OTYPER_ODR_6 ((uint32_t)0x00000040)
|
| 2200 |
|
|
#define GPIO_OTYPER_ODR_7 ((uint32_t)0x00000080)
|
| 2201 |
|
|
#define GPIO_OTYPER_ODR_8 ((uint32_t)0x00000100)
|
| 2202 |
|
|
#define GPIO_OTYPER_ODR_9 ((uint32_t)0x00000200)
|
| 2203 |
|
|
#define GPIO_OTYPER_ODR_10 ((uint32_t)0x00000400)
|
| 2204 |
|
|
#define GPIO_OTYPER_ODR_11 ((uint32_t)0x00000800)
|
| 2205 |
|
|
#define GPIO_OTYPER_ODR_12 ((uint32_t)0x00001000)
|
| 2206 |
|
|
#define GPIO_OTYPER_ODR_13 ((uint32_t)0x00002000)
|
| 2207 |
|
|
#define GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000)
|
| 2208 |
|
|
#define GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000)
|
| 2209 |
|
|
|
| 2210 |
|
|
/******************* Bit definition for GPIO_BSRR register ******************/
|
| 2211 |
|
|
#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
|
| 2212 |
|
|
#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
|
| 2213 |
|
|
#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
|
| 2214 |
|
|
#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
|
| 2215 |
|
|
#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
|
| 2216 |
|
|
#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
|
| 2217 |
|
|
#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
|
| 2218 |
|
|
#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
|
| 2219 |
|
|
#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
|
| 2220 |
|
|
#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
|
| 2221 |
|
|
#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
|
| 2222 |
|
|
#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
|
| 2223 |
|
|
#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
|
| 2224 |
|
|
#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
|
| 2225 |
|
|
#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
|
| 2226 |
|
|
#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
|
| 2227 |
|
|
#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
|
| 2228 |
|
|
#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
|
| 2229 |
|
|
#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
|
| 2230 |
|
|
#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
|
| 2231 |
|
|
#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
|
| 2232 |
|
|
#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
|
| 2233 |
|
|
#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
|
| 2234 |
|
|
#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
|
| 2235 |
|
|
#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
|
| 2236 |
|
|
#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
|
| 2237 |
|
|
#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
|
| 2238 |
|
|
#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
|
| 2239 |
|
|
#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
|
| 2240 |
|
|
#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
|
| 2241 |
|
|
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
|
| 2242 |
|
|
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
|
| 2243 |
|
|
|
| 2244 |
|
|
/******************************************************************************/
|
| 2245 |
|
|
/* */
|
| 2246 |
|
|
/* Inter-integrated Circuit Interface */
|
| 2247 |
|
|
/* */
|
| 2248 |
|
|
/******************************************************************************/
|
| 2249 |
|
|
|
| 2250 |
|
|
/******************* Bit definition for I2C_CR1 register ********************/
|
| 2251 |
|
|
#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
|
| 2252 |
|
|
#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
|
| 2253 |
|
|
#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
|
| 2254 |
|
|
#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
|
| 2255 |
|
|
#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
|
| 2256 |
|
|
#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
|
| 2257 |
|
|
#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
|
| 2258 |
|
|
#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
|
| 2259 |
|
|
#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
|
| 2260 |
|
|
#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
|
| 2261 |
|
|
#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
|
| 2262 |
|
|
#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
|
| 2263 |
|
|
#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
|
| 2264 |
|
|
#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
|
| 2265 |
|
|
|
| 2266 |
|
|
/******************* Bit definition for I2C_CR2 register ********************/
|
| 2267 |
|
|
#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
|
| 2268 |
|
|
#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
|
| 2269 |
|
|
#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
|
| 2270 |
|
|
#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
|
| 2271 |
|
|
#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
|
| 2272 |
|
|
#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
|
| 2273 |
|
|
#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
|
| 2274 |
|
|
|
| 2275 |
|
|
#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
|
| 2276 |
|
|
#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
|
| 2277 |
|
|
#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
|
| 2278 |
|
|
#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
|
| 2279 |
|
|
#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
|
| 2280 |
|
|
|
| 2281 |
|
|
/******************* Bit definition for I2C_OAR1 register *******************/
|
| 2282 |
|
|
#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
|
| 2283 |
|
|
#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
|
| 2284 |
|
|
|
| 2285 |
|
|
#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
|
| 2286 |
|
|
#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
|
| 2287 |
|
|
#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
|
| 2288 |
|
|
#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
|
| 2289 |
|
|
#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
|
| 2290 |
|
|
#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
|
| 2291 |
|
|
#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
|
| 2292 |
|
|
#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
|
| 2293 |
|
|
#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
|
| 2294 |
|
|
#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
|
| 2295 |
|
|
|
| 2296 |
|
|
#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
|
| 2297 |
|
|
|
| 2298 |
|
|
/******************* Bit definition for I2C_OAR2 register *******************/
|
| 2299 |
|
|
#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
|
| 2300 |
|
|
#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
|
| 2301 |
|
|
|
| 2302 |
|
|
/******************** Bit definition for I2C_DR register ********************/
|
| 2303 |
|
|
#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
|
| 2304 |
|
|
|
| 2305 |
|
|
/******************* Bit definition for I2C_SR1 register ********************/
|
| 2306 |
|
|
#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
|
| 2307 |
|
|
#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
|
| 2308 |
|
|
#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
|
| 2309 |
|
|
#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
|
| 2310 |
|
|
#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
|
| 2311 |
|
|
#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
|
| 2312 |
|
|
#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
|
| 2313 |
|
|
#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
|
| 2314 |
|
|
#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
|
| 2315 |
|
|
#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
|
| 2316 |
|
|
#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
|
| 2317 |
|
|
#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
|
| 2318 |
|
|
#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
|
| 2319 |
|
|
#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
|
| 2320 |
|
|
|
| 2321 |
|
|
/******************* Bit definition for I2C_SR2 register ********************/
|
| 2322 |
|
|
#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
|
| 2323 |
|
|
#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
|
| 2324 |
|
|
#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
|
| 2325 |
|
|
#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
|
| 2326 |
|
|
#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
|
| 2327 |
|
|
#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
|
| 2328 |
|
|
#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
|
| 2329 |
|
|
#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
|
| 2330 |
|
|
|
| 2331 |
|
|
/******************* Bit definition for I2C_CCR register ********************/
|
| 2332 |
|
|
#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
|
| 2333 |
|
|
#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
|
| 2334 |
|
|
#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
|
| 2335 |
|
|
|
| 2336 |
|
|
/****************** Bit definition for I2C_TRISE register *******************/
|
| 2337 |
|
|
#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
|
| 2338 |
|
|
|
| 2339 |
|
|
/******************************************************************************/
|
| 2340 |
|
|
/* */
|
| 2341 |
|
|
/* Independent WATCHDOG */
|
| 2342 |
|
|
/* */
|
| 2343 |
|
|
/******************************************************************************/
|
| 2344 |
|
|
|
| 2345 |
|
|
/******************* Bit definition for IWDG_KR register ********************/
|
| 2346 |
|
|
#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
|
| 2347 |
|
|
|
| 2348 |
|
|
/******************* Bit definition for IWDG_PR register ********************/
|
| 2349 |
|
|
#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
|
| 2350 |
|
|
#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
|
| 2351 |
|
|
#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
|
| 2352 |
|
|
#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
|
| 2353 |
|
|
|
| 2354 |
|
|
/******************* Bit definition for IWDG_RLR register *******************/
|
| 2355 |
|
|
#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
|
| 2356 |
|
|
|
| 2357 |
|
|
/******************* Bit definition for IWDG_SR register ********************/
|
| 2358 |
|
|
#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
|
| 2359 |
|
|
#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
|
| 2360 |
|
|
|
| 2361 |
|
|
/******************************************************************************/
|
| 2362 |
|
|
/* */
|
| 2363 |
|
|
/* LCD */
|
| 2364 |
|
|
/* */
|
| 2365 |
|
|
/******************************************************************************/
|
| 2366 |
|
|
|
| 2367 |
|
|
/******************* Bit definition for LCD_CR register *********************/
|
| 2368 |
|
|
#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
|
| 2369 |
|
|
#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
|
| 2370 |
|
|
|
| 2371 |
|
|
#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
|
| 2372 |
|
|
#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
|
| 2373 |
|
|
#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
|
| 2374 |
|
|
#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
|
| 2375 |
|
|
|
| 2376 |
|
|
#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
|
| 2377 |
|
|
#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
|
| 2378 |
|
|
#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
|
| 2379 |
|
|
|
| 2380 |
|
|
#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
|
| 2381 |
|
|
|
| 2382 |
|
|
/******************* Bit definition for LCD_FCR register ********************/
|
| 2383 |
|
|
#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
|
| 2384 |
|
|
#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
|
| 2385 |
|
|
#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
|
| 2386 |
|
|
|
| 2387 |
|
|
#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
|
| 2388 |
|
|
#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
| 2389 |
|
|
#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
| 2390 |
|
|
#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
| 2391 |
|
|
|
| 2392 |
|
|
#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
|
| 2393 |
|
|
#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
|
| 2394 |
|
|
#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
|
| 2395 |
|
|
#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
|
| 2396 |
|
|
|
| 2397 |
|
|
#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
|
| 2398 |
|
|
#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 2399 |
|
|
#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 2400 |
|
|
#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 2401 |
|
|
|
| 2402 |
|
|
#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
|
| 2403 |
|
|
#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
|
| 2404 |
|
|
#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
|
| 2405 |
|
|
#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
|
| 2406 |
|
|
|
| 2407 |
|
|
#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
|
| 2408 |
|
|
#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
| 2409 |
|
|
#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
| 2410 |
|
|
|
| 2411 |
|
|
#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
|
| 2412 |
|
|
#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
|
| 2413 |
|
|
|
| 2414 |
|
|
/******************* Bit definition for LCD_SR register *********************/
|
| 2415 |
|
|
#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
|
| 2416 |
|
|
#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
|
| 2417 |
|
|
#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
|
| 2418 |
|
|
#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
|
| 2419 |
|
|
#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
|
| 2420 |
|
|
#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
|
| 2421 |
|
|
|
| 2422 |
|
|
/******************* Bit definition for LCD_CLR register ********************/
|
| 2423 |
|
|
#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
|
| 2424 |
|
|
#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
|
| 2425 |
|
|
|
| 2426 |
|
|
/******************* Bit definition for LCD_RAM register ********************/
|
| 2427 |
|
|
#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
|
| 2428 |
|
|
|
| 2429 |
|
|
/******************************************************************************/
|
| 2430 |
|
|
/* */
|
| 2431 |
|
|
/* Power Control */
|
| 2432 |
|
|
/* */
|
| 2433 |
|
|
/******************************************************************************/
|
| 2434 |
|
|
|
| 2435 |
|
|
/******************** Bit definition for PWR_CR register ********************/
|
| 2436 |
|
|
#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */
|
| 2437 |
|
|
#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
|
| 2438 |
|
|
#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
|
| 2439 |
|
|
#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
|
| 2440 |
|
|
#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
|
| 2441 |
|
|
|
| 2442 |
|
|
#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
|
| 2443 |
|
|
#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
|
| 2444 |
|
|
#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
|
| 2445 |
|
|
#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
|
| 2446 |
|
|
|
| 2447 |
|
|
/*!< PVD level configuration */
|
| 2448 |
|
|
#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
|
| 2449 |
|
|
#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
|
| 2450 |
|
|
#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
|
| 2451 |
|
|
#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
|
| 2452 |
|
|
#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
|
| 2453 |
|
|
#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
|
| 2454 |
|
|
#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
|
| 2455 |
|
|
#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
|
| 2456 |
|
|
|
| 2457 |
|
|
#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
|
| 2458 |
|
|
#define PWR_CR_ULP ((uint16_t)0x0200) /*!< Ultra Low Power mode */
|
| 2459 |
|
|
#define PWR_CR_FWU ((uint16_t)0x0400) /*!< Fast wakeup */
|
| 2460 |
|
|
|
| 2461 |
|
|
#define PWR_CR_VOS ((uint16_t)0x1800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
|
| 2462 |
|
|
#define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */
|
| 2463 |
|
|
#define PWR_CR_VOS_1 ((uint16_t)0x1000) /*!< Bit 1 */
|
| 2464 |
|
|
#define PWR_CR_LPRUN ((uint16_t)0x4000) /*!< Low power run mode */
|
| 2465 |
|
|
|
| 2466 |
|
|
/******************* Bit definition for PWR_CSR register ********************/
|
| 2467 |
|
|
#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
|
| 2468 |
|
|
#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
|
| 2469 |
|
|
#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
|
| 2470 |
|
|
#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */
|
| 2471 |
|
|
#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */
|
| 2472 |
|
|
#define PWR_CSR_REGLPF ((uint16_t)0x0020) /*!< Regulator LP flag */
|
| 2473 |
|
|
|
| 2474 |
|
|
#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
|
| 2475 |
|
|
#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
|
| 2476 |
|
|
#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
|
| 2477 |
|
|
|
| 2478 |
|
|
/******************************************************************************/
|
| 2479 |
|
|
/* */
|
| 2480 |
|
|
/* Reset and Clock Control */
|
| 2481 |
|
|
/* */
|
| 2482 |
|
|
/******************************************************************************/
|
| 2483 |
|
|
/******************** Bit definition for RCC_CR register ********************/
|
| 2484 |
|
|
#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
|
| 2485 |
|
|
#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
|
| 2486 |
|
|
|
| 2487 |
|
|
#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
|
| 2488 |
|
|
#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
|
| 2489 |
|
|
|
| 2490 |
|
|
#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
|
| 2491 |
|
|
#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
|
| 2492 |
|
|
#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
|
| 2493 |
|
|
|
| 2494 |
|
|
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
|
| 2495 |
|
|
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
|
| 2496 |
|
|
#define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */
|
| 2497 |
|
|
|
| 2498 |
|
|
#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */
|
| 2499 |
|
|
#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */
|
| 2500 |
|
|
#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */
|
| 2501 |
|
|
|
| 2502 |
|
|
/******************** Bit definition for RCC_ICSCR register *****************/
|
| 2503 |
|
|
#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
|
| 2504 |
|
|
#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
|
| 2505 |
|
|
|
| 2506 |
|
|
#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
|
| 2507 |
|
|
#define RCC_ICSCR_MSIRANGE_64KHz ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 64KHz */
|
| 2508 |
|
|
#define RCC_ICSCR_MSIRANGE_128KHz ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 128KHz */
|
| 2509 |
|
|
#define RCC_ICSCR_MSIRANGE_256KHz ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 256KHz */
|
| 2510 |
|
|
#define RCC_ICSCR_MSIRANGE_512KHz ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 512KHz */
|
| 2511 |
|
|
#define RCC_ICSCR_MSIRANGE_1MHz ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1MHz */
|
| 2512 |
|
|
#define RCC_ICSCR_MSIRANGE_2MHz ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2MHz */
|
| 2513 |
|
|
#define RCC_ICSCR_MSIRANGE_4MHz ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4MHz */
|
| 2514 |
|
|
#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
|
| 2515 |
|
|
#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
|
| 2516 |
|
|
|
| 2517 |
|
|
/******************** Bit definition for RCC_CFGR register ******************/
|
| 2518 |
|
|
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
|
| 2519 |
|
|
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 2520 |
|
|
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 2521 |
|
|
|
| 2522 |
|
|
/*!< SW configuration */
|
| 2523 |
|
|
#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
|
| 2524 |
|
|
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
|
| 2525 |
|
|
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
|
| 2526 |
|
|
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
|
| 2527 |
|
|
|
| 2528 |
|
|
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
|
| 2529 |
|
|
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
|
| 2530 |
|
|
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
|
| 2531 |
|
|
|
| 2532 |
|
|
/*!< SWS configuration */
|
| 2533 |
|
|
#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
|
| 2534 |
|
|
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
|
| 2535 |
|
|
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
|
| 2536 |
|
|
#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
|
| 2537 |
|
|
|
| 2538 |
|
|
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
|
| 2539 |
|
|
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
| 2540 |
|
|
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
| 2541 |
|
|
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
| 2542 |
|
|
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
|
| 2543 |
|
|
|
| 2544 |
|
|
/*!< HPRE configuration */
|
| 2545 |
|
|
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
|
| 2546 |
|
|
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
|
| 2547 |
|
|
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
|
| 2548 |
|
|
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
|
| 2549 |
|
|
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
|
| 2550 |
|
|
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
|
| 2551 |
|
|
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
|
| 2552 |
|
|
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
|
| 2553 |
|
|
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
|
| 2554 |
|
|
|
| 2555 |
|
|
#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
|
| 2556 |
|
|
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
| 2557 |
|
|
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
| 2558 |
|
|
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
|
| 2559 |
|
|
|
| 2560 |
|
|
/*!< PPRE1 configuration */
|
| 2561 |
|
|
#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
| 2562 |
|
|
#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
|
| 2563 |
|
|
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
|
| 2564 |
|
|
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
|
| 2565 |
|
|
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
|
| 2566 |
|
|
|
| 2567 |
|
|
#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
|
| 2568 |
|
|
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
|
| 2569 |
|
|
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
|
| 2570 |
|
|
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
|
| 2571 |
|
|
|
| 2572 |
|
|
/*!< PPRE2 configuration */
|
| 2573 |
|
|
#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
| 2574 |
|
|
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
|
| 2575 |
|
|
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
|
| 2576 |
|
|
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
|
| 2577 |
|
|
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
|
| 2578 |
|
|
|
| 2579 |
|
|
/*!< PLL entry clock source*/
|
| 2580 |
|
|
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
|
| 2581 |
|
|
|
| 2582 |
|
|
#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
|
| 2583 |
|
|
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
|
| 2584 |
|
|
|
| 2585 |
|
|
|
| 2586 |
|
|
#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
|
| 2587 |
|
|
#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
| 2588 |
|
|
#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
| 2589 |
|
|
#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
|
| 2590 |
|
|
#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
|
| 2591 |
|
|
|
| 2592 |
|
|
/*!< PLLMUL configuration */
|
| 2593 |
|
|
#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
|
| 2594 |
|
|
#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
|
| 2595 |
|
|
#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
|
| 2596 |
|
|
#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
|
| 2597 |
|
|
#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
|
| 2598 |
|
|
#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
|
| 2599 |
|
|
#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
|
| 2600 |
|
|
#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
|
| 2601 |
|
|
#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
|
| 2602 |
|
|
|
| 2603 |
|
|
/*!< PLLDIV configuration */
|
| 2604 |
|
|
#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
|
| 2605 |
|
|
#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
|
| 2606 |
|
|
#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
|
| 2607 |
|
|
|
| 2608 |
|
|
|
| 2609 |
|
|
/*!< PLLDIV configuration */
|
| 2610 |
|
|
#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */
|
| 2611 |
|
|
#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
|
| 2612 |
|
|
#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
|
| 2613 |
|
|
#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
|
| 2614 |
|
|
|
| 2615 |
|
|
|
| 2616 |
|
|
#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
|
| 2617 |
|
|
#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
| 2618 |
|
|
#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
| 2619 |
|
|
#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
| 2620 |
|
|
|
| 2621 |
|
|
/*!< MCO configuration */
|
| 2622 |
|
|
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
|
| 2623 |
|
|
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */
|
| 2624 |
|
|
#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
|
| 2625 |
|
|
#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
|
| 2626 |
|
|
#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
|
| 2627 |
|
|
#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
|
| 2628 |
|
|
#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
|
| 2629 |
|
|
#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
|
| 2630 |
|
|
|
| 2631 |
|
|
#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
|
| 2632 |
|
|
#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
|
| 2633 |
|
|
#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
|
| 2634 |
|
|
#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
|
| 2635 |
|
|
|
| 2636 |
|
|
/*!< MCO Prescaler configuration */
|
| 2637 |
|
|
#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */
|
| 2638 |
|
|
#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */
|
| 2639 |
|
|
#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */
|
| 2640 |
|
|
#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */
|
| 2641 |
|
|
#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */
|
| 2642 |
|
|
|
| 2643 |
|
|
/*!<****************** Bit definition for RCC_CIR register ********************/
|
| 2644 |
|
|
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
| 2645 |
|
|
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
|
| 2646 |
|
|
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
|
| 2647 |
|
|
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
|
| 2648 |
|
|
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
|
| 2649 |
|
|
#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
|
| 2650 |
|
|
#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
|
| 2651 |
|
|
|
| 2652 |
|
|
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
|
| 2653 |
|
|
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
|
| 2654 |
|
|
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
|
| 2655 |
|
|
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
|
| 2656 |
|
|
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
|
| 2657 |
|
|
#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */
|
| 2658 |
|
|
|
| 2659 |
|
|
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
|
| 2660 |
|
|
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
|
| 2661 |
|
|
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
|
| 2662 |
|
|
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
|
| 2663 |
|
|
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
|
| 2664 |
|
|
#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */
|
| 2665 |
|
|
#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
|
| 2666 |
|
|
|
| 2667 |
|
|
|
| 2668 |
|
|
/***************** Bit definition for RCC_AHBRSTR register ******************/
|
| 2669 |
|
|
#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
|
| 2670 |
|
|
#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
|
| 2671 |
|
|
#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
|
| 2672 |
|
|
#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
|
| 2673 |
|
|
#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
|
| 2674 |
|
|
#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */
|
| 2675 |
|
|
#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
|
| 2676 |
|
|
#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
|
| 2677 |
|
|
#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
|
| 2678 |
|
|
|
| 2679 |
|
|
/***************** Bit definition for RCC_APB2RSTR register *****************/
|
| 2680 |
|
|
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
|
| 2681 |
|
|
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
|
| 2682 |
|
|
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */
|
| 2683 |
|
|
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */
|
| 2684 |
|
|
#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */
|
| 2685 |
|
|
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
|
| 2686 |
|
|
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
|
| 2687 |
|
|
|
| 2688 |
|
|
/***************** Bit definition for RCC_APB1RSTR register *****************/
|
| 2689 |
|
|
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
|
| 2690 |
|
|
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
|
| 2691 |
|
|
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
|
| 2692 |
|
|
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
|
| 2693 |
|
|
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
|
| 2694 |
|
|
#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */
|
| 2695 |
|
|
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
|
| 2696 |
|
|
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
|
| 2697 |
|
|
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
|
| 2698 |
|
|
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
|
| 2699 |
|
|
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
|
| 2700 |
|
|
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
|
| 2701 |
|
|
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
|
| 2702 |
|
|
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
|
| 2703 |
|
|
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
|
| 2704 |
|
|
#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */
|
| 2705 |
|
|
|
| 2706 |
|
|
/****************** Bit definition for RCC_AHBENR register ******************/
|
| 2707 |
|
|
#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
|
| 2708 |
|
|
#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
|
| 2709 |
|
|
#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
|
| 2710 |
|
|
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
|
| 2711 |
|
|
#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
|
| 2712 |
|
|
#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */
|
| 2713 |
|
|
#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
|
| 2714 |
|
|
#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
|
| 2715 |
|
|
the Flash memory is in power down mode) */
|
| 2716 |
|
|
#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */
|
| 2717 |
|
|
|
| 2718 |
|
|
|
| 2719 |
|
|
/****************** Bit definition for RCC_APB2ENR register *****************/
|
| 2720 |
|
|
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */
|
| 2721 |
|
|
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */
|
| 2722 |
|
|
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */
|
| 2723 |
|
|
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */
|
| 2724 |
|
|
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
|
| 2725 |
|
|
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
|
| 2726 |
|
|
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
|
| 2727 |
|
|
|
| 2728 |
|
|
|
| 2729 |
|
|
/***************** Bit definition for RCC_APB1ENR register ******************/
|
| 2730 |
|
|
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
|
| 2731 |
|
|
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
|
| 2732 |
|
|
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
|
| 2733 |
|
|
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
|
| 2734 |
|
|
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
|
| 2735 |
|
|
#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
|
| 2736 |
|
|
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
|
| 2737 |
|
|
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
|
| 2738 |
|
|
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
|
| 2739 |
|
|
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
|
| 2740 |
|
|
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
|
| 2741 |
|
|
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
|
| 2742 |
|
|
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
|
| 2743 |
|
|
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
|
| 2744 |
|
|
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
|
| 2745 |
|
|
#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */
|
| 2746 |
|
|
|
| 2747 |
|
|
/****************** Bit definition for RCC_AHBLPENR register ****************/
|
| 2748 |
|
|
#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
|
| 2749 |
|
|
#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
|
| 2750 |
|
|
#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
|
| 2751 |
|
|
#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
|
| 2752 |
|
|
#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
|
| 2753 |
|
|
#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */
|
| 2754 |
|
|
#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
|
| 2755 |
|
|
#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
|
| 2756 |
|
|
(has effect only when the Flash memory is
|
| 2757 |
|
|
in power down mode) */
|
| 2758 |
|
|
#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */
|
| 2759 |
|
|
#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */
|
| 2760 |
|
|
|
| 2761 |
|
|
/****************** Bit definition for RCC_APB2LPENR register ***************/
|
| 2762 |
|
|
#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */
|
| 2763 |
|
|
#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */
|
| 2764 |
|
|
#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */
|
| 2765 |
|
|
#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */
|
| 2766 |
|
|
#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
|
| 2767 |
|
|
#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
|
| 2768 |
|
|
#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
|
| 2769 |
|
|
|
| 2770 |
|
|
/***************** Bit definition for RCC_APB1LPENR register ****************/
|
| 2771 |
|
|
#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
|
| 2772 |
|
|
#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
|
| 2773 |
|
|
#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */
|
| 2774 |
|
|
#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
|
| 2775 |
|
|
#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
|
| 2776 |
|
|
#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
|
| 2777 |
|
|
#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
|
| 2778 |
|
|
#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */
|
| 2779 |
|
|
#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */
|
| 2780 |
|
|
#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */
|
| 2781 |
|
|
#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */
|
| 2782 |
|
|
#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */
|
| 2783 |
|
|
#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
|
| 2784 |
|
|
#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */
|
| 2785 |
|
|
#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */
|
| 2786 |
|
|
#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/
|
| 2787 |
|
|
|
| 2788 |
|
|
/******************* Bit definition for RCC_CSR register ********************/
|
| 2789 |
|
|
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
|
| 2790 |
|
|
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
|
| 2791 |
|
|
|
| 2792 |
|
|
#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
|
| 2793 |
|
|
#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
|
| 2794 |
|
|
#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
|
| 2795 |
|
|
|
| 2796 |
|
|
#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
|
| 2797 |
|
|
#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
| 2798 |
|
|
#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
| 2799 |
|
|
|
| 2800 |
|
|
/*!< RTC congiguration */
|
| 2801 |
|
|
#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
|
| 2802 |
|
|
#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
|
| 2803 |
|
|
#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
|
| 2804 |
|
|
#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
|
| 2805 |
|
|
|
| 2806 |
|
|
#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
|
| 2807 |
|
|
#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
|
| 2808 |
|
|
|
| 2809 |
|
|
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
|
| 2810 |
|
|
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
|
| 2811 |
|
|
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
|
| 2812 |
|
|
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
|
| 2813 |
|
|
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
|
| 2814 |
|
|
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
|
| 2815 |
|
|
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
|
| 2816 |
|
|
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
|
| 2817 |
|
|
|
| 2818 |
|
|
|
| 2819 |
|
|
/******************************************************************************/
|
| 2820 |
|
|
/* */
|
| 2821 |
|
|
/* Real-Time Clock */
|
| 2822 |
|
|
/* */
|
| 2823 |
|
|
/******************************************************************************/
|
| 2824 |
|
|
/******************** Bits definition for RTC_TR register *******************/
|
| 2825 |
|
|
#define RTC_TR_PM ((uint32_t)0x00400000)
|
| 2826 |
|
|
#define RTC_TR_HT ((uint32_t)0x00300000)
|
| 2827 |
|
|
#define RTC_TR_HT_0 ((uint32_t)0x00100000)
|
| 2828 |
|
|
#define RTC_TR_HT_1 ((uint32_t)0x00200000)
|
| 2829 |
|
|
#define RTC_TR_HU ((uint32_t)0x000F0000)
|
| 2830 |
|
|
#define RTC_TR_HU_0 ((uint32_t)0x00010000)
|
| 2831 |
|
|
#define RTC_TR_HU_1 ((uint32_t)0x00020000)
|
| 2832 |
|
|
#define RTC_TR_HU_2 ((uint32_t)0x00040000)
|
| 2833 |
|
|
#define RTC_TR_HU_3 ((uint32_t)0x00080000)
|
| 2834 |
|
|
#define RTC_TR_MNT ((uint32_t)0x00007000)
|
| 2835 |
|
|
#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
|
| 2836 |
|
|
#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
|
| 2837 |
|
|
#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
|
| 2838 |
|
|
#define RTC_TR_MNU ((uint32_t)0x00000F00)
|
| 2839 |
|
|
#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
|
| 2840 |
|
|
#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
|
| 2841 |
|
|
#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
|
| 2842 |
|
|
#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
|
| 2843 |
|
|
#define RTC_TR_ST ((uint32_t)0x00000070)
|
| 2844 |
|
|
#define RTC_TR_ST_0 ((uint32_t)0x00000010)
|
| 2845 |
|
|
#define RTC_TR_ST_1 ((uint32_t)0x00000020)
|
| 2846 |
|
|
#define RTC_TR_ST_2 ((uint32_t)0x00000040)
|
| 2847 |
|
|
#define RTC_TR_SU ((uint32_t)0x0000000F)
|
| 2848 |
|
|
#define RTC_TR_SU_0 ((uint32_t)0x00000001)
|
| 2849 |
|
|
#define RTC_TR_SU_1 ((uint32_t)0x00000002)
|
| 2850 |
|
|
#define RTC_TR_SU_2 ((uint32_t)0x00000004)
|
| 2851 |
|
|
#define RTC_TR_SU_3 ((uint32_t)0x00000008)
|
| 2852 |
|
|
|
| 2853 |
|
|
/******************** Bits definition for RTC_DR register *******************/
|
| 2854 |
|
|
#define RTC_DR_YT ((uint32_t)0x00F00000)
|
| 2855 |
|
|
#define RTC_DR_YT_0 ((uint32_t)0x00100000)
|
| 2856 |
|
|
#define RTC_DR_YT_1 ((uint32_t)0x00200000)
|
| 2857 |
|
|
#define RTC_DR_YT_2 ((uint32_t)0x00400000)
|
| 2858 |
|
|
#define RTC_DR_YT_3 ((uint32_t)0x00800000)
|
| 2859 |
|
|
#define RTC_DR_YU ((uint32_t)0x000F0000)
|
| 2860 |
|
|
#define RTC_DR_YU_0 ((uint32_t)0x00010000)
|
| 2861 |
|
|
#define RTC_DR_YU_1 ((uint32_t)0x00020000)
|
| 2862 |
|
|
#define RTC_DR_YU_2 ((uint32_t)0x00040000)
|
| 2863 |
|
|
#define RTC_DR_YU_3 ((uint32_t)0x00080000)
|
| 2864 |
|
|
#define RTC_DR_WDU ((uint32_t)0x0000E000)
|
| 2865 |
|
|
#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
|
| 2866 |
|
|
#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
|
| 2867 |
|
|
#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
|
| 2868 |
|
|
#define RTC_DR_MT ((uint32_t)0x00001000)
|
| 2869 |
|
|
#define RTC_DR_MU ((uint32_t)0x00000F00)
|
| 2870 |
|
|
#define RTC_DR_MU_0 ((uint32_t)0x00000100)
|
| 2871 |
|
|
#define RTC_DR_MU_1 ((uint32_t)0x00000200)
|
| 2872 |
|
|
#define RTC_DR_MU_2 ((uint32_t)0x00000400)
|
| 2873 |
|
|
#define RTC_DR_MU_3 ((uint32_t)0x00000800)
|
| 2874 |
|
|
#define RTC_DR_DT ((uint32_t)0x00000030)
|
| 2875 |
|
|
#define RTC_DR_DT_0 ((uint32_t)0x00000010)
|
| 2876 |
|
|
#define RTC_DR_DT_1 ((uint32_t)0x00000020)
|
| 2877 |
|
|
#define RTC_DR_DU ((uint32_t)0x0000000F)
|
| 2878 |
|
|
#define RTC_DR_DU_0 ((uint32_t)0x00000001)
|
| 2879 |
|
|
#define RTC_DR_DU_1 ((uint32_t)0x00000002)
|
| 2880 |
|
|
#define RTC_DR_DU_2 ((uint32_t)0x00000004)
|
| 2881 |
|
|
#define RTC_DR_DU_3 ((uint32_t)0x00000008)
|
| 2882 |
|
|
|
| 2883 |
|
|
/******************** Bits definition for RTC_CR register *******************/
|
| 2884 |
|
|
#define RTC_CR_COE ((uint32_t)0x00800000)
|
| 2885 |
|
|
#define RTC_CR_OSEL ((uint32_t)0x00600000)
|
| 2886 |
|
|
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
|
| 2887 |
|
|
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
|
| 2888 |
|
|
#define RTC_CR_POL ((uint32_t)0x00100000)
|
| 2889 |
|
|
#define RTC_CR_BCK ((uint32_t)0x00040000)
|
| 2890 |
|
|
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
|
| 2891 |
|
|
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
|
| 2892 |
|
|
#define RTC_CR_TSIE ((uint32_t)0x00008000)
|
| 2893 |
|
|
#define RTC_CR_WUTIE ((uint32_t)0x00004000)
|
| 2894 |
|
|
#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
|
| 2895 |
|
|
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
|
| 2896 |
|
|
#define RTC_CR_TSE ((uint32_t)0x00000800)
|
| 2897 |
|
|
#define RTC_CR_WUTE ((uint32_t)0x00000400)
|
| 2898 |
|
|
#define RTC_CR_ALRBE ((uint32_t)0x00000200)
|
| 2899 |
|
|
#define RTC_CR_ALRAE ((uint32_t)0x00000100)
|
| 2900 |
|
|
#define RTC_CR_DCE ((uint32_t)0x00000080)
|
| 2901 |
|
|
#define RTC_CR_FMT ((uint32_t)0x00000040)
|
| 2902 |
|
|
#define RTC_CR_REFCKON ((uint32_t)0x00000010)
|
| 2903 |
|
|
#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
|
| 2904 |
|
|
#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
|
| 2905 |
|
|
#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
|
| 2906 |
|
|
#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
|
| 2907 |
|
|
#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
|
| 2908 |
|
|
|
| 2909 |
|
|
/******************** Bits definition for RTC_ISR register ******************/
|
| 2910 |
|
|
#define RTC_ISR_TAMPF ((uint32_t)0x00002000)
|
| 2911 |
|
|
#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
|
| 2912 |
|
|
#define RTC_ISR_TSF ((uint32_t)0x00000800)
|
| 2913 |
|
|
#define RTC_ISR_WUTF ((uint32_t)0x00000400)
|
| 2914 |
|
|
#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
|
| 2915 |
|
|
#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
|
| 2916 |
|
|
#define RTC_ISR_INIT ((uint32_t)0x00000080)
|
| 2917 |
|
|
#define RTC_ISR_INITF ((uint32_t)0x00000040)
|
| 2918 |
|
|
#define RTC_ISR_RSF ((uint32_t)0x00000020)
|
| 2919 |
|
|
#define RTC_ISR_INITS ((uint32_t)0x00000010)
|
| 2920 |
|
|
#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
|
| 2921 |
|
|
#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
|
| 2922 |
|
|
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
|
| 2923 |
|
|
|
| 2924 |
|
|
/******************** Bits definition for RTC_PRER register *****************/
|
| 2925 |
|
|
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
| 2926 |
|
|
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
| 2927 |
|
|
|
| 2928 |
|
|
/******************** Bits definition for RTC_WUTR register *****************/
|
| 2929 |
|
|
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
| 2930 |
|
|
|
| 2931 |
|
|
/******************** Bits definition for RTC_CALIBR register ***************/
|
| 2932 |
|
|
#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
|
| 2933 |
|
|
#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
|
| 2934 |
|
|
|
| 2935 |
|
|
/******************** Bits definition for RTC_ALRMAR register ***************/
|
| 2936 |
|
|
#define RTC_ALRMAR_MSK3 ((uint32_t)0x80000000)
|
| 2937 |
|
|
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
|
| 2938 |
|
|
#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
|
| 2939 |
|
|
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
|
| 2940 |
|
|
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
|
| 2941 |
|
|
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
|
| 2942 |
|
|
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
|
| 2943 |
|
|
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
|
| 2944 |
|
|
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
|
| 2945 |
|
|
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
|
| 2946 |
|
|
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00800000)
|
| 2947 |
|
|
#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
|
| 2948 |
|
|
#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
|
| 2949 |
|
|
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
|
| 2950 |
|
|
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
|
| 2951 |
|
|
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
|
| 2952 |
|
|
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
|
| 2953 |
|
|
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
|
| 2954 |
|
|
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
|
| 2955 |
|
|
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
|
| 2956 |
|
|
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00008000)
|
| 2957 |
|
|
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
|
| 2958 |
|
|
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
|
| 2959 |
|
|
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
|
| 2960 |
|
|
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
|
| 2961 |
|
|
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
|
| 2962 |
|
|
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
|
| 2963 |
|
|
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
|
| 2964 |
|
|
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
|
| 2965 |
|
|
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
|
| 2966 |
|
|
#define RTC_ALRMAR_MSK0 ((uint32_t)0x00000080)
|
| 2967 |
|
|
#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
|
| 2968 |
|
|
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
|
| 2969 |
|
|
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
|
| 2970 |
|
|
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
|
| 2971 |
|
|
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
|
| 2972 |
|
|
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
|
| 2973 |
|
|
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
|
| 2974 |
|
|
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
|
| 2975 |
|
|
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
|
| 2976 |
|
|
|
| 2977 |
|
|
/******************** Bits definition for RTC_ALRMBR register ***************/
|
| 2978 |
|
|
#define RTC_ALRMBR_MSK3 ((uint32_t)0x80000000)
|
| 2979 |
|
|
#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
|
| 2980 |
|
|
#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
|
| 2981 |
|
|
#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
|
| 2982 |
|
|
#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
|
| 2983 |
|
|
#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
|
| 2984 |
|
|
#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
|
| 2985 |
|
|
#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
|
| 2986 |
|
|
#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
|
| 2987 |
|
|
#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
|
| 2988 |
|
|
#define RTC_ALRMBR_MSK2 ((uint32_t)0x00800000)
|
| 2989 |
|
|
#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
|
| 2990 |
|
|
#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
|
| 2991 |
|
|
#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
|
| 2992 |
|
|
#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
|
| 2993 |
|
|
#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
|
| 2994 |
|
|
#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
|
| 2995 |
|
|
#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
|
| 2996 |
|
|
#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
|
| 2997 |
|
|
#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
|
| 2998 |
|
|
#define RTC_ALRMBR_MSK1 ((uint32_t)0x00008000)
|
| 2999 |
|
|
#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
|
| 3000 |
|
|
#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
|
| 3001 |
|
|
#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
|
| 3002 |
|
|
#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
|
| 3003 |
|
|
#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
|
| 3004 |
|
|
#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
|
| 3005 |
|
|
#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
|
| 3006 |
|
|
#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
|
| 3007 |
|
|
#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
|
| 3008 |
|
|
#define RTC_ALRMBR_MSK0 ((uint32_t)0x00000080)
|
| 3009 |
|
|
#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
|
| 3010 |
|
|
#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
|
| 3011 |
|
|
#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
|
| 3012 |
|
|
#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
|
| 3013 |
|
|
#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
|
| 3014 |
|
|
#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
|
| 3015 |
|
|
#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
|
| 3016 |
|
|
#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
|
| 3017 |
|
|
#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
|
| 3018 |
|
|
|
| 3019 |
|
|
/******************** Bits definition for RTC_WRP register ******************/
|
| 3020 |
|
|
#define RTC_WRP_KEY ((uint32_t)0x000000FF)
|
| 3021 |
|
|
|
| 3022 |
|
|
/******************** Bits definition for RTC_TSTR register *****************/
|
| 3023 |
|
|
#define RTC_TSTR_PM ((uint32_t)0x00400000)
|
| 3024 |
|
|
#define RTC_TSTR_HT ((uint32_t)0x00300000)
|
| 3025 |
|
|
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
|
| 3026 |
|
|
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
|
| 3027 |
|
|
#define RTC_TSTR_HU ((uint32_t)0x000F0000)
|
| 3028 |
|
|
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
|
| 3029 |
|
|
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
|
| 3030 |
|
|
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
|
| 3031 |
|
|
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
|
| 3032 |
|
|
#define RTC_TSTR_MNT ((uint32_t)0x00007000)
|
| 3033 |
|
|
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
|
| 3034 |
|
|
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
|
| 3035 |
|
|
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
|
| 3036 |
|
|
#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
|
| 3037 |
|
|
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
|
| 3038 |
|
|
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
|
| 3039 |
|
|
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
|
| 3040 |
|
|
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
|
| 3041 |
|
|
#define RTC_TSTR_ST ((uint32_t)0x00000070)
|
| 3042 |
|
|
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
|
| 3043 |
|
|
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
|
| 3044 |
|
|
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
|
| 3045 |
|
|
#define RTC_TSTR_SU ((uint32_t)0x0000000F)
|
| 3046 |
|
|
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
|
| 3047 |
|
|
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
|
| 3048 |
|
|
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
|
| 3049 |
|
|
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
|
| 3050 |
|
|
|
| 3051 |
|
|
/******************** Bits definition for RTC_TSDR register *****************/
|
| 3052 |
|
|
#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
|
| 3053 |
|
|
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
|
| 3054 |
|
|
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
|
| 3055 |
|
|
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
|
| 3056 |
|
|
#define RTC_TSDR_MT ((uint32_t)0x00001000)
|
| 3057 |
|
|
#define RTC_TSDR_MU ((uint32_t)0x00000F00)
|
| 3058 |
|
|
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
|
| 3059 |
|
|
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
|
| 3060 |
|
|
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
|
| 3061 |
|
|
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
|
| 3062 |
|
|
#define RTC_TSDR_DT ((uint32_t)0x00000030)
|
| 3063 |
|
|
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
|
| 3064 |
|
|
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
|
| 3065 |
|
|
#define RTC_TSDR_DU ((uint32_t)0x0000000F)
|
| 3066 |
|
|
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
|
| 3067 |
|
|
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
|
| 3068 |
|
|
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
|
| 3069 |
|
|
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
|
| 3070 |
|
|
|
| 3071 |
|
|
/******************** Bits definition for RTC_TAFCR register ****************/
|
| 3072 |
|
|
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
|
| 3073 |
|
|
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
|
| 3074 |
|
|
#define RTC_TAFCR_TAMPEDGE ((uint32_t)0x00000002)
|
| 3075 |
|
|
#define RTC_TAFCR_TAMPE ((uint32_t)0x00000001)
|
| 3076 |
|
|
|
| 3077 |
|
|
/******************** Bits definition for RTC_BK0R register *****************/
|
| 3078 |
|
|
#define RTC_BK0R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3079 |
|
|
|
| 3080 |
|
|
/******************** Bits definition for RTC_BK1R register *****************/
|
| 3081 |
|
|
#define RTC_BK1R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3082 |
|
|
|
| 3083 |
|
|
/******************** Bits definition for RTC_BK2R register *****************/
|
| 3084 |
|
|
#define RTC_BK2R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3085 |
|
|
|
| 3086 |
|
|
/******************** Bits definition for RTC_BK3R register *****************/
|
| 3087 |
|
|
#define RTC_BK3R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3088 |
|
|
|
| 3089 |
|
|
/******************** Bits definition for RTC_BK4R register *****************/
|
| 3090 |
|
|
#define RTC_BK4R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3091 |
|
|
|
| 3092 |
|
|
/******************** Bits definition for RTC_BK5R register *****************/
|
| 3093 |
|
|
#define RTC_BK5R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3094 |
|
|
|
| 3095 |
|
|
/******************** Bits definition for RTC_BK6R register *****************/
|
| 3096 |
|
|
#define RTC_BK6R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3097 |
|
|
|
| 3098 |
|
|
/******************** Bits definition for RTC_BK7R register *****************/
|
| 3099 |
|
|
#define RTC_BK7R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3100 |
|
|
|
| 3101 |
|
|
/******************** Bits definition for RTC_BK8R register *****************/
|
| 3102 |
|
|
#define RTC_BK8R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3103 |
|
|
|
| 3104 |
|
|
/******************** Bits definition for RTC_BK9R register *****************/
|
| 3105 |
|
|
#define RTC_BK9R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3106 |
|
|
|
| 3107 |
|
|
/******************** Bits definition for RTC_BK10R register ****************/
|
| 3108 |
|
|
#define RTC_BK10R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3109 |
|
|
|
| 3110 |
|
|
/******************** Bits definition for RTC_BK11R register ****************/
|
| 3111 |
|
|
#define RTC_BK11R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3112 |
|
|
|
| 3113 |
|
|
/******************** Bits definition for RTC_BK12R register ****************/
|
| 3114 |
|
|
#define RTC_BK12R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3115 |
|
|
|
| 3116 |
|
|
/******************** Bits definition for RTC_BK13R register ****************/
|
| 3117 |
|
|
#define RTC_BK13R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3118 |
|
|
|
| 3119 |
|
|
/******************** Bits definition for RTC_BK14R register ****************/
|
| 3120 |
|
|
#define RTC_BK14R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3121 |
|
|
|
| 3122 |
|
|
/******************** Bits definition for RTC_BK15R register ****************/
|
| 3123 |
|
|
#define RTC_BK15R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3124 |
|
|
|
| 3125 |
|
|
/******************** Bits definition for RTC_BK16R register ****************/
|
| 3126 |
|
|
#define RTC_BK16R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3127 |
|
|
|
| 3128 |
|
|
/******************** Bits definition for RTC_BK17R register ****************/
|
| 3129 |
|
|
#define RTC_BK17R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3130 |
|
|
|
| 3131 |
|
|
/******************** Bits definition for RTC_BK18R register ****************/
|
| 3132 |
|
|
#define RTC_BK18R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3133 |
|
|
|
| 3134 |
|
|
/******************** Bits definition for RTC_BK19R register ****************/
|
| 3135 |
|
|
#define RTC_BK19R_BCK ((uint32_t)0xFFFFFFFF)
|
| 3136 |
|
|
|
| 3137 |
|
|
/******************************************************************************/
|
| 3138 |
|
|
/* */
|
| 3139 |
|
|
/* Serial Peripheral Interface */
|
| 3140 |
|
|
/* */
|
| 3141 |
|
|
/******************************************************************************/
|
| 3142 |
|
|
|
| 3143 |
|
|
/******************* Bit definition for SPI_CR1 register ********************/
|
| 3144 |
|
|
#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
|
| 3145 |
|
|
#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
|
| 3146 |
|
|
#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
|
| 3147 |
|
|
|
| 3148 |
|
|
#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
|
| 3149 |
|
|
#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
|
| 3150 |
|
|
#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
|
| 3151 |
|
|
#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
|
| 3152 |
|
|
|
| 3153 |
|
|
#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
|
| 3154 |
|
|
#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
|
| 3155 |
|
|
#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
|
| 3156 |
|
|
#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
|
| 3157 |
|
|
#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
|
| 3158 |
|
|
#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
|
| 3159 |
|
|
#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
|
| 3160 |
|
|
#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
|
| 3161 |
|
|
#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
|
| 3162 |
|
|
#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
|
| 3163 |
|
|
|
| 3164 |
|
|
/******************* Bit definition for SPI_CR2 register ********************/
|
| 3165 |
|
|
#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
|
| 3166 |
|
|
#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
|
| 3167 |
|
|
#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
|
| 3168 |
|
|
#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
|
| 3169 |
|
|
#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
|
| 3170 |
|
|
#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
|
| 3171 |
|
|
|
| 3172 |
|
|
/******************** Bit definition for SPI_SR register ********************/
|
| 3173 |
|
|
#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
|
| 3174 |
|
|
#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
|
| 3175 |
|
|
#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
|
| 3176 |
|
|
#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
|
| 3177 |
|
|
#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
|
| 3178 |
|
|
#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
|
| 3179 |
|
|
|
| 3180 |
|
|
/******************** Bit definition for SPI_DR register ********************/
|
| 3181 |
|
|
#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
|
| 3182 |
|
|
|
| 3183 |
|
|
/******************* Bit definition for SPI_CRCPR register ******************/
|
| 3184 |
|
|
#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
|
| 3185 |
|
|
|
| 3186 |
|
|
/****************** Bit definition for SPI_RXCRCR register ******************/
|
| 3187 |
|
|
#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
|
| 3188 |
|
|
|
| 3189 |
|
|
/****************** Bit definition for SPI_TXCRCR register ******************/
|
| 3190 |
|
|
#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
|
| 3191 |
|
|
|
| 3192 |
|
|
/******************************************************************************/
|
| 3193 |
|
|
/* */
|
| 3194 |
|
|
/* System Configuration (SYSCFG) */
|
| 3195 |
|
|
/* */
|
| 3196 |
|
|
/******************************************************************************/
|
| 3197 |
|
|
/***************** Bit definition for SYSCFG_MEMRMP register ****************/
|
| 3198 |
|
|
#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
| 3199 |
|
|
#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 3200 |
|
|
#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 3201 |
|
|
|
| 3202 |
|
|
/***************** Bit definition for SYSCFG_PMC register *******************/
|
| 3203 |
|
|
#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */
|
| 3204 |
|
|
|
| 3205 |
|
|
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
| 3206 |
|
|
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
|
| 3207 |
|
|
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
|
| 3208 |
|
|
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
|
| 3209 |
|
|
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
|
| 3210 |
|
|
|
| 3211 |
|
|
/**
|
| 3212 |
|
|
* @brief EXTI0 configuration
|
| 3213 |
|
|
*/
|
| 3214 |
|
|
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
|
| 3215 |
|
|
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
|
| 3216 |
|
|
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
|
| 3217 |
|
|
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
|
| 3218 |
|
|
#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
|
| 3219 |
|
|
#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */
|
| 3220 |
|
|
|
| 3221 |
|
|
/**
|
| 3222 |
|
|
* @brief EXTI1 configuration
|
| 3223 |
|
|
*/
|
| 3224 |
|
|
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
|
| 3225 |
|
|
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
|
| 3226 |
|
|
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
|
| 3227 |
|
|
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
|
| 3228 |
|
|
#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
|
| 3229 |
|
|
#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */
|
| 3230 |
|
|
|
| 3231 |
|
|
/**
|
| 3232 |
|
|
* @brief EXTI2 configuration
|
| 3233 |
|
|
*/
|
| 3234 |
|
|
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
|
| 3235 |
|
|
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
|
| 3236 |
|
|
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
|
| 3237 |
|
|
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
|
| 3238 |
|
|
#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
|
| 3239 |
|
|
#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */
|
| 3240 |
|
|
|
| 3241 |
|
|
/**
|
| 3242 |
|
|
* @brief EXTI3 configuration
|
| 3243 |
|
|
*/
|
| 3244 |
|
|
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
|
| 3245 |
|
|
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
|
| 3246 |
|
|
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
|
| 3247 |
|
|
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
|
| 3248 |
|
|
#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
|
| 3249 |
|
|
|
| 3250 |
|
|
/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
|
| 3251 |
|
|
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
|
| 3252 |
|
|
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
|
| 3253 |
|
|
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
|
| 3254 |
|
|
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
|
| 3255 |
|
|
|
| 3256 |
|
|
/**
|
| 3257 |
|
|
* @brief EXTI4 configuration
|
| 3258 |
|
|
*/
|
| 3259 |
|
|
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
|
| 3260 |
|
|
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
|
| 3261 |
|
|
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
|
| 3262 |
|
|
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
|
| 3263 |
|
|
#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
|
| 3264 |
|
|
|
| 3265 |
|
|
/**
|
| 3266 |
|
|
* @brief EXTI5 configuration
|
| 3267 |
|
|
*/
|
| 3268 |
|
|
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
|
| 3269 |
|
|
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
|
| 3270 |
|
|
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
|
| 3271 |
|
|
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
|
| 3272 |
|
|
#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
|
| 3273 |
|
|
|
| 3274 |
|
|
/**
|
| 3275 |
|
|
* @brief EXTI6 configuration
|
| 3276 |
|
|
*/
|
| 3277 |
|
|
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
|
| 3278 |
|
|
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
|
| 3279 |
|
|
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
|
| 3280 |
|
|
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
|
| 3281 |
|
|
#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
|
| 3282 |
|
|
|
| 3283 |
|
|
/**
|
| 3284 |
|
|
* @brief EXTI7 configuration
|
| 3285 |
|
|
*/
|
| 3286 |
|
|
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
|
| 3287 |
|
|
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
|
| 3288 |
|
|
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
|
| 3289 |
|
|
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
|
| 3290 |
|
|
#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
|
| 3291 |
|
|
|
| 3292 |
|
|
/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
|
| 3293 |
|
|
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
|
| 3294 |
|
|
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
|
| 3295 |
|
|
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
|
| 3296 |
|
|
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
|
| 3297 |
|
|
|
| 3298 |
|
|
/**
|
| 3299 |
|
|
* @brief EXTI8 configuration
|
| 3300 |
|
|
*/
|
| 3301 |
|
|
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
|
| 3302 |
|
|
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
|
| 3303 |
|
|
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
|
| 3304 |
|
|
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
|
| 3305 |
|
|
#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
|
| 3306 |
|
|
|
| 3307 |
|
|
/**
|
| 3308 |
|
|
* @brief EXTI9 configuration
|
| 3309 |
|
|
*/
|
| 3310 |
|
|
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
|
| 3311 |
|
|
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
|
| 3312 |
|
|
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
|
| 3313 |
|
|
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
|
| 3314 |
|
|
#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
|
| 3315 |
|
|
|
| 3316 |
|
|
/**
|
| 3317 |
|
|
* @brief EXTI10 configuration
|
| 3318 |
|
|
*/
|
| 3319 |
|
|
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
|
| 3320 |
|
|
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
|
| 3321 |
|
|
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
|
| 3322 |
|
|
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
|
| 3323 |
|
|
#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
|
| 3324 |
|
|
|
| 3325 |
|
|
/**
|
| 3326 |
|
|
* @brief EXTI11 configuration
|
| 3327 |
|
|
*/
|
| 3328 |
|
|
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
|
| 3329 |
|
|
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
|
| 3330 |
|
|
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
|
| 3331 |
|
|
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
|
| 3332 |
|
|
#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
|
| 3333 |
|
|
|
| 3334 |
|
|
/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
|
| 3335 |
|
|
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
|
| 3336 |
|
|
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
|
| 3337 |
|
|
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
|
| 3338 |
|
|
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
|
| 3339 |
|
|
|
| 3340 |
|
|
/**
|
| 3341 |
|
|
* @brief EXTI12 configuration
|
| 3342 |
|
|
*/
|
| 3343 |
|
|
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
|
| 3344 |
|
|
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
|
| 3345 |
|
|
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
|
| 3346 |
|
|
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
|
| 3347 |
|
|
#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
|
| 3348 |
|
|
|
| 3349 |
|
|
/**
|
| 3350 |
|
|
* @brief EXTI13 configuration
|
| 3351 |
|
|
*/
|
| 3352 |
|
|
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
|
| 3353 |
|
|
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
|
| 3354 |
|
|
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
|
| 3355 |
|
|
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
|
| 3356 |
|
|
#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
|
| 3357 |
|
|
|
| 3358 |
|
|
/**
|
| 3359 |
|
|
* @brief EXTI14 configuration
|
| 3360 |
|
|
*/
|
| 3361 |
|
|
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
|
| 3362 |
|
|
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
|
| 3363 |
|
|
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
|
| 3364 |
|
|
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
|
| 3365 |
|
|
#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
|
| 3366 |
|
|
|
| 3367 |
|
|
/**
|
| 3368 |
|
|
* @brief EXTI15 configuration
|
| 3369 |
|
|
*/
|
| 3370 |
|
|
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
|
| 3371 |
|
|
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
|
| 3372 |
|
|
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
|
| 3373 |
|
|
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
|
| 3374 |
|
|
#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
|
| 3375 |
|
|
|
| 3376 |
|
|
/******************************************************************************/
|
| 3377 |
|
|
/* */
|
| 3378 |
|
|
/* Routing Interface (RI) */
|
| 3379 |
|
|
/* */
|
| 3380 |
|
|
/******************************************************************************/
|
| 3381 |
|
|
|
| 3382 |
|
|
/******************** Bit definition for RI_ICR register ********************/
|
| 3383 |
|
|
#define RI_ICR_IC1Z ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */
|
| 3384 |
|
|
#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 3385 |
|
|
#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 3386 |
|
|
#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 3387 |
|
|
#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 3388 |
|
|
|
| 3389 |
|
|
#define RI_ICR_IC2Z ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
|
| 3390 |
|
|
#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
| 3391 |
|
|
#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
| 3392 |
|
|
#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
| 3393 |
|
|
#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /*!< Bit 3 */
|
| 3394 |
|
|
|
| 3395 |
|
|
#define RI_ICR_IC3Z ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */
|
| 3396 |
|
|
#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
| 3397 |
|
|
#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
| 3398 |
|
|
#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /*!< Bit 2 */
|
| 3399 |
|
|
#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /*!< Bit 3 */
|
| 3400 |
|
|
|
| 3401 |
|
|
#define RI_ICR_IC4Z ((uint32_t)0x0000F000) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
|
| 3402 |
|
|
#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /*!< Bit 0 */
|
| 3403 |
|
|
#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /*!< Bit 1 */
|
| 3404 |
|
|
#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /*!< Bit 2 */
|
| 3405 |
|
|
#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /*!< Bit 3 */
|
| 3406 |
|
|
|
| 3407 |
|
|
#define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
|
| 3408 |
|
|
#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
| 3409 |
|
|
#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
| 3410 |
|
|
|
| 3411 |
|
|
#define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */
|
| 3412 |
|
|
#define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */
|
| 3413 |
|
|
#define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */
|
| 3414 |
|
|
#define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */
|
| 3415 |
|
|
|
| 3416 |
|
|
/******************** Bit definition for RI_ASCR1 register ********************/
|
| 3417 |
|
|
#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
|
| 3418 |
|
|
#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 3419 |
|
|
#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 3420 |
|
|
#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 3421 |
|
|
#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 3422 |
|
|
#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 3423 |
|
|
#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
| 3424 |
|
|
#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
| 3425 |
|
|
#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
| 3426 |
|
|
#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
| 3427 |
|
|
#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
| 3428 |
|
|
#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
| 3429 |
|
|
#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
| 3430 |
|
|
#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
| 3431 |
|
|
#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
| 3432 |
|
|
#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
| 3433 |
|
|
#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
| 3434 |
|
|
#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */
|
| 3435 |
|
|
#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */
|
| 3436 |
|
|
#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */
|
| 3437 |
|
|
#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */
|
| 3438 |
|
|
#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */
|
| 3439 |
|
|
#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */
|
| 3440 |
|
|
#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */
|
| 3441 |
|
|
#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */
|
| 3442 |
|
|
|
| 3443 |
|
|
#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
|
| 3444 |
|
|
#define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */
|
| 3445 |
|
|
|
| 3446 |
|
|
/******************** Bit definition for RI_ASCR2 register ********************/
|
| 3447 |
|
|
#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
|
| 3448 |
|
|
#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
|
| 3449 |
|
|
#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
|
| 3450 |
|
|
#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
|
| 3451 |
|
|
#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
|
| 3452 |
|
|
#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
|
| 3453 |
|
|
#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
|
| 3454 |
|
|
#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
|
| 3455 |
|
|
#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
|
| 3456 |
|
|
#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
|
| 3457 |
|
|
#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
|
| 3458 |
|
|
#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
|
| 3459 |
|
|
|
| 3460 |
|
|
|
| 3461 |
|
|
/******************** Bit definition for RI_HYSCR1 register ********************/
|
| 3462 |
|
|
#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
|
| 3463 |
|
|
#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 3464 |
|
|
#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 3465 |
|
|
#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 3466 |
|
|
#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 3467 |
|
|
#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 3468 |
|
|
#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
| 3469 |
|
|
#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
| 3470 |
|
|
#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
| 3471 |
|
|
#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
| 3472 |
|
|
#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
| 3473 |
|
|
#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
| 3474 |
|
|
#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
| 3475 |
|
|
#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
| 3476 |
|
|
#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
| 3477 |
|
|
#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
| 3478 |
|
|
#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
| 3479 |
|
|
|
| 3480 |
|
|
#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
|
| 3481 |
|
|
#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
| 3482 |
|
|
#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
| 3483 |
|
|
#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */
|
| 3484 |
|
|
#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */
|
| 3485 |
|
|
#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */
|
| 3486 |
|
|
#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */
|
| 3487 |
|
|
#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */
|
| 3488 |
|
|
#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */
|
| 3489 |
|
|
#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */
|
| 3490 |
|
|
#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */
|
| 3491 |
|
|
#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */
|
| 3492 |
|
|
#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */
|
| 3493 |
|
|
#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */
|
| 3494 |
|
|
#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */
|
| 3495 |
|
|
#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */
|
| 3496 |
|
|
#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */
|
| 3497 |
|
|
|
| 3498 |
|
|
/******************** Bit definition for RI_HYSCR2 register ********************/
|
| 3499 |
|
|
#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
|
| 3500 |
|
|
#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 3501 |
|
|
#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 3502 |
|
|
#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 3503 |
|
|
#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 3504 |
|
|
#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 3505 |
|
|
#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
| 3506 |
|
|
#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
| 3507 |
|
|
#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
| 3508 |
|
|
#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
| 3509 |
|
|
#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
| 3510 |
|
|
#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
| 3511 |
|
|
#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
| 3512 |
|
|
#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
| 3513 |
|
|
#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
| 3514 |
|
|
#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
| 3515 |
|
|
#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
| 3516 |
|
|
|
| 3517 |
|
|
#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
|
| 3518 |
|
|
#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
| 3519 |
|
|
#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
| 3520 |
|
|
#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
|
| 3521 |
|
|
#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
|
| 3522 |
|
|
#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
|
| 3523 |
|
|
#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
|
| 3524 |
|
|
#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
|
| 3525 |
|
|
#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
|
| 3526 |
|
|
#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */
|
| 3527 |
|
|
#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */
|
| 3528 |
|
|
#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */
|
| 3529 |
|
|
#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */
|
| 3530 |
|
|
#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */
|
| 3531 |
|
|
#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */
|
| 3532 |
|
|
#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */
|
| 3533 |
|
|
#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */
|
| 3534 |
|
|
|
| 3535 |
|
|
/******************** Bit definition for RI_HYSCR3 register ********************/
|
| 3536 |
|
|
#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
|
| 3537 |
|
|
#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
| 3538 |
|
|
#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
| 3539 |
|
|
#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
| 3540 |
|
|
#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
| 3541 |
|
|
#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
| 3542 |
|
|
#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
| 3543 |
|
|
#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
| 3544 |
|
|
#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
| 3545 |
|
|
#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
| 3546 |
|
|
#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
| 3547 |
|
|
#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
| 3548 |
|
|
#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
| 3549 |
|
|
#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
| 3550 |
|
|
#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
| 3551 |
|
|
#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
| 3552 |
|
|
#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
| 3553 |
|
|
|
| 3554 |
|
|
/******************************************************************************/
|
| 3555 |
|
|
/* */
|
| 3556 |
|
|
/* TIM */
|
| 3557 |
|
|
/* */
|
| 3558 |
|
|
/******************************************************************************/
|
| 3559 |
|
|
|
| 3560 |
|
|
/******************* Bit definition for TIM_CR1 register ********************/
|
| 3561 |
|
|
#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
|
| 3562 |
|
|
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
|
| 3563 |
|
|
#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
|
| 3564 |
|
|
#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
|
| 3565 |
|
|
#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
|
| 3566 |
|
|
|
| 3567 |
|
|
#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
|
| 3568 |
|
|
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
|
| 3569 |
|
|
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
|
| 3570 |
|
|
|
| 3571 |
|
|
#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
|
| 3572 |
|
|
|
| 3573 |
|
|
#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
|
| 3574 |
|
|
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3575 |
|
|
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3576 |
|
|
|
| 3577 |
|
|
/******************* Bit definition for TIM_CR2 register ********************/
|
| 3578 |
|
|
#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
|
| 3579 |
|
|
#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
|
| 3580 |
|
|
#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
|
| 3581 |
|
|
|
| 3582 |
|
|
#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
|
| 3583 |
|
|
#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3584 |
|
|
#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3585 |
|
|
#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3586 |
|
|
|
| 3587 |
|
|
#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
|
| 3588 |
|
|
#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
|
| 3589 |
|
|
#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
|
| 3590 |
|
|
#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
|
| 3591 |
|
|
#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
|
| 3592 |
|
|
#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
|
| 3593 |
|
|
#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
|
| 3594 |
|
|
#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
|
| 3595 |
|
|
|
| 3596 |
|
|
/******************* Bit definition for TIM_SMCR register *******************/
|
| 3597 |
|
|
#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
|
| 3598 |
|
|
#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3599 |
|
|
#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3600 |
|
|
#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
|
| 3601 |
|
|
|
| 3602 |
|
|
#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!<OCCS bits (OCref Clear Selection) */
|
| 3603 |
|
|
|
| 3604 |
|
|
#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
|
| 3605 |
|
|
#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3606 |
|
|
#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3607 |
|
|
#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3608 |
|
|
|
| 3609 |
|
|
#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
|
| 3610 |
|
|
|
| 3611 |
|
|
#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
|
| 3612 |
|
|
#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3613 |
|
|
#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3614 |
|
|
#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
|
| 3615 |
|
|
#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
|
| 3616 |
|
|
|
| 3617 |
|
|
#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
|
| 3618 |
|
|
#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3619 |
|
|
#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3620 |
|
|
|
| 3621 |
|
|
#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
|
| 3622 |
|
|
#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
|
| 3623 |
|
|
|
| 3624 |
|
|
/******************* Bit definition for TIM_DIER register *******************/
|
| 3625 |
|
|
#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
|
| 3626 |
|
|
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
|
| 3627 |
|
|
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
|
| 3628 |
|
|
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
|
| 3629 |
|
|
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
|
| 3630 |
|
|
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
|
| 3631 |
|
|
#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
|
| 3632 |
|
|
#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
|
| 3633 |
|
|
#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
|
| 3634 |
|
|
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
|
| 3635 |
|
|
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
|
| 3636 |
|
|
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
|
| 3637 |
|
|
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
|
| 3638 |
|
|
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
|
| 3639 |
|
|
#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
|
| 3640 |
|
|
|
| 3641 |
|
|
/******************** Bit definition for TIM_SR register ********************/
|
| 3642 |
|
|
#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
|
| 3643 |
|
|
#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
|
| 3644 |
|
|
#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
|
| 3645 |
|
|
#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
|
| 3646 |
|
|
#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
|
| 3647 |
|
|
#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
|
| 3648 |
|
|
#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
|
| 3649 |
|
|
#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
|
| 3650 |
|
|
#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
|
| 3651 |
|
|
#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
|
| 3652 |
|
|
#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
|
| 3653 |
|
|
#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
|
| 3654 |
|
|
|
| 3655 |
|
|
/******************* Bit definition for TIM_EGR register ********************/
|
| 3656 |
|
|
#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
|
| 3657 |
|
|
#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
|
| 3658 |
|
|
#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
|
| 3659 |
|
|
#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
|
| 3660 |
|
|
#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
|
| 3661 |
|
|
#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
|
| 3662 |
|
|
#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
|
| 3663 |
|
|
#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
|
| 3664 |
|
|
|
| 3665 |
|
|
/****************** Bit definition for TIM_CCMR1 register *******************/
|
| 3666 |
|
|
#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
|
| 3667 |
|
|
#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3668 |
|
|
#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3669 |
|
|
|
| 3670 |
|
|
#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
|
| 3671 |
|
|
#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
|
| 3672 |
|
|
|
| 3673 |
|
|
#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
|
| 3674 |
|
|
#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3675 |
|
|
#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3676 |
|
|
#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3677 |
|
|
|
| 3678 |
|
|
#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
|
| 3679 |
|
|
|
| 3680 |
|
|
#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
|
| 3681 |
|
|
#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3682 |
|
|
#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3683 |
|
|
|
| 3684 |
|
|
#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
|
| 3685 |
|
|
#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
|
| 3686 |
|
|
|
| 3687 |
|
|
#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
|
| 3688 |
|
|
#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3689 |
|
|
#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3690 |
|
|
#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
|
| 3691 |
|
|
|
| 3692 |
|
|
#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
|
| 3693 |
|
|
|
| 3694 |
|
|
/*----------------------------------------------------------------------------*/
|
| 3695 |
|
|
|
| 3696 |
|
|
#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
|
| 3697 |
|
|
#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
|
| 3698 |
|
|
#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
|
| 3699 |
|
|
|
| 3700 |
|
|
#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
|
| 3701 |
|
|
#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3702 |
|
|
#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3703 |
|
|
#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3704 |
|
|
#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
|
| 3705 |
|
|
|
| 3706 |
|
|
#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
|
| 3707 |
|
|
#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 3708 |
|
|
#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 3709 |
|
|
|
| 3710 |
|
|
#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
|
| 3711 |
|
|
#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3712 |
|
|
#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3713 |
|
|
#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
|
| 3714 |
|
|
#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
|
| 3715 |
|
|
|
| 3716 |
|
|
/****************** Bit definition for TIM_CCMR2 register *******************/
|
| 3717 |
|
|
#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
|
| 3718 |
|
|
#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3719 |
|
|
#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3720 |
|
|
|
| 3721 |
|
|
#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
|
| 3722 |
|
|
#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
|
| 3723 |
|
|
|
| 3724 |
|
|
#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
| 3725 |
|
|
#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3726 |
|
|
#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3727 |
|
|
#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3728 |
|
|
|
| 3729 |
|
|
#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
|
| 3730 |
|
|
|
| 3731 |
|
|
#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
|
| 3732 |
|
|
#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3733 |
|
|
#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3734 |
|
|
|
| 3735 |
|
|
#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
|
| 3736 |
|
|
#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
|
| 3737 |
|
|
|
| 3738 |
|
|
#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
| 3739 |
|
|
#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3740 |
|
|
#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3741 |
|
|
#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
|
| 3742 |
|
|
|
| 3743 |
|
|
#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
|
| 3744 |
|
|
|
| 3745 |
|
|
/*----------------------------------------------------------------------------*/
|
| 3746 |
|
|
|
| 3747 |
|
|
#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
|
| 3748 |
|
|
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
|
| 3749 |
|
|
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
|
| 3750 |
|
|
|
| 3751 |
|
|
#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
|
| 3752 |
|
|
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3753 |
|
|
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3754 |
|
|
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
|
| 3755 |
|
|
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
|
| 3756 |
|
|
|
| 3757 |
|
|
#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
|
| 3758 |
|
|
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
|
| 3759 |
|
|
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
|
| 3760 |
|
|
|
| 3761 |
|
|
#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
|
| 3762 |
|
|
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3763 |
|
|
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3764 |
|
|
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
|
| 3765 |
|
|
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
|
| 3766 |
|
|
|
| 3767 |
|
|
/******************* Bit definition for TIM_CCER register *******************/
|
| 3768 |
|
|
#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
|
| 3769 |
|
|
#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
|
| 3770 |
|
|
#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
|
| 3771 |
|
|
#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
|
| 3772 |
|
|
#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
|
| 3773 |
|
|
#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
|
| 3774 |
|
|
#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
|
| 3775 |
|
|
#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
|
| 3776 |
|
|
#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
|
| 3777 |
|
|
#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
|
| 3778 |
|
|
#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
|
| 3779 |
|
|
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
|
| 3780 |
|
|
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
|
| 3781 |
|
|
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
|
| 3782 |
|
|
#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
|
| 3783 |
|
|
|
| 3784 |
|
|
/******************* Bit definition for TIM_CNT register ********************/
|
| 3785 |
|
|
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
|
| 3786 |
|
|
|
| 3787 |
|
|
/******************* Bit definition for TIM_PSC register ********************/
|
| 3788 |
|
|
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
|
| 3789 |
|
|
|
| 3790 |
|
|
/******************* Bit definition for TIM_ARR register ********************/
|
| 3791 |
|
|
#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
|
| 3792 |
|
|
|
| 3793 |
|
|
/******************* Bit definition for TIM_RCR register ********************/
|
| 3794 |
|
|
#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
|
| 3795 |
|
|
|
| 3796 |
|
|
/******************* Bit definition for TIM_CCR1 register *******************/
|
| 3797 |
|
|
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
|
| 3798 |
|
|
|
| 3799 |
|
|
/******************* Bit definition for TIM_CCR2 register *******************/
|
| 3800 |
|
|
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
|
| 3801 |
|
|
|
| 3802 |
|
|
/******************* Bit definition for TIM_CCR3 register *******************/
|
| 3803 |
|
|
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
|
| 3804 |
|
|
|
| 3805 |
|
|
/******************* Bit definition for TIM_CCR4 register *******************/
|
| 3806 |
|
|
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
|
| 3807 |
|
|
|
| 3808 |
|
|
/******************* Bit definition for TIM_DCR register ********************/
|
| 3809 |
|
|
#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
|
| 3810 |
|
|
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3811 |
|
|
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3812 |
|
|
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
|
| 3813 |
|
|
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
|
| 3814 |
|
|
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
|
| 3815 |
|
|
|
| 3816 |
|
|
#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
|
| 3817 |
|
|
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
|
| 3818 |
|
|
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
|
| 3819 |
|
|
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
|
| 3820 |
|
|
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
|
| 3821 |
|
|
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
|
| 3822 |
|
|
|
| 3823 |
|
|
/******************* Bit definition for TIM_DMAR register *******************/
|
| 3824 |
|
|
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
|
| 3825 |
|
|
|
| 3826 |
|
|
/******************* Bit definition for TIM_OR register *********************/
|
| 3827 |
|
|
#define TIM_OR_TI1RMP ((uint16_t)0x0003) /*!<Option register for TI1 Remapping */
|
| 3828 |
|
|
#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
|
| 3829 |
|
|
#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
|
| 3830 |
|
|
|
| 3831 |
|
|
/******************************************************************************/
|
| 3832 |
|
|
/* */
|
| 3833 |
|
|
/* Universal Synchronous Asynchronous Receiver Transmitter */
|
| 3834 |
|
|
/* */
|
| 3835 |
|
|
/******************************************************************************/
|
| 3836 |
|
|
|
| 3837 |
|
|
/******************* Bit definition for USART_SR register *******************/
|
| 3838 |
|
|
#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
|
| 3839 |
|
|
#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
|
| 3840 |
|
|
#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
|
| 3841 |
|
|
#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
|
| 3842 |
|
|
#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
|
| 3843 |
|
|
#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
|
| 3844 |
|
|
#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
|
| 3845 |
|
|
#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
|
| 3846 |
|
|
#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
|
| 3847 |
|
|
#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
|
| 3848 |
|
|
|
| 3849 |
|
|
/******************* Bit definition for USART_DR register *******************/
|
| 3850 |
|
|
#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
|
| 3851 |
|
|
|
| 3852 |
|
|
/****************** Bit definition for USART_BRR register *******************/
|
| 3853 |
|
|
#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
|
| 3854 |
|
|
#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
|
| 3855 |
|
|
|
| 3856 |
|
|
/****************** Bit definition for USART_CR1 register *******************/
|
| 3857 |
|
|
#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
|
| 3858 |
|
|
#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
|
| 3859 |
|
|
#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
|
| 3860 |
|
|
#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
|
| 3861 |
|
|
#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
|
| 3862 |
|
|
#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
|
| 3863 |
|
|
#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
|
| 3864 |
|
|
#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
|
| 3865 |
|
|
#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
|
| 3866 |
|
|
#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
|
| 3867 |
|
|
#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
|
| 3868 |
|
|
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
|
| 3869 |
|
|
#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
|
| 3870 |
|
|
#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
|
| 3871 |
|
|
#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< Oversampling mode */
|
| 3872 |
|
|
|
| 3873 |
|
|
/****************** Bit definition for USART_CR2 register *******************/
|
| 3874 |
|
|
#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
|
| 3875 |
|
|
#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
|
| 3876 |
|
|
#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
|
| 3877 |
|
|
#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
|
| 3878 |
|
|
#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
|
| 3879 |
|
|
#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
|
| 3880 |
|
|
#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
|
| 3881 |
|
|
|
| 3882 |
|
|
#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
|
| 3883 |
|
|
#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
|
| 3884 |
|
|
#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
|
| 3885 |
|
|
|
| 3886 |
|
|
#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
|
| 3887 |
|
|
|
| 3888 |
|
|
/****************** Bit definition for USART_CR3 register *******************/
|
| 3889 |
|
|
#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
|
| 3890 |
|
|
#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
|
| 3891 |
|
|
#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
|
| 3892 |
|
|
#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
|
| 3893 |
|
|
#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
|
| 3894 |
|
|
#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
|
| 3895 |
|
|
#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
|
| 3896 |
|
|
#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
|
| 3897 |
|
|
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
|
| 3898 |
|
|
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
|
| 3899 |
|
|
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
|
| 3900 |
|
|
#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One sample bit method enable */
|
| 3901 |
|
|
|
| 3902 |
|
|
/****************** Bit definition for USART_GTPR register ******************/
|
| 3903 |
|
|
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
|
| 3904 |
|
|
#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
|
| 3905 |
|
|
#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
|
| 3906 |
|
|
#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
|
| 3907 |
|
|
#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
|
| 3908 |
|
|
#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
|
| 3909 |
|
|
#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
|
| 3910 |
|
|
#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
|
| 3911 |
|
|
#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
|
| 3912 |
|
|
|
| 3913 |
|
|
#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
|
| 3914 |
|
|
|
| 3915 |
|
|
/******************************************************************************/
|
| 3916 |
|
|
/* */
|
| 3917 |
|
|
/* USB */
|
| 3918 |
|
|
/* */
|
| 3919 |
|
|
/******************************************************************************/
|
| 3920 |
|
|
|
| 3921 |
|
|
/*!<Endpoint-specific registers */
|
| 3922 |
|
|
/******************* Bit definition for USB_EP0R register *******************/
|
| 3923 |
|
|
#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 3924 |
|
|
|
| 3925 |
|
|
#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 3926 |
|
|
#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3927 |
|
|
#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3928 |
|
|
|
| 3929 |
|
|
#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 3930 |
|
|
#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 3931 |
|
|
#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 3932 |
|
|
|
| 3933 |
|
|
#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 3934 |
|
|
#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 3935 |
|
|
#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 3936 |
|
|
|
| 3937 |
|
|
#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 3938 |
|
|
|
| 3939 |
|
|
#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 3940 |
|
|
#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3941 |
|
|
#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3942 |
|
|
|
| 3943 |
|
|
#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 3944 |
|
|
#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 3945 |
|
|
|
| 3946 |
|
|
/******************* Bit definition for USB_EP1R register *******************/
|
| 3947 |
|
|
#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 3948 |
|
|
|
| 3949 |
|
|
#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 3950 |
|
|
#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3951 |
|
|
#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3952 |
|
|
|
| 3953 |
|
|
#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 3954 |
|
|
#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 3955 |
|
|
#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 3956 |
|
|
|
| 3957 |
|
|
#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 3958 |
|
|
#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 3959 |
|
|
#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 3960 |
|
|
|
| 3961 |
|
|
#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 3962 |
|
|
|
| 3963 |
|
|
#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 3964 |
|
|
#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3965 |
|
|
#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3966 |
|
|
|
| 3967 |
|
|
#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 3968 |
|
|
#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 3969 |
|
|
|
| 3970 |
|
|
/******************* Bit definition for USB_EP2R register *******************/
|
| 3971 |
|
|
#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 3972 |
|
|
|
| 3973 |
|
|
#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 3974 |
|
|
#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3975 |
|
|
#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 3976 |
|
|
|
| 3977 |
|
|
#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 3978 |
|
|
#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 3979 |
|
|
#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 3980 |
|
|
|
| 3981 |
|
|
#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 3982 |
|
|
#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 3983 |
|
|
#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 3984 |
|
|
|
| 3985 |
|
|
#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 3986 |
|
|
|
| 3987 |
|
|
#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 3988 |
|
|
#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 3989 |
|
|
#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 3990 |
|
|
|
| 3991 |
|
|
#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 3992 |
|
|
#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 3993 |
|
|
|
| 3994 |
|
|
/******************* Bit definition for USB_EP3R register *******************/
|
| 3995 |
|
|
#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 3996 |
|
|
|
| 3997 |
|
|
#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 3998 |
|
|
#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 3999 |
|
|
#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 4000 |
|
|
|
| 4001 |
|
|
#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 4002 |
|
|
#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 4003 |
|
|
#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 4004 |
|
|
|
| 4005 |
|
|
#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 4006 |
|
|
#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 4007 |
|
|
#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 4008 |
|
|
|
| 4009 |
|
|
#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 4010 |
|
|
|
| 4011 |
|
|
#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 4012 |
|
|
#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 4013 |
|
|
#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 4014 |
|
|
|
| 4015 |
|
|
#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 4016 |
|
|
#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 4017 |
|
|
|
| 4018 |
|
|
/******************* Bit definition for USB_EP4R register *******************/
|
| 4019 |
|
|
#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 4020 |
|
|
|
| 4021 |
|
|
#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 4022 |
|
|
#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 4023 |
|
|
#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 4024 |
|
|
|
| 4025 |
|
|
#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 4026 |
|
|
#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 4027 |
|
|
#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 4028 |
|
|
|
| 4029 |
|
|
#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 4030 |
|
|
#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 4031 |
|
|
#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 4032 |
|
|
|
| 4033 |
|
|
#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 4034 |
|
|
|
| 4035 |
|
|
#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 4036 |
|
|
#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 4037 |
|
|
#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 4038 |
|
|
|
| 4039 |
|
|
#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 4040 |
|
|
#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 4041 |
|
|
|
| 4042 |
|
|
/******************* Bit definition for USB_EP5R register *******************/
|
| 4043 |
|
|
#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 4044 |
|
|
|
| 4045 |
|
|
#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 4046 |
|
|
#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 4047 |
|
|
#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 4048 |
|
|
|
| 4049 |
|
|
#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 4050 |
|
|
#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 4051 |
|
|
#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 4052 |
|
|
|
| 4053 |
|
|
#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 4054 |
|
|
#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 4055 |
|
|
#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 4056 |
|
|
|
| 4057 |
|
|
#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 4058 |
|
|
|
| 4059 |
|
|
#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 4060 |
|
|
#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 4061 |
|
|
#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 4062 |
|
|
|
| 4063 |
|
|
#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 4064 |
|
|
#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 4065 |
|
|
|
| 4066 |
|
|
/******************* Bit definition for USB_EP6R register *******************/
|
| 4067 |
|
|
#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 4068 |
|
|
|
| 4069 |
|
|
#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 4070 |
|
|
#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 4071 |
|
|
#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 4072 |
|
|
|
| 4073 |
|
|
#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 4074 |
|
|
#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 4075 |
|
|
#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 4076 |
|
|
|
| 4077 |
|
|
#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 4078 |
|
|
#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 4079 |
|
|
#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 4080 |
|
|
|
| 4081 |
|
|
#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 4082 |
|
|
|
| 4083 |
|
|
#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 4084 |
|
|
#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 4085 |
|
|
#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 4086 |
|
|
|
| 4087 |
|
|
#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 4088 |
|
|
#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 4089 |
|
|
|
| 4090 |
|
|
/******************* Bit definition for USB_EP7R register *******************/
|
| 4091 |
|
|
#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
|
| 4092 |
|
|
|
| 4093 |
|
|
#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
|
| 4094 |
|
|
#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
|
| 4095 |
|
|
#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
|
| 4096 |
|
|
|
| 4097 |
|
|
#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
|
| 4098 |
|
|
#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
|
| 4099 |
|
|
#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
|
| 4100 |
|
|
|
| 4101 |
|
|
#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
|
| 4102 |
|
|
#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
|
| 4103 |
|
|
#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
|
| 4104 |
|
|
|
| 4105 |
|
|
#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
|
| 4106 |
|
|
|
| 4107 |
|
|
#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
|
| 4108 |
|
|
#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
|
| 4109 |
|
|
#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
|
| 4110 |
|
|
|
| 4111 |
|
|
#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
|
| 4112 |
|
|
#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
|
| 4113 |
|
|
|
| 4114 |
|
|
/*!<Common registers */
|
| 4115 |
|
|
/******************* Bit definition for USB_CNTR register *******************/
|
| 4116 |
|
|
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
|
| 4117 |
|
|
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
|
| 4118 |
|
|
#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
|
| 4119 |
|
|
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
|
| 4120 |
|
|
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
|
| 4121 |
|
|
#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
|
| 4122 |
|
|
#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
|
| 4123 |
|
|
#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
|
| 4124 |
|
|
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
|
| 4125 |
|
|
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
|
| 4126 |
|
|
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
|
| 4127 |
|
|
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
|
| 4128 |
|
|
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
|
| 4129 |
|
|
|
| 4130 |
|
|
/******************* Bit definition for USB_ISTR register *******************/
|
| 4131 |
|
|
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
|
| 4132 |
|
|
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
|
| 4133 |
|
|
#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
|
| 4134 |
|
|
#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
|
| 4135 |
|
|
#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
|
| 4136 |
|
|
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
|
| 4137 |
|
|
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
|
| 4138 |
|
|
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
|
| 4139 |
|
|
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
|
| 4140 |
|
|
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
|
| 4141 |
|
|
|
| 4142 |
|
|
/******************* Bit definition for USB_FNR register ********************/
|
| 4143 |
|
|
#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
|
| 4144 |
|
|
#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
|
| 4145 |
|
|
#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
|
| 4146 |
|
|
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
|
| 4147 |
|
|
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
|
| 4148 |
|
|
|
| 4149 |
|
|
/****************** Bit definition for USB_DADDR register *******************/
|
| 4150 |
|
|
#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
|
| 4151 |
|
|
#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
|
| 4152 |
|
|
#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
|
| 4153 |
|
|
#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
|
| 4154 |
|
|
#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
|
| 4155 |
|
|
#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
|
| 4156 |
|
|
#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
|
| 4157 |
|
|
#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
|
| 4158 |
|
|
|
| 4159 |
|
|
#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
|
| 4160 |
|
|
|
| 4161 |
|
|
/****************** Bit definition for USB_BTABLE register ******************/
|
| 4162 |
|
|
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
|
| 4163 |
|
|
|
| 4164 |
|
|
/*!< Buffer descriptor table */
|
| 4165 |
|
|
/***************** Bit definition for USB_ADDR0_TX register *****************/
|
| 4166 |
|
|
#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
|
| 4167 |
|
|
|
| 4168 |
|
|
/***************** Bit definition for USB_ADDR1_TX register *****************/
|
| 4169 |
|
|
#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
|
| 4170 |
|
|
|
| 4171 |
|
|
/***************** Bit definition for USB_ADDR2_TX register *****************/
|
| 4172 |
|
|
#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
|
| 4173 |
|
|
|
| 4174 |
|
|
/***************** Bit definition for USB_ADDR3_TX register *****************/
|
| 4175 |
|
|
#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
|
| 4176 |
|
|
|
| 4177 |
|
|
/***************** Bit definition for USB_ADDR4_TX register *****************/
|
| 4178 |
|
|
#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
|
| 4179 |
|
|
|
| 4180 |
|
|
/***************** Bit definition for USB_ADDR5_TX register *****************/
|
| 4181 |
|
|
#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
|
| 4182 |
|
|
|
| 4183 |
|
|
/***************** Bit definition for USB_ADDR6_TX register *****************/
|
| 4184 |
|
|
#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
|
| 4185 |
|
|
|
| 4186 |
|
|
/***************** Bit definition for USB_ADDR7_TX register *****************/
|
| 4187 |
|
|
#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
|
| 4188 |
|
|
|
| 4189 |
|
|
/*----------------------------------------------------------------------------*/
|
| 4190 |
|
|
|
| 4191 |
|
|
/***************** Bit definition for USB_COUNT0_TX register ****************/
|
| 4192 |
|
|
#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
|
| 4193 |
|
|
|
| 4194 |
|
|
/***************** Bit definition for USB_COUNT1_TX register ****************/
|
| 4195 |
|
|
#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
|
| 4196 |
|
|
|
| 4197 |
|
|
/***************** Bit definition for USB_COUNT2_TX register ****************/
|
| 4198 |
|
|
#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
|
| 4199 |
|
|
|
| 4200 |
|
|
/***************** Bit definition for USB_COUNT3_TX register ****************/
|
| 4201 |
|
|
#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
|
| 4202 |
|
|
|
| 4203 |
|
|
/***************** Bit definition for USB_COUNT4_TX register ****************/
|
| 4204 |
|
|
#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
|
| 4205 |
|
|
|
| 4206 |
|
|
/***************** Bit definition for USB_COUNT5_TX register ****************/
|
| 4207 |
|
|
#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
|
| 4208 |
|
|
|
| 4209 |
|
|
/***************** Bit definition for USB_COUNT6_TX register ****************/
|
| 4210 |
|
|
#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
|
| 4211 |
|
|
|
| 4212 |
|
|
/***************** Bit definition for USB_COUNT7_TX register ****************/
|
| 4213 |
|
|
#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
|
| 4214 |
|
|
|
| 4215 |
|
|
/*----------------------------------------------------------------------------*/
|
| 4216 |
|
|
|
| 4217 |
|
|
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
|
| 4218 |
|
|
#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
|
| 4219 |
|
|
|
| 4220 |
|
|
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
|
| 4221 |
|
|
#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
|
| 4222 |
|
|
|
| 4223 |
|
|
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
|
| 4224 |
|
|
#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
|
| 4225 |
|
|
|
| 4226 |
|
|
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
|
| 4227 |
|
|
#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
|
| 4228 |
|
|
|
| 4229 |
|
|
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
|
| 4230 |
|
|
#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
|
| 4231 |
|
|
|
| 4232 |
|
|
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
|
| 4233 |
|
|
#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
|
| 4234 |
|
|
|
| 4235 |
|
|
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
|
| 4236 |
|
|
#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
|
| 4237 |
|
|
|
| 4238 |
|
|
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
|
| 4239 |
|
|
#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
|
| 4240 |
|
|
|
| 4241 |
|
|
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
|
| 4242 |
|
|
#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
|
| 4243 |
|
|
|
| 4244 |
|
|
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
|
| 4245 |
|
|
#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
|
| 4246 |
|
|
|
| 4247 |
|
|
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
|
| 4248 |
|
|
#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
|
| 4249 |
|
|
|
| 4250 |
|
|
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
|
| 4251 |
|
|
#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
|
| 4252 |
|
|
|
| 4253 |
|
|
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
|
| 4254 |
|
|
#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
|
| 4255 |
|
|
|
| 4256 |
|
|
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
|
| 4257 |
|
|
#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
|
| 4258 |
|
|
|
| 4259 |
|
|
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
|
| 4260 |
|
|
#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
|
| 4261 |
|
|
|
| 4262 |
|
|
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
|
| 4263 |
|
|
#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
|
| 4264 |
|
|
|
| 4265 |
|
|
/*----------------------------------------------------------------------------*/
|
| 4266 |
|
|
|
| 4267 |
|
|
/***************** Bit definition for USB_ADDR0_RX register *****************/
|
| 4268 |
|
|
#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
|
| 4269 |
|
|
|
| 4270 |
|
|
/***************** Bit definition for USB_ADDR1_RX register *****************/
|
| 4271 |
|
|
#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
|
| 4272 |
|
|
|
| 4273 |
|
|
/***************** Bit definition for USB_ADDR2_RX register *****************/
|
| 4274 |
|
|
#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
|
| 4275 |
|
|
|
| 4276 |
|
|
/***************** Bit definition for USB_ADDR3_RX register *****************/
|
| 4277 |
|
|
#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
|
| 4278 |
|
|
|
| 4279 |
|
|
/***************** Bit definition for USB_ADDR4_RX register *****************/
|
| 4280 |
|
|
#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
|
| 4281 |
|
|
|
| 4282 |
|
|
/***************** Bit definition for USB_ADDR5_RX register *****************/
|
| 4283 |
|
|
#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
|
| 4284 |
|
|
|
| 4285 |
|
|
/***************** Bit definition for USB_ADDR6_RX register *****************/
|
| 4286 |
|
|
#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
|
| 4287 |
|
|
|
| 4288 |
|
|
/***************** Bit definition for USB_ADDR7_RX register *****************/
|
| 4289 |
|
|
#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
|
| 4290 |
|
|
|
| 4291 |
|
|
/*----------------------------------------------------------------------------*/
|
| 4292 |
|
|
|
| 4293 |
|
|
/***************** Bit definition for USB_COUNT0_RX register ****************/
|
| 4294 |
|
|
#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
|
| 4295 |
|
|
|
| 4296 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 4297 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 4298 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 4299 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
|
| 4300 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
|
| 4301 |
|
|
#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
|
| 4302 |
|
|
|
| 4303 |
|
|
#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
|
| 4304 |
|
|
|
| 4305 |
|
|
/***************** Bit definition for USB_COUNT1_RX register ****************/
|
| 4306 |
|
|
#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
|
| 4307 |
|
|
|
| 4308 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 4309 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 4310 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 4311 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
|
| 4312 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
|
| 4313 |
|
|
#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
|
| 4314 |
|
|
|
| 4315 |
|
|
#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
|
| 4316 |
|
|
|
| 4317 |
|
|
/***************** Bit definition for USB_COUNT2_RX register ****************/
|
| 4318 |
|
|
#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
|
| 4319 |
|
|
|
| 4320 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 4321 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 4322 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 4323 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
|
| 4324 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
|
| 4325 |
|
|
#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
|
| 4326 |
|
|
|
| 4327 |
|
|
#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
|
| 4328 |
|
|
|
| 4329 |
|
|
/***************** Bit definition for USB_COUNT3_RX register ****************/
|
| 4330 |
|
|
#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
|
| 4331 |
|
|
|
| 4332 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 4333 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 4334 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 4335 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
|
| 4336 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
|
| 4337 |
|
|
#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
|
| 4338 |
|
|
|
| 4339 |
|
|
#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
|
| 4340 |
|
|
|
| 4341 |
|
|
/***************** Bit definition for USB_COUNT4_RX register ****************/
|
| 4342 |
|
|
#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
|
| 4343 |
|
|
|
| 4344 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 4345 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 4346 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 4347 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
|
| 4348 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
|
| 4349 |
|
|
#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
|
| 4350 |
|
|
|
| 4351 |
|
|
#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
|
| 4352 |
|
|
|
| 4353 |
|
|
/***************** Bit definition for USB_COUNT5_RX register ****************/
|
| 4354 |
|
|
#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
|
| 4355 |
|
|
|
| 4356 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 4357 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 4358 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 4359 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
|
| 4360 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
|
| 4361 |
|
|
#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
|
| 4362 |
|
|
|
| 4363 |
|
|
#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
|
| 4364 |
|
|
|
| 4365 |
|
|
/***************** Bit definition for USB_COUNT6_RX register ****************/
|
| 4366 |
|
|
#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
|
| 4367 |
|
|
|
| 4368 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 4369 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 4370 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 4371 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
|
| 4372 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
|
| 4373 |
|
|
#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
|
| 4374 |
|
|
|
| 4375 |
|
|
#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
|
| 4376 |
|
|
|
| 4377 |
|
|
/***************** Bit definition for USB_COUNT7_RX register ****************/
|
| 4378 |
|
|
#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
|
| 4379 |
|
|
|
| 4380 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
|
| 4381 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
|
| 4382 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
|
| 4383 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
|
| 4384 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
|
| 4385 |
|
|
#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
|
| 4386 |
|
|
|
| 4387 |
|
|
#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
|
| 4388 |
|
|
|
| 4389 |
|
|
/*----------------------------------------------------------------------------*/
|
| 4390 |
|
|
|
| 4391 |
|
|
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
|
| 4392 |
|
|
#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
|
| 4393 |
|
|
|
| 4394 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 4395 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 4396 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 4397 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 4398 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 4399 |
|
|
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 4400 |
|
|
|
| 4401 |
|
|
#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
|
| 4402 |
|
|
|
| 4403 |
|
|
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
|
| 4404 |
|
|
#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
|
| 4405 |
|
|
|
| 4406 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 4407 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
|
| 4408 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
|
| 4409 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
|
| 4410 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
|
| 4411 |
|
|
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
|
| 4412 |
|
|
|
| 4413 |
|
|
#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
|
| 4414 |
|
|
|
| 4415 |
|
|
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
|
| 4416 |
|
|
#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
|
| 4417 |
|
|
|
| 4418 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 4419 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 4420 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 4421 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 4422 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 4423 |
|
|
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 4424 |
|
|
|
| 4425 |
|
|
#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
|
| 4426 |
|
|
|
| 4427 |
|
|
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
|
| 4428 |
|
|
#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
|
| 4429 |
|
|
|
| 4430 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 4431 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
|
| 4432 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
|
| 4433 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
|
| 4434 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
|
| 4435 |
|
|
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
|
| 4436 |
|
|
|
| 4437 |
|
|
#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
|
| 4438 |
|
|
|
| 4439 |
|
|
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
|
| 4440 |
|
|
#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
|
| 4441 |
|
|
|
| 4442 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 4443 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 4444 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 4445 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 4446 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 4447 |
|
|
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 4448 |
|
|
|
| 4449 |
|
|
#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
|
| 4450 |
|
|
|
| 4451 |
|
|
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
|
| 4452 |
|
|
#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
|
| 4453 |
|
|
|
| 4454 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 4455 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
|
| 4456 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
|
| 4457 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
|
| 4458 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
|
| 4459 |
|
|
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
|
| 4460 |
|
|
|
| 4461 |
|
|
#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
|
| 4462 |
|
|
|
| 4463 |
|
|
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
|
| 4464 |
|
|
#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
|
| 4465 |
|
|
|
| 4466 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 4467 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 4468 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 4469 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 4470 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 4471 |
|
|
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 4472 |
|
|
|
| 4473 |
|
|
#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
|
| 4474 |
|
|
|
| 4475 |
|
|
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
|
| 4476 |
|
|
#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
|
| 4477 |
|
|
|
| 4478 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 4479 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
|
| 4480 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
|
| 4481 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
|
| 4482 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
|
| 4483 |
|
|
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
|
| 4484 |
|
|
|
| 4485 |
|
|
#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
|
| 4486 |
|
|
|
| 4487 |
|
|
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
|
| 4488 |
|
|
#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
|
| 4489 |
|
|
|
| 4490 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 4491 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 4492 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 4493 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 4494 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 4495 |
|
|
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 4496 |
|
|
|
| 4497 |
|
|
#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
|
| 4498 |
|
|
|
| 4499 |
|
|
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
|
| 4500 |
|
|
#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
|
| 4501 |
|
|
|
| 4502 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 4503 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
|
| 4504 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
|
| 4505 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
|
| 4506 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
|
| 4507 |
|
|
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
|
| 4508 |
|
|
|
| 4509 |
|
|
#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
|
| 4510 |
|
|
|
| 4511 |
|
|
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
|
| 4512 |
|
|
#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
|
| 4513 |
|
|
|
| 4514 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 4515 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 4516 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 4517 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 4518 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 4519 |
|
|
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 4520 |
|
|
|
| 4521 |
|
|
#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
|
| 4522 |
|
|
|
| 4523 |
|
|
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
|
| 4524 |
|
|
#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
|
| 4525 |
|
|
|
| 4526 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 4527 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
|
| 4528 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
|
| 4529 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
|
| 4530 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
|
| 4531 |
|
|
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
|
| 4532 |
|
|
|
| 4533 |
|
|
#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
|
| 4534 |
|
|
|
| 4535 |
|
|
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
|
| 4536 |
|
|
#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
|
| 4537 |
|
|
|
| 4538 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 4539 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 4540 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 4541 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 4542 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 4543 |
|
|
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 4544 |
|
|
|
| 4545 |
|
|
#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
|
| 4546 |
|
|
|
| 4547 |
|
|
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
|
| 4548 |
|
|
#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
|
| 4549 |
|
|
|
| 4550 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 4551 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
|
| 4552 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
|
| 4553 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
|
| 4554 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
|
| 4555 |
|
|
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
|
| 4556 |
|
|
|
| 4557 |
|
|
#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
|
| 4558 |
|
|
|
| 4559 |
|
|
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
|
| 4560 |
|
|
#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
|
| 4561 |
|
|
|
| 4562 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
|
| 4563 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
| 4564 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
| 4565 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
| 4566 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
|
| 4567 |
|
|
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
|
| 4568 |
|
|
|
| 4569 |
|
|
#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
|
| 4570 |
|
|
|
| 4571 |
|
|
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
|
| 4572 |
|
|
#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
|
| 4573 |
|
|
|
| 4574 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
|
| 4575 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
|
| 4576 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
|
| 4577 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
|
| 4578 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
|
| 4579 |
|
|
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
|
| 4580 |
|
|
|
| 4581 |
|
|
#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
|
| 4582 |
|
|
|
| 4583 |
|
|
/******************************************************************************/
|
| 4584 |
|
|
/* */
|
| 4585 |
|
|
/* Window WATCHDOG */
|
| 4586 |
|
|
/* */
|
| 4587 |
|
|
/******************************************************************************/
|
| 4588 |
|
|
|
| 4589 |
|
|
/******************* Bit definition for WWDG_CR register ********************/
|
| 4590 |
|
|
#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
| 4591 |
|
|
#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
|
| 4592 |
|
|
#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
|
| 4593 |
|
|
#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
|
| 4594 |
|
|
#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
|
| 4595 |
|
|
#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
|
| 4596 |
|
|
#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
|
| 4597 |
|
|
#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
|
| 4598 |
|
|
|
| 4599 |
|
|
#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
|
| 4600 |
|
|
|
| 4601 |
|
|
/******************* Bit definition for WWDG_CFR register *******************/
|
| 4602 |
|
|
#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
|
| 4603 |
|
|
#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
|
| 4604 |
|
|
#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
|
| 4605 |
|
|
#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
|
| 4606 |
|
|
#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
|
| 4607 |
|
|
#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
|
| 4608 |
|
|
#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
|
| 4609 |
|
|
#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
|
| 4610 |
|
|
|
| 4611 |
|
|
#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
|
| 4612 |
|
|
#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
|
| 4613 |
|
|
#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
|
| 4614 |
|
|
|
| 4615 |
|
|
#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
|
| 4616 |
|
|
|
| 4617 |
|
|
/******************* Bit definition for WWDG_SR register ********************/
|
| 4618 |
|
|
#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
|
| 4619 |
|
|
|
| 4620 |
|
|
/******************************************************************************/
|
| 4621 |
|
|
/* */
|
| 4622 |
|
|
/* SystemTick */
|
| 4623 |
|
|
/* */
|
| 4624 |
|
|
/******************************************************************************/
|
| 4625 |
|
|
|
| 4626 |
|
|
/***************** Bit definition for SysTick_CTRL register *****************/
|
| 4627 |
|
|
#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
|
| 4628 |
|
|
#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
|
| 4629 |
|
|
#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
|
| 4630 |
|
|
#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
|
| 4631 |
|
|
|
| 4632 |
|
|
/***************** Bit definition for SysTick_LOAD register *****************/
|
| 4633 |
|
|
#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
|
| 4634 |
|
|
|
| 4635 |
|
|
/***************** Bit definition for SysTick_VAL register ******************/
|
| 4636 |
|
|
#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
|
| 4637 |
|
|
|
| 4638 |
|
|
/***************** Bit definition for SysTick_CALIB register ****************/
|
| 4639 |
|
|
#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
|
| 4640 |
|
|
#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
|
| 4641 |
|
|
#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
|
| 4642 |
|
|
|
| 4643 |
|
|
/******************************************************************************/
|
| 4644 |
|
|
/* */
|
| 4645 |
|
|
/* Nested Vectored Interrupt Controller */
|
| 4646 |
|
|
/* */
|
| 4647 |
|
|
/******************************************************************************/
|
| 4648 |
|
|
|
| 4649 |
|
|
/****************** Bit definition for NVIC_ISER register *******************/
|
| 4650 |
|
|
#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
|
| 4651 |
|
|
#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 4652 |
|
|
#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 4653 |
|
|
#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 4654 |
|
|
#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 4655 |
|
|
#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 4656 |
|
|
#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 4657 |
|
|
#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 4658 |
|
|
#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 4659 |
|
|
#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 4660 |
|
|
#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 4661 |
|
|
#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 4662 |
|
|
#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 4663 |
|
|
#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 4664 |
|
|
#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 4665 |
|
|
#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 4666 |
|
|
#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 4667 |
|
|
#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 4668 |
|
|
#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 4669 |
|
|
#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 4670 |
|
|
#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 4671 |
|
|
#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 4672 |
|
|
#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 4673 |
|
|
#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 4674 |
|
|
#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 4675 |
|
|
#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 4676 |
|
|
#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 4677 |
|
|
#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 4678 |
|
|
#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 4679 |
|
|
#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 4680 |
|
|
#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 4681 |
|
|
#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 4682 |
|
|
#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 4683 |
|
|
|
| 4684 |
|
|
/****************** Bit definition for NVIC_ICER register *******************/
|
| 4685 |
|
|
#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
|
| 4686 |
|
|
#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 4687 |
|
|
#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 4688 |
|
|
#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 4689 |
|
|
#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 4690 |
|
|
#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 4691 |
|
|
#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 4692 |
|
|
#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 4693 |
|
|
#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 4694 |
|
|
#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 4695 |
|
|
#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 4696 |
|
|
#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 4697 |
|
|
#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 4698 |
|
|
#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 4699 |
|
|
#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 4700 |
|
|
#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 4701 |
|
|
#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 4702 |
|
|
#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 4703 |
|
|
#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 4704 |
|
|
#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 4705 |
|
|
#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 4706 |
|
|
#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 4707 |
|
|
#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 4708 |
|
|
#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 4709 |
|
|
#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 4710 |
|
|
#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 4711 |
|
|
#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 4712 |
|
|
#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 4713 |
|
|
#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 4714 |
|
|
#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 4715 |
|
|
#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 4716 |
|
|
#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 4717 |
|
|
#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 4718 |
|
|
|
| 4719 |
|
|
/****************** Bit definition for NVIC_ISPR register *******************/
|
| 4720 |
|
|
#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
|
| 4721 |
|
|
#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 4722 |
|
|
#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 4723 |
|
|
#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 4724 |
|
|
#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 4725 |
|
|
#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 4726 |
|
|
#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 4727 |
|
|
#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 4728 |
|
|
#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 4729 |
|
|
#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 4730 |
|
|
#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 4731 |
|
|
#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 4732 |
|
|
#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 4733 |
|
|
#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 4734 |
|
|
#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 4735 |
|
|
#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 4736 |
|
|
#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 4737 |
|
|
#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 4738 |
|
|
#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 4739 |
|
|
#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 4740 |
|
|
#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 4741 |
|
|
#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 4742 |
|
|
#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 4743 |
|
|
#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 4744 |
|
|
#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 4745 |
|
|
#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 4746 |
|
|
#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 4747 |
|
|
#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 4748 |
|
|
#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 4749 |
|
|
#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 4750 |
|
|
#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 4751 |
|
|
#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 4752 |
|
|
#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 4753 |
|
|
|
| 4754 |
|
|
/****************** Bit definition for NVIC_ICPR register *******************/
|
| 4755 |
|
|
#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
|
| 4756 |
|
|
#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 4757 |
|
|
#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 4758 |
|
|
#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 4759 |
|
|
#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 4760 |
|
|
#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 4761 |
|
|
#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 4762 |
|
|
#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 4763 |
|
|
#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 4764 |
|
|
#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 4765 |
|
|
#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 4766 |
|
|
#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 4767 |
|
|
#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 4768 |
|
|
#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 4769 |
|
|
#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 4770 |
|
|
#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 4771 |
|
|
#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 4772 |
|
|
#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 4773 |
|
|
#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 4774 |
|
|
#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 4775 |
|
|
#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 4776 |
|
|
#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 4777 |
|
|
#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 4778 |
|
|
#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 4779 |
|
|
#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 4780 |
|
|
#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 4781 |
|
|
#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 4782 |
|
|
#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 4783 |
|
|
#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 4784 |
|
|
#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 4785 |
|
|
#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 4786 |
|
|
#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 4787 |
|
|
#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 4788 |
|
|
|
| 4789 |
|
|
/****************** Bit definition for NVIC_IABR register *******************/
|
| 4790 |
|
|
#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
|
| 4791 |
|
|
#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
|
| 4792 |
|
|
#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
|
| 4793 |
|
|
#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
|
| 4794 |
|
|
#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
|
| 4795 |
|
|
#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
|
| 4796 |
|
|
#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
|
| 4797 |
|
|
#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
|
| 4798 |
|
|
#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
|
| 4799 |
|
|
#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
|
| 4800 |
|
|
#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
|
| 4801 |
|
|
#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
|
| 4802 |
|
|
#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
|
| 4803 |
|
|
#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
|
| 4804 |
|
|
#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
|
| 4805 |
|
|
#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
|
| 4806 |
|
|
#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
|
| 4807 |
|
|
#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
|
| 4808 |
|
|
#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
|
| 4809 |
|
|
#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
|
| 4810 |
|
|
#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
|
| 4811 |
|
|
#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
|
| 4812 |
|
|
#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
|
| 4813 |
|
|
#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
|
| 4814 |
|
|
#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
|
| 4815 |
|
|
#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
|
| 4816 |
|
|
#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
|
| 4817 |
|
|
#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
|
| 4818 |
|
|
#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
|
| 4819 |
|
|
#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
|
| 4820 |
|
|
#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
|
| 4821 |
|
|
#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
|
| 4822 |
|
|
#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
|
| 4823 |
|
|
|
| 4824 |
|
|
/****************** Bit definition for NVIC_PRI0 register *******************/
|
| 4825 |
|
|
#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
|
| 4826 |
|
|
#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
|
| 4827 |
|
|
#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
|
| 4828 |
|
|
#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
|
| 4829 |
|
|
|
| 4830 |
|
|
/****************** Bit definition for NVIC_PRI1 register *******************/
|
| 4831 |
|
|
#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
|
| 4832 |
|
|
#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
|
| 4833 |
|
|
#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
|
| 4834 |
|
|
#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
|
| 4835 |
|
|
|
| 4836 |
|
|
/****************** Bit definition for NVIC_PRI2 register *******************/
|
| 4837 |
|
|
#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
|
| 4838 |
|
|
#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
|
| 4839 |
|
|
#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
|
| 4840 |
|
|
#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
|
| 4841 |
|
|
|
| 4842 |
|
|
/****************** Bit definition for NVIC_PRI3 register *******************/
|
| 4843 |
|
|
#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
|
| 4844 |
|
|
#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
|
| 4845 |
|
|
#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
|
| 4846 |
|
|
#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
|
| 4847 |
|
|
|
| 4848 |
|
|
/****************** Bit definition for NVIC_PRI4 register *******************/
|
| 4849 |
|
|
#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
|
| 4850 |
|
|
#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
|
| 4851 |
|
|
#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
|
| 4852 |
|
|
#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
|
| 4853 |
|
|
|
| 4854 |
|
|
/****************** Bit definition for NVIC_PRI5 register *******************/
|
| 4855 |
|
|
#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
|
| 4856 |
|
|
#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
|
| 4857 |
|
|
#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
|
| 4858 |
|
|
#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
|
| 4859 |
|
|
|
| 4860 |
|
|
/****************** Bit definition for NVIC_PRI6 register *******************/
|
| 4861 |
|
|
#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
|
| 4862 |
|
|
#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
|
| 4863 |
|
|
#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
|
| 4864 |
|
|
#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
|
| 4865 |
|
|
|
| 4866 |
|
|
/****************** Bit definition for NVIC_PRI7 register *******************/
|
| 4867 |
|
|
#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
|
| 4868 |
|
|
#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
|
| 4869 |
|
|
#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
|
| 4870 |
|
|
#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
|
| 4871 |
|
|
|
| 4872 |
|
|
/****************** Bit definition for SCB_CPUID register *******************/
|
| 4873 |
|
|
#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
|
| 4874 |
|
|
#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
|
| 4875 |
|
|
#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
|
| 4876 |
|
|
#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
|
| 4877 |
|
|
#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
|
| 4878 |
|
|
|
| 4879 |
|
|
/******************* Bit definition for SCB_ICSR register *******************/
|
| 4880 |
|
|
#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
|
| 4881 |
|
|
#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
|
| 4882 |
|
|
#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
|
| 4883 |
|
|
#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
|
| 4884 |
|
|
#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
|
| 4885 |
|
|
#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
|
| 4886 |
|
|
#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
|
| 4887 |
|
|
#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
|
| 4888 |
|
|
#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
|
| 4889 |
|
|
#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
|
| 4890 |
|
|
|
| 4891 |
|
|
/******************* Bit definition for SCB_VTOR register *******************/
|
| 4892 |
|
|
#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
|
| 4893 |
|
|
#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
|
| 4894 |
|
|
|
| 4895 |
|
|
/*!<***************** Bit definition for SCB_AIRCR register *******************/
|
| 4896 |
|
|
#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
|
| 4897 |
|
|
#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
|
| 4898 |
|
|
#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
|
| 4899 |
|
|
|
| 4900 |
|
|
#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
|
| 4901 |
|
|
#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
| 4902 |
|
|
#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
| 4903 |
|
|
#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
|
| 4904 |
|
|
|
| 4905 |
|
|
/* prority group configuration */
|
| 4906 |
|
|
#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
|
| 4907 |
|
|
#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
|
| 4908 |
|
|
#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
|
| 4909 |
|
|
#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
|
| 4910 |
|
|
#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
|
| 4911 |
|
|
#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
|
| 4912 |
|
|
#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
|
| 4913 |
|
|
#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
|
| 4914 |
|
|
|
| 4915 |
|
|
#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
|
| 4916 |
|
|
#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
|
| 4917 |
|
|
|
| 4918 |
|
|
/******************* Bit definition for SCB_SCR register ********************/
|
| 4919 |
|
|
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
|
| 4920 |
|
|
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
|
| 4921 |
|
|
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
|
| 4922 |
|
|
|
| 4923 |
|
|
/******************** Bit definition for SCB_CCR register *******************/
|
| 4924 |
|
|
#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
|
| 4925 |
|
|
#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
|
| 4926 |
|
|
#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
|
| 4927 |
|
|
#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
|
| 4928 |
|
|
#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
|
| 4929 |
|
|
#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
|
| 4930 |
|
|
|
| 4931 |
|
|
/******************* Bit definition for SCB_SHPR register ********************/
|
| 4932 |
|
|
#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
|
| 4933 |
|
|
#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
|
| 4934 |
|
|
#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
|
| 4935 |
|
|
#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
|
| 4936 |
|
|
|
| 4937 |
|
|
/****************** Bit definition for SCB_SHCSR register *******************/
|
| 4938 |
|
|
#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
|
| 4939 |
|
|
#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
|
| 4940 |
|
|
#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
|
| 4941 |
|
|
#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
|
| 4942 |
|
|
#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
|
| 4943 |
|
|
#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
|
| 4944 |
|
|
#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
|
| 4945 |
|
|
#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
|
| 4946 |
|
|
#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
|
| 4947 |
|
|
#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
|
| 4948 |
|
|
#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
|
| 4949 |
|
|
#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
|
| 4950 |
|
|
#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
|
| 4951 |
|
|
#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
|
| 4952 |
|
|
|
| 4953 |
|
|
/******************* Bit definition for SCB_CFSR register *******************/
|
| 4954 |
|
|
/*!< MFSR */
|
| 4955 |
|
|
#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
|
| 4956 |
|
|
#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
|
| 4957 |
|
|
#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
|
| 4958 |
|
|
#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
|
| 4959 |
|
|
#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
|
| 4960 |
|
|
/*!< BFSR */
|
| 4961 |
|
|
#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
|
| 4962 |
|
|
#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
|
| 4963 |
|
|
#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
|
| 4964 |
|
|
#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
|
| 4965 |
|
|
#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
|
| 4966 |
|
|
#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
|
| 4967 |
|
|
/*!< UFSR */
|
| 4968 |
|
|
#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
|
| 4969 |
|
|
#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
|
| 4970 |
|
|
#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
|
| 4971 |
|
|
#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
|
| 4972 |
|
|
#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
|
| 4973 |
|
|
#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
|
| 4974 |
|
|
|
| 4975 |
|
|
/******************* Bit definition for SCB_HFSR register *******************/
|
| 4976 |
|
|
#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
|
| 4977 |
|
|
#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
|
| 4978 |
|
|
#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
|
| 4979 |
|
|
|
| 4980 |
|
|
/******************* Bit definition for SCB_DFSR register *******************/
|
| 4981 |
|
|
#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
|
| 4982 |
|
|
#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
|
| 4983 |
|
|
#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
|
| 4984 |
|
|
#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
|
| 4985 |
|
|
#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
|
| 4986 |
|
|
|
| 4987 |
|
|
/******************* Bit definition for SCB_MMFAR register ******************/
|
| 4988 |
|
|
#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
|
| 4989 |
|
|
|
| 4990 |
|
|
/******************* Bit definition for SCB_BFAR register *******************/
|
| 4991 |
|
|
#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
|
| 4992 |
|
|
|
| 4993 |
|
|
/******************* Bit definition for SCB_afsr register *******************/
|
| 4994 |
|
|
#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
|
| 4995 |
|
|
/**
|
| 4996 |
|
|
* @}
|
| 4997 |
|
|
*/
|
| 4998 |
|
|
|
| 4999 |
|
|
/**
|
| 5000 |
|
|
* @}
|
| 5001 |
|
|
*/
|
| 5002 |
|
|
|
| 5003 |
|
|
#ifdef USE_STDPERIPH_DRIVER
|
| 5004 |
|
|
#include "stm32l1xx_conf.h"
|
| 5005 |
|
|
#endif
|
| 5006 |
|
|
|
| 5007 |
|
|
/** @addtogroup Exported_macro
|
| 5008 |
|
|
* @{
|
| 5009 |
|
|
*/
|
| 5010 |
|
|
|
| 5011 |
|
|
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
| 5012 |
|
|
|
| 5013 |
|
|
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
| 5014 |
|
|
|
| 5015 |
|
|
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
| 5016 |
|
|
|
| 5017 |
|
|
#define CLEAR_REG(REG) ((REG) = (0x0))
|
| 5018 |
|
|
|
| 5019 |
|
|
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
| 5020 |
|
|
|
| 5021 |
|
|
#define READ_REG(REG) ((REG))
|
| 5022 |
|
|
|
| 5023 |
|
|
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
| 5024 |
|
|
|
| 5025 |
|
|
/**
|
| 5026 |
|
|
* @}
|
| 5027 |
|
|
*/
|
| 5028 |
|
|
|
| 5029 |
|
|
#ifdef __cplusplus
|
| 5030 |
|
|
}
|
| 5031 |
|
|
#endif
|
| 5032 |
|
|
|
| 5033 |
|
|
#endif /* __STM32L1XX_H */
|
| 5034 |
|
|
|
| 5035 |
|
|
/**
|
| 5036 |
|
|
* @}
|
| 5037 |
|
|
*/
|
| 5038 |
|
|
|
| 5039 |
|
|
/**
|
| 5040 |
|
|
* @}
|
| 5041 |
|
|
*/
|
| 5042 |
|
|
|
| 5043 |
|
|
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|
