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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_STM32L152_IAR/] [system_and_ST_code/] [STM32L1xx_StdPeriph_Driver/] [inc/] [stm32l1xx_rcc.h] - Blame information for rev 582

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/**
  ******************************************************************************
  * @file    stm32l1xx_rcc.h
  * @author  MCD Application Team
  * @version V1.0.0RC1
  * @date    07/02/2010
  * @brief   This file contains all the functions prototypes for the RCC
  *          firmware library.
  ******************************************************************************
  * @copy
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
  */
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_RCC_H
#define __STM32L1xx_RCC_H
 
#ifdef __cplusplus
 extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
 
/** @addtogroup STM32L1xx_StdPeriph_Driver
  * @{
  */
 
/** @addtogroup RCC
  * @{
  */
 
/** @defgroup RCC_Exported_Types
  * @{
  */
 
typedef struct
{
  uint32_t SYSCLK_Frequency;
  uint32_t HCLK_Frequency;
  uint32_t PCLK1_Frequency;
  uint32_t PCLK2_Frequency;
}RCC_ClocksTypeDef;
 
/**
  * @}
  */
 
/** @defgroup RCC_Exported_Constants
  * @{
  */
 
/** @defgroup HSE_configuration
  * @{
  */
 
#define RCC_HSE_OFF                      ((uint8_t)0x00)
#define RCC_HSE_ON                       ((uint8_t)0x01)
#define RCC_HSE_Bypass                   ((uint8_t)0x05)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_Bypass))
 
/**
  * @}
  */
 
/** @defgroup MSI_Clock_Range
  * @{
  */
 
#define RCC_MSIRange_64KHz               RCC_ICSCR_MSIRANGE_64KHz
#define RCC_MSIRange_128KHz              RCC_ICSCR_MSIRANGE_128KHz
#define RCC_MSIRange_256KHz              RCC_ICSCR_MSIRANGE_256KHz
#define RCC_MSIRange_512KHz              RCC_ICSCR_MSIRANGE_512KHz
#define RCC_MSIRange_1MHz                RCC_ICSCR_MSIRANGE_1MHz
#define RCC_MSIRange_2MHz                RCC_ICSCR_MSIRANGE_2MHz
#define RCC_MSIRange_4MHz                RCC_ICSCR_MSIRANGE_4MHz
 
#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_64KHz) || \
                                       ((RANGE) == RCC_MSIRange_128KHz) || \
                                       ((RANGE) == RCC_MSIRange_256KHz) || \
                                       ((RANGE) == RCC_MSIRange_512KHz) || \
                                       ((RANGE) == RCC_MSIRange_1MHz) || \
                                       ((RANGE) == RCC_MSIRange_2MHz) || \
                                       ((RANGE) == RCC_MSIRange_4MHz))
 
/**
  * @}
  */
 
/** @defgroup PLL_Clock_Source
  * @{
  */
 
#define RCC_PLLSource_HSI                ((uint8_t)0x00)
#define RCC_PLLSource_HSE                ((uint8_t)0x01)
 
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
                                   ((SOURCE) == RCC_PLLSource_HSE))
/**
  * @}
  */
 
/** @defgroup PLL_Multiplication_Factor
  * @{
  */
 
#define RCC_PLLMul_3                     ((uint8_t)0x00)
#define RCC_PLLMul_4                     ((uint8_t)0x04)
#define RCC_PLLMul_6                     ((uint8_t)0x08)
#define RCC_PLLMul_8                     ((uint8_t)0x0C)
#define RCC_PLLMul_12                    ((uint8_t)0x10)
#define RCC_PLLMul_16                    ((uint8_t)0x14)
#define RCC_PLLMul_24                    ((uint8_t)0x18)
#define RCC_PLLMul_32                    ((uint8_t)0x1C)
#define RCC_PLLMul_48                    ((uint8_t)0x20)
 
 
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \
                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \
                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \
                             ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \
                             ((MUL) == RCC_PLLMul_48))
/**
  * @}
  */
 
/** @defgroup PLL_Divider_Factor
  * @{
  */
 
#define RCC_PLLDiv_2                     ((uint8_t)0x40)
#define RCC_PLLDiv_3                     ((uint8_t)0x80)
#define RCC_PLLDiv_4                     ((uint8_t)0xC0)
 
 
#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \
                             ((DIV) == RCC_PLLDiv_4))
/**
  * @}
  */
 
/** @defgroup System_Clock_Source
  * @{
  */
 
#define RCC_SYSCLKSource_MSI             RCC_CFGR_SW_MSI
#define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI
#define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE
#define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSI) || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
/**
  * @}
  */
 
/** @defgroup AHB_Clock_Source
  * @{
  */
 
#define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1
#define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2
#define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4
#define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8
#define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16
#define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64
#define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128
#define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256
#define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
                           ((HCLK) == RCC_SYSCLK_Div512))
/**
  * @}
  */
 
/** @defgroup APB1_APB2_Clock_Source
  * @{
  */
 
#define RCC_HCLK_Div1                    RCC_CFGR_PPRE1_DIV1
#define RCC_HCLK_Div2                    RCC_CFGR_PPRE1_DIV2
#define RCC_HCLK_Div4                    RCC_CFGR_PPRE1_DIV4
#define RCC_HCLK_Div8                    RCC_CFGR_PPRE1_DIV8
#define RCC_HCLK_Div16                   RCC_CFGR_PPRE1_DIV16
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
                           ((PCLK) == RCC_HCLK_Div16))
/**
  * @}
  */
 
 
/** @defgroup RCC_Interrupt_Source
  * @{
  */
 
#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
#define RCC_IT_LSERDY                    ((uint8_t)0x02)
#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
#define RCC_IT_HSERDY                    ((uint8_t)0x08)
#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
#define RCC_IT_MSIRDY                    ((uint8_t)0x20)
#define RCC_IT_CSS                       ((uint8_t)0x80)
 
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
 
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
                           ((IT) == RCC_IT_CSS))
 
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
 
/**
  * @}
  */
 
/** @defgroup LSE_Configuration
  * @{
  */
 
#define RCC_LSE_OFF                      ((uint8_t)0x00)
#define RCC_LSE_ON                       ((uint8_t)0x01)
#define RCC_LSE_Bypass                   ((uint8_t)0x05)
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_Bypass))
/**
  * @}
  */
 
/** @defgroup RTC_Clock_Source
  * @{
  */
 
#define RCC_RTCCLKSource_LSE             RCC_CSR_RTCSEL_LSE
#define RCC_RTCCLKSource_LSI             RCC_CSR_RTCSEL_LSI
#define RCC_RTCCLKSource_HSE_Div2        RCC_CSR_RTCSEL_HSE
#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))
/**
  * @}
  */
 
/** @defgroup AHB_Peripherals
  * @{
  */
 
#define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN
#define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN
#define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN
#define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN
#define RCC_AHBPeriph_GPIOE               RCC_AHBENR_GPIOEEN
#define RCC_AHBPeriph_GPIOH               RCC_AHBENR_GPIOHEN
#define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
#define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN
#define RCC_AHBPeriph_SRAM                RCC_AHBLPENR_SRAMLPEN
#define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN
 
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))
 
/**
  * @}
  */
 
/** @defgroup APB2_Peripherals
  * @{
  */
 
#define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN
#define RCC_APB2Periph_TIM9              RCC_APB2ENR_TIM9EN
#define RCC_APB2Periph_TIM10             RCC_APB2ENR_TIM10EN
#define RCC_APB2Periph_TIM11             RCC_APB2ENR_TIM11EN
#define RCC_APB2Periph_ADC1              RCC_APB2ENR_ADC1EN
#define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN
#define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN
 
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))
/**
  * @}
  */
 
/** @defgroup APB1_Peripherals
  * @{
  */
 
#define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN
#define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN
#define RCC_APB1Periph_TIM4              RCC_APB1ENR_TIM4EN
#define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN
#define RCC_APB1Periph_TIM7              RCC_APB1ENR_TIM7EN
#define RCC_APB1Periph_LCD               RCC_APB1ENR_LCDEN
#define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN
#define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN
#define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN
#define RCC_APB1Periph_USART3            RCC_APB1ENR_USART3EN
#define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN
#define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN
#define RCC_APB1Periph_USB               RCC_APB1ENR_USBEN
#define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN
#define RCC_APB1Periph_DAC               RCC_APB1ENR_DACEN
#define RCC_APB1Periph_COMP              RCC_APB1ENR_COMPEN
 
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))
/**
  * @}
  */
 
/** @defgroup MCO_Clock_Source
  * @{
  */
 
#define RCC_MCOSource_NoClock            ((uint8_t)0x00)
#define RCC_MCOSource_SYSCLK             ((uint8_t)0x01)
#define RCC_MCOSource_HSI                ((uint8_t)0x02)
#define RCC_MCOSource_MSI                ((uint8_t)0x03)
#define RCC_MCOSource_HSE                ((uint8_t)0x04)
#define RCC_MCOSource_PLLCLK             ((uint8_t)0x05)
#define RCC_MCOSource_LSI                ((uint8_t)0x06)
#define RCC_MCOSource_LSE                ((uint8_t)0x07)
 
#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \
                                   ((SOURCE) == RCC_MCOSource_HSI)  || ((SOURCE) == RCC_MCOSource_MSI) || \
                                   ((SOURCE) == RCC_MCOSource_HSE)  || ((SOURCE) == RCC_MCOSource_PLLCLK) || \
                                   ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))
/**
  * @}
  */
 
/** @defgroup MCO_Output_Divider
  * @{
  */
 
#define RCC_MCODiv_1                     ((uint8_t)0x00)
#define RCC_MCODiv_2                     ((uint8_t)0x10)
#define RCC_MCODiv_4                     ((uint8_t)0x20)
#define RCC_MCODiv_8                     ((uint8_t)0x30)
#define RCC_MCODiv_16                    ((uint8_t)0x40)
 
#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \
                             ((DIV) == RCC_MCODiv_4)  || ((DIV) == RCC_MCODiv_8) || \
                             ((DIV) == RCC_MCODiv_16))
/**
  * @}
  */
 
/** @defgroup RCC_Flag
  * @{
  */
 
#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
#define RCC_FLAG_MSIRDY                  ((uint8_t)0x29)
#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
#define RCC_FLAG_LSERDY                  ((uint8_t)0x49)
#define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
#define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
#define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
#define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
#define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
#define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
#define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
#define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
 
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
                           ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \
                           ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \
                           ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
                           ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
                           ((FLAG) == RCC_FLAG_WWDGRST))
 
#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
 
/**
  * @}
  */
 
/**
  * @}
  */
 
/** @defgroup RCC_Exported_Macros
  * @{
  */
 
/**
  * @}
  */
 
/** @defgroup RCC_Exported_Functions
  * @{
  */
 
void RCC_DeInit(void);
void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);
void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);
void RCC_MSICmd(FunctionalState NewState);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_RTCResetCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
 
#ifdef __cplusplus
}
#endif
 
#endif /* __STM32L1xx_RCC_H */
/**
  * @}
  */
 
/**
  * @}
  */
 
/**
  * @}
  */
 
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_STM32L152_IAR/] [system_and_ST_code/] [STM32L1xx_StdPeriph_Driver/] [inc/] [stm32l1xx_rcc.h] - Blame information for rev 582

Line No.	Rev	Author	Line
1	582	jeremybenn	`/**`
2			`******************************************************************************`
3			`* @file stm32l1xx_rcc.h`
4			`* @author MCD Application Team`
5			`* @version V1.0.0RC1`
6			`* @date 07/02/2010`
7			`* @brief This file contains all the functions prototypes for the RCC`
8			`* firmware library.`
9			`******************************************************************************`
10			`* @copy`
11			`*`
12			`* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS`
13			`* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE`
14			`* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY`
15			`* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING`
16			`* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE`
17			`* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.`
18			`*`
19			`* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>`
20			`*/`
21
22			`/* Define to prevent recursive inclusion -------------------------------------*/`
23			`#ifndef __STM32L1xx_RCC_H`
24			`#define __STM32L1xx_RCC_H`
25
26			`#ifdef __cplusplus`
27			`extern "C" {`
28			`#endif`
29
30			`/* Includes ------------------------------------------------------------------*/`
31			`#include "stm32l1xx.h"`
32
33			`/** @addtogroup STM32L1xx_StdPeriph_Driver`
34			`* @{`
35			`*/`
36
37			`/** @addtogroup RCC`
38			`* @{`
39			`*/`
40
41			`/** @defgroup RCC_Exported_Types`
42			`* @{`
43			`*/`
44
45			`typedef struct`
46			`{`
47			`uint32_t SYSCLK_Frequency;`
48			`uint32_t HCLK_Frequency;`
49			`uint32_t PCLK1_Frequency;`
50			`uint32_t PCLK2_Frequency;`
51			`}RCC_ClocksTypeDef;`
52
53			`/**`
54			`* @}`
55			`*/`
56
57			`/** @defgroup RCC_Exported_Constants`
58			`* @{`
59			`*/`
60
61			`/** @defgroup HSE_configuration`
62			`* @{`
63			`*/`
64
65			`#define RCC_HSE_OFF ((uint8_t)0x00)`
66			`#define RCC_HSE_ON ((uint8_t)0x01)`
67			`#define RCC_HSE_Bypass ((uint8_t)0x05)`
68			`#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \`
69			`((HSE) == RCC_HSE_Bypass))`
70
71			`/**`
72			`* @}`
73			`*/`
74
75			`/** @defgroup MSI_Clock_Range`
76			`* @{`
77			`*/`
78
79			`#define RCC_MSIRange_64KHz RCC_ICSCR_MSIRANGE_64KHz`
80			`#define RCC_MSIRange_128KHz RCC_ICSCR_MSIRANGE_128KHz`
81			`#define RCC_MSIRange_256KHz RCC_ICSCR_MSIRANGE_256KHz`
82			`#define RCC_MSIRange_512KHz RCC_ICSCR_MSIRANGE_512KHz`
83			`#define RCC_MSIRange_1MHz RCC_ICSCR_MSIRANGE_1MHz`
84			`#define RCC_MSIRange_2MHz RCC_ICSCR_MSIRANGE_2MHz`
85			`#define RCC_MSIRange_4MHz RCC_ICSCR_MSIRANGE_4MHz`
86
87			`#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_64KHz) \|\| \`
88			`((RANGE) == RCC_MSIRange_128KHz) \|\| \`
89			`((RANGE) == RCC_MSIRange_256KHz) \|\| \`
90			`((RANGE) == RCC_MSIRange_512KHz) \|\| \`
91			`((RANGE) == RCC_MSIRange_1MHz) \|\| \`
92			`((RANGE) == RCC_MSIRange_2MHz) \|\| \`
93			`((RANGE) == RCC_MSIRange_4MHz))`
94
95			`/**`
96			`* @}`
97			`*/`
98
99			`/** @defgroup PLL_Clock_Source`
100			`* @{`
101			`*/`
102
103			`#define RCC_PLLSource_HSI ((uint8_t)0x00)`
104			`#define RCC_PLLSource_HSE ((uint8_t)0x01)`
105
106			`#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) \|\| \`
107			`((SOURCE) == RCC_PLLSource_HSE))`
108			`/**`
109			`* @}`
110			`*/`
111
112			`/** @defgroup PLL_Multiplication_Factor`
113			`* @{`
114			`*/`
115
116			`#define RCC_PLLMul_3 ((uint8_t)0x00)`
117			`#define RCC_PLLMul_4 ((uint8_t)0x04)`
118			`#define RCC_PLLMul_6 ((uint8_t)0x08)`
119			`#define RCC_PLLMul_8 ((uint8_t)0x0C)`
120			`#define RCC_PLLMul_12 ((uint8_t)0x10)`
121			`#define RCC_PLLMul_16 ((uint8_t)0x14)`
122			`#define RCC_PLLMul_24 ((uint8_t)0x18)`
123			`#define RCC_PLLMul_32 ((uint8_t)0x1C)`
124			`#define RCC_PLLMul_48 ((uint8_t)0x20)`
125
126
127			`#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) \|\| ((MUL) == RCC_PLLMul_4) \|\| \`
128			`((MUL) == RCC_PLLMul_6) \|\| ((MUL) == RCC_PLLMul_8) \|\| \`
129			`((MUL) == RCC_PLLMul_12) \|\| ((MUL) == RCC_PLLMul_16) \|\| \`
130			`((MUL) == RCC_PLLMul_24) \|\| ((MUL) == RCC_PLLMul_32) \|\| \`
131			`((MUL) == RCC_PLLMul_48))`
132			`/**`
133			`* @}`
134			`*/`
135
136			`/** @defgroup PLL_Divider_Factor`
137			`* @{`
138			`*/`
139
140			`#define RCC_PLLDiv_2 ((uint8_t)0x40)`
141			`#define RCC_PLLDiv_3 ((uint8_t)0x80)`
142			`#define RCC_PLLDiv_4 ((uint8_t)0xC0)`
143
144
145			`#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) \|\| ((DIV) == RCC_PLLDiv_3) \|\| \`
146			`((DIV) == RCC_PLLDiv_4))`
147			`/**`
148			`* @}`
149			`*/`
150
151			`/** @defgroup System_Clock_Source`
152			`* @{`
153			`*/`
154
155			`#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI`
156			`#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI`
157			`#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE`
158			`#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL`
159			`#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) \|\| \`
160			`((SOURCE) == RCC_SYSCLKSource_HSI) \|\| \`
161			`((SOURCE) == RCC_SYSCLKSource_HSE) \|\| \`
162			`((SOURCE) == RCC_SYSCLKSource_PLLCLK))`
163			`/**`
164			`* @}`
165			`*/`
166
167			`/** @defgroup AHB_Clock_Source`
168			`* @{`
169			`*/`
170
171			`#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1`
172			`#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2`
173			`#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4`
174			`#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8`
175			`#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16`
176			`#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64`
177			`#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128`
178			`#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256`
179			`#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512`
180			`#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) \|\| ((HCLK) == RCC_SYSCLK_Div2) \|\| \`
181			`((HCLK) == RCC_SYSCLK_Div4) \|\| ((HCLK) == RCC_SYSCLK_Div8) \|\| \`
182			`((HCLK) == RCC_SYSCLK_Div16) \|\| ((HCLK) == RCC_SYSCLK_Div64) \|\| \`
183			`((HCLK) == RCC_SYSCLK_Div128) \|\| ((HCLK) == RCC_SYSCLK_Div256) \|\| \`
184			`((HCLK) == RCC_SYSCLK_Div512))`
185			`/**`
186			`* @}`
187			`*/`
188
189			`/** @defgroup APB1_APB2_Clock_Source`
190			`* @{`
191			`*/`
192
193			`#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1`
194			`#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2`
195			`#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4`
196			`#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8`
197			`#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16`
198			`#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) \|\| ((PCLK) == RCC_HCLK_Div2) \|\| \`
199			`((PCLK) == RCC_HCLK_Div4) \|\| ((PCLK) == RCC_HCLK_Div8) \|\| \`
200			`((PCLK) == RCC_HCLK_Div16))`
201			`/**`
202			`* @}`
203			`*/`
204
205
206			`/** @defgroup RCC_Interrupt_Source`
207			`* @{`
208			`*/`
209
210			`#define RCC_IT_LSIRDY ((uint8_t)0x01)`
211			`#define RCC_IT_LSERDY ((uint8_t)0x02)`
212			`#define RCC_IT_HSIRDY ((uint8_t)0x04)`
213			`#define RCC_IT_HSERDY ((uint8_t)0x08)`
214			`#define RCC_IT_PLLRDY ((uint8_t)0x10)`
215			`#define RCC_IT_MSIRDY ((uint8_t)0x20)`
216			`#define RCC_IT_CSS ((uint8_t)0x80)`
217
218			`#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))`
219
220			`#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) \|\| ((IT) == RCC_IT_LSERDY) \|\| \`
221			`((IT) == RCC_IT_HSIRDY) \|\| ((IT) == RCC_IT_HSERDY) \|\| \`
222			`((IT) == RCC_IT_PLLRDY) \|\| ((IT) == RCC_IT_MSIRDY) \|\| \`
223			`((IT) == RCC_IT_CSS))`
224
225			`#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))`
226
227			`/**`
228			`* @}`
229			`*/`
230
231			`/** @defgroup LSE_Configuration`
232			`* @{`
233			`*/`
234
235			`#define RCC_LSE_OFF ((uint8_t)0x00)`
236			`#define RCC_LSE_ON ((uint8_t)0x01)`
237			`#define RCC_LSE_Bypass ((uint8_t)0x05)`
238			`#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \`
239			`((LSE) == RCC_LSE_Bypass))`
240			`/**`
241			`* @}`
242			`*/`
243
244			`/** @defgroup RTC_Clock_Source`
245			`* @{`
246			`*/`
247
248			`#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE`
249			`#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI`
250			`#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE`
251			`#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)`
252			`#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)`
253			`#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)`
254			`#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) \|\| \`
255			`((SOURCE) == RCC_RTCCLKSource_LSI) \|\| \`
256			`((SOURCE) == RCC_RTCCLKSource_HSE_Div2) \|\| \`
257			`((SOURCE) == RCC_RTCCLKSource_HSE_Div4) \|\| \`
258			`((SOURCE) == RCC_RTCCLKSource_HSE_Div8) \|\| \`
259			`((SOURCE) == RCC_RTCCLKSource_HSE_Div16))`
260			`/**`
261			`* @}`
262			`*/`
263
264			`/** @defgroup AHB_Peripherals`
265			`* @{`
266			`*/`
267
268			`#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN`
269			`#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN`
270			`#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN`
271			`#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN`
272			`#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN`
273			`#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN`
274			`#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN`
275			`#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN`
276			`#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN`
277			`#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN`
278
279			`#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))`
280			`#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))`
281
282			`/**`
283			`* @}`
284			`*/`
285
286			`/** @defgroup APB2_Peripherals`
287			`* @{`
288			`*/`
289
290			`#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN`
291			`#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN`
292			`#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN`
293			`#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN`
294			`#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN`
295			`#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN`
296			`#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN`
297
298			`#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))`
299			`/**`
300			`* @}`
301			`*/`
302
303			`/** @defgroup APB1_Peripherals`
304			`* @{`
305			`*/`
306
307			`#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN`
308			`#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN`
309			`#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN`
310			`#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN`
311			`#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN`
312			`#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN`
313			`#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN`
314			`#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN`
315			`#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN`
316			`#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN`
317			`#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN`
318			`#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN`
319			`#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN`
320			`#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN`
321			`#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN`
322			`#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN`
323
324			`#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))`
325			`/**`
326			`* @}`
327			`*/`
328
329			`/** @defgroup MCO_Clock_Source`
330			`* @{`
331			`*/`
332
333			`#define RCC_MCOSource_NoClock ((uint8_t)0x00)`
334			`#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)`
335			`#define RCC_MCOSource_HSI ((uint8_t)0x02)`
336			`#define RCC_MCOSource_MSI ((uint8_t)0x03)`
337			`#define RCC_MCOSource_HSE ((uint8_t)0x04)`
338			`#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)`
339			`#define RCC_MCOSource_LSI ((uint8_t)0x06)`
340			`#define RCC_MCOSource_LSE ((uint8_t)0x07)`
341
342			`#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) \|\| ((SOURCE) == RCC_MCOSource_SYSCLK) \|\| \`
343			`((SOURCE) == RCC_MCOSource_HSI) \|\| ((SOURCE) == RCC_MCOSource_MSI) \|\| \`
344			`((SOURCE) == RCC_MCOSource_HSE) \|\| ((SOURCE) == RCC_MCOSource_PLLCLK) \|\| \`
345			`((SOURCE) == RCC_MCOSource_LSI) \|\| ((SOURCE) == RCC_MCOSource_LSE))`
346			`/**`
347			`* @}`
348			`*/`
349
350			`/** @defgroup MCO_Output_Divider`
351			`* @{`
352			`*/`
353
354			`#define RCC_MCODiv_1 ((uint8_t)0x00)`
355			`#define RCC_MCODiv_2 ((uint8_t)0x10)`
356			`#define RCC_MCODiv_4 ((uint8_t)0x20)`
357			`#define RCC_MCODiv_8 ((uint8_t)0x30)`
358			`#define RCC_MCODiv_16 ((uint8_t)0x40)`
359
360			`#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) \|\| ((DIV) == RCC_MCODiv_2) \|\| \`
361			`((DIV) == RCC_MCODiv_4) \|\| ((DIV) == RCC_MCODiv_8) \|\| \`
362			`((DIV) == RCC_MCODiv_16))`
363			`/**`
364			`* @}`
365			`*/`
366
367			`/** @defgroup RCC_Flag`
368			`* @{`
369			`*/`
370
371			`#define RCC_FLAG_HSIRDY ((uint8_t)0x21)`
372			`#define RCC_FLAG_MSIRDY ((uint8_t)0x29)`
373			`#define RCC_FLAG_HSERDY ((uint8_t)0x31)`
374			`#define RCC_FLAG_PLLRDY ((uint8_t)0x39)`
375			`#define RCC_FLAG_LSERDY ((uint8_t)0x49)`
376			`#define RCC_FLAG_LSIRDY ((uint8_t)0x41)`
377			`#define RCC_FLAG_OBLRST ((uint8_t)0x59)`
378			`#define RCC_FLAG_PINRST ((uint8_t)0x5A)`
379			`#define RCC_FLAG_PORRST ((uint8_t)0x5B)`
380			`#define RCC_FLAG_SFTRST ((uint8_t)0x5C)`
381			`#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)`
382			`#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)`
383			`#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)`
384
385			`#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) \|\| ((FLAG) == RCC_FLAG_HSERDY) \|\| \`
386			`((FLAG) == RCC_FLAG_MSIRDY) \|\| ((FLAG) == RCC_FLAG_PLLRDY) \|\| \`
387			`((FLAG) == RCC_FLAG_LSERDY) \|\| ((FLAG) == RCC_FLAG_LSIRDY) \|\| \`
388			`((FLAG) == RCC_FLAG_PINRST) \|\| ((FLAG) == RCC_FLAG_PORRST) \|\| \`
389			`((FLAG) == RCC_FLAG_SFTRST) \|\| ((FLAG) == RCC_FLAG_IWDGRST)\|\| \`
390			`((FLAG) == RCC_FLAG_WWDGRST)\|\| ((FLAG) == RCC_FLAG_LPWRRST)\|\| \`
391			`((FLAG) == RCC_FLAG_WWDGRST))`
392
393			`#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)`
394			`#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)`
395
396			`/**`
397			`* @}`
398			`*/`
399
400			`/**`
401			`* @}`
402			`*/`
403
404			`/** @defgroup RCC_Exported_Macros`
405			`* @{`
406			`*/`
407
408			`/**`
409			`* @}`
410			`*/`
411
412			`/** @defgroup RCC_Exported_Functions`
413			`* @{`
414			`*/`
415
416			`void RCC_DeInit(void);`
417			`void RCC_HSEConfig(uint8_t RCC_HSE);`
418			`ErrorStatus RCC_WaitForHSEStartUp(void);`
419			`void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);`
420			`void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);`
421			`void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);`
422			`void RCC_MSICmd(FunctionalState NewState);`
423			`void RCC_HSICmd(FunctionalState NewState);`
424			`void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);`
425			`void RCC_PLLCmd(FunctionalState NewState);`
426			`void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);`
427			`uint8_t RCC_GetSYSCLKSource(void);`
428			`void RCC_HCLKConfig(uint32_t RCC_SYSCLK);`
429			`void RCC_PCLK1Config(uint32_t RCC_HCLK);`
430			`void RCC_PCLK2Config(uint32_t RCC_HCLK);`
431			`void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);`
432			`void RCC_LSEConfig(uint8_t RCC_LSE);`
433			`void RCC_LSICmd(FunctionalState NewState);`
434			`void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);`
435			`void RCC_RTCCLKCmd(FunctionalState NewState);`
436			`void RCC_RTCResetCmd(FunctionalState NewState);`
437			`void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);`
438			`void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);`
439			`void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);`
440			`void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);`
441			`void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);`
442			`void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);`
443			`void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);`
444			`void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);`
445			`void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);`
446			`void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);`
447			`void RCC_ClockSecuritySystemCmd(FunctionalState NewState);`
448			`void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);`
449			`FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);`
450			`void RCC_ClearFlag(void);`
451			`ITStatus RCC_GetITStatus(uint8_t RCC_IT);`
452			`void RCC_ClearITPendingBit(uint8_t RCC_IT);`
453
454			`#ifdef __cplusplus`
455			`}`
456			`#endif`
457
458			`#endif /* __STM32L1xx_RCC_H */`
459			`/**`
460			`* @}`
461			`*/`
462
463			`/**`
464			`* @}`
465			`*/`
466
467			`/**`
468			`* @}`
469			`*/`
470
471			`/***************** (C) COPYRIGHT 2010 STMicroelectronics *END OF FILE**/`