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jeremybenn |
/**
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******************************************************************************
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* @file stm32l1xx_tim.h
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* @author MCD Application Team
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* @version V1.0.0RC1
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* @date 07/02/2010
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* @brief This file contains all the functions prototypes for the TIM firmware
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* library.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32L1xx_TIM_H
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#define __STM32L1xx_TIM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx.h"
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/** @addtogroup STM32L1xx_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup TIM
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* @{
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*/
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/** @defgroup TIM_Exported_Types
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* @{
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*/
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/**
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* @brief TIM Time Base Init structure definition
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* @note This sturcture is used with all TIMx except for TIM6 and TIM7.
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*/
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typedef struct
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{
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uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
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This parameter can be a value of @ref TIM_Counter_Mode */
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uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
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Auto-Reload Register at the next update event.
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This parameter must be a number between 0x0000 and 0xFFFF. */
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uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
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This parameter can be a value of @ref TIM_Clock_Division_CKD */
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} TIM_TimeBaseInitTypeDef;
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/**
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* @brief TIM Output Compare Init structure definition
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*/
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typedef struct
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{
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uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
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This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
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This parameter can be a value of @ref TIM_Output_Compare_state */
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uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
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This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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} TIM_OCInitTypeDef;
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/**
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* @brief TIM Input Capture Init structure definition
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*/
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typedef struct
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{
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uint16_t TIM_Channel; /*!< Specifies the TIM channel.
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This parameter can be a value of @ref TIM_Channel */
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uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
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This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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uint16_t TIM_ICSelection; /*!< Specifies the input.
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This parameter can be a value of @ref TIM_Input_Capture_Selection */
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uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
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This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
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This parameter can be a number between 0x0 and 0xF */
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} TIM_ICInitTypeDef;
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/**
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* @}
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*/
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/** @defgroup TIM_Exported_constants
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* @{
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*/
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#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM6) || \
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((PERIPH) == TIM7) || \
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((PERIPH) == TIM9) || \
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((PERIPH) == TIM10) || \
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((PERIPH) == TIM11))
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#define IS_TIM_23491011_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM9) || \
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((PERIPH) == TIM10) || \
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((PERIPH) == TIM11))
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#define IS_TIM_234_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4))
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#define IS_TIM_2349_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) ||\
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((PERIPH) == TIM9))
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#define IS_TIM_234679_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) ||\
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((PERIPH) == TIM6) || \
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((PERIPH) == TIM7) ||\
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((PERIPH) == TIM9))
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#define IS_TIM_23467_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) ||\
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((PERIPH) == TIM6) || \
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((PERIPH) == TIM7))
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#define IS_TIM_91011_PERIPH(PERIPH) (((PERIPH) == TIM9) || \
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((PERIPH) == TIM10) ||\
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((PERIPH) == TIM11))
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/** @defgroup TIM_Output_Compare_and_PWM_modes
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* @{
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*/
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#define TIM_OCMode_Timing ((uint16_t)0x0000)
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#define TIM_OCMode_Active ((uint16_t)0x0010)
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#define TIM_OCMode_Inactive ((uint16_t)0x0020)
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#define TIM_OCMode_Toggle ((uint16_t)0x0030)
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#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
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#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
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#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
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((MODE) == TIM_OCMode_Active) || \
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((MODE) == TIM_OCMode_Inactive) || \
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((MODE) == TIM_OCMode_Toggle)|| \
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((MODE) == TIM_OCMode_PWM1) || \
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((MODE) == TIM_OCMode_PWM2))
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#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
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((MODE) == TIM_OCMode_Active) || \
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((MODE) == TIM_OCMode_Inactive) || \
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((MODE) == TIM_OCMode_Toggle)|| \
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((MODE) == TIM_OCMode_PWM1) || \
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((MODE) == TIM_OCMode_PWM2) || \
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((MODE) == TIM_ForcedAction_Active) || \
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((MODE) == TIM_ForcedAction_InActive))
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/**
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* @}
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*/
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/** @defgroup TIM_One_Pulse_Mode
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* @{
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*/
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#define TIM_OPMode_Single ((uint16_t)0x0008)
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#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
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#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
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((MODE) == TIM_OPMode_Repetitive))
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/**
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* @}
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*/
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/** @defgroup TIM_Channel
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* @{
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*/
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#define TIM_Channel_1 ((uint16_t)0x0000)
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#define TIM_Channel_2 ((uint16_t)0x0004)
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#define TIM_Channel_3 ((uint16_t)0x0008)
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#define TIM_Channel_4 ((uint16_t)0x000C)
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#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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((CHANNEL) == TIM_Channel_2) || \
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((CHANNEL) == TIM_Channel_3) || \
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((CHANNEL) == TIM_Channel_4))
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#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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((CHANNEL) == TIM_Channel_2))
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/**
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* @}
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*/
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/** @defgroup TIM_Clock_Division_CKD
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* @{
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*/
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#define TIM_CKD_DIV1 ((uint16_t)0x0000)
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#define TIM_CKD_DIV2 ((uint16_t)0x0100)
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#define TIM_CKD_DIV4 ((uint16_t)0x0200)
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#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
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((DIV) == TIM_CKD_DIV2) || \
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((DIV) == TIM_CKD_DIV4))
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/**
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* @}
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*/
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/** @defgroup TIM_Counter_Mode
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* @{
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*/
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#define TIM_CounterMode_Up ((uint16_t)0x0000)
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#define TIM_CounterMode_Down ((uint16_t)0x0010)
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#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
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#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
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#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
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#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
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((MODE) == TIM_CounterMode_Down) || \
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((MODE) == TIM_CounterMode_CenterAligned1) || \
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((MODE) == TIM_CounterMode_CenterAligned2) || \
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((MODE) == TIM_CounterMode_CenterAligned3))
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/**
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* @}
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*/
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/** @defgroup TIM_Output_Compare_Polarity
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* @{
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*/
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#define TIM_OCPolarity_High ((uint16_t)0x0000)
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#define TIM_OCPolarity_Low ((uint16_t)0x0002)
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#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
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((POLARITY) == TIM_OCPolarity_Low))
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/**
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* @}
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*/
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/** @defgroup TIM_Output_Compare_state
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* @{
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*/
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#define TIM_OutputState_Disable ((uint16_t)0x0000)
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#define TIM_OutputState_Enable ((uint16_t)0x0001)
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#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
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((STATE) == TIM_OutputState_Enable))
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/**
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* @}
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*/
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/** @defgroup TIM_Capture_Compare_state
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* @{
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*/
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#define TIM_CCx_Enable ((uint16_t)0x0001)
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#define TIM_CCx_Disable ((uint16_t)0x0000)
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#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
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((CCX) == TIM_CCx_Disable))
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/**
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* @}
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*/
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/** @defgroup TIM_Input_Capture_Polarity
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* @{
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*/
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#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
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#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
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#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
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#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
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((POLARITY) == TIM_ICPolarity_Falling)|| \
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((POLARITY) == TIM_ICPolarity_BothEdge))
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/**
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* @}
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*/
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/** @defgroup TIM_Input_Capture_Selection
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* @{
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*/
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#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
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connected to IC1, IC2, IC3 or IC4, respectively */
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#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
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connected to IC2, IC1, IC4 or IC3, respectively. */
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#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
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#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
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((SELECTION) == TIM_ICSelection_IndirectTI) || \
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((SELECTION) == TIM_ICSelection_TRC))
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/**
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* @}
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*/
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/** @defgroup TIM_Input_Capture_Prescaler
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* @{
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*/
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#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
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#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
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#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
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#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
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#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
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((PRESCALER) == TIM_ICPSC_DIV2) || \
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((PRESCALER) == TIM_ICPSC_DIV4) || \
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((PRESCALER) == TIM_ICPSC_DIV8))
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/**
|
338 |
|
|
* @}
|
339 |
|
|
*/
|
340 |
|
|
|
341 |
|
|
/** @defgroup TIM_interrupt_sources
|
342 |
|
|
* @{
|
343 |
|
|
*/
|
344 |
|
|
|
345 |
|
|
#define TIM_IT_Update ((uint16_t)0x0001)
|
346 |
|
|
#define TIM_IT_CC1 ((uint16_t)0x0002)
|
347 |
|
|
#define TIM_IT_CC2 ((uint16_t)0x0004)
|
348 |
|
|
#define TIM_IT_CC3 ((uint16_t)0x0008)
|
349 |
|
|
#define TIM_IT_CC4 ((uint16_t)0x0010)
|
350 |
|
|
#define TIM_IT_Trigger ((uint16_t)0x0040)
|
351 |
|
|
#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))
|
352 |
|
|
|
353 |
|
|
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
|
354 |
|
|
((IT) == TIM_IT_CC1) || \
|
355 |
|
|
((IT) == TIM_IT_CC2) || \
|
356 |
|
|
((IT) == TIM_IT_CC3) || \
|
357 |
|
|
((IT) == TIM_IT_CC4) || \
|
358 |
|
|
((IT) == TIM_IT_Trigger))
|
359 |
|
|
/**
|
360 |
|
|
* @}
|
361 |
|
|
*/
|
362 |
|
|
|
363 |
|
|
/** @defgroup TIM_DMA_Base_address
|
364 |
|
|
* @{
|
365 |
|
|
*/
|
366 |
|
|
|
367 |
|
|
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
|
368 |
|
|
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
|
369 |
|
|
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
|
370 |
|
|
#define TIM_DMABase_DIER ((uint16_t)0x0003)
|
371 |
|
|
#define TIM_DMABase_SR ((uint16_t)0x0004)
|
372 |
|
|
#define TIM_DMABase_EGR ((uint16_t)0x0005)
|
373 |
|
|
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
|
374 |
|
|
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
|
375 |
|
|
#define TIM_DMABase_CCER ((uint16_t)0x0008)
|
376 |
|
|
#define TIM_DMABase_CNT ((uint16_t)0x0009)
|
377 |
|
|
#define TIM_DMABase_PSC ((uint16_t)0x000A)
|
378 |
|
|
#define TIM_DMABase_ARR ((uint16_t)0x000B)
|
379 |
|
|
#define TIM_DMABase_RCR ((uint16_t)0x000C)
|
380 |
|
|
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
|
381 |
|
|
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
|
382 |
|
|
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
|
383 |
|
|
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
|
384 |
|
|
#define TIM_DMABase_DCR ((uint16_t)0x0012)
|
385 |
|
|
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
|
386 |
|
|
((BASE) == TIM_DMABase_CR2) || \
|
387 |
|
|
((BASE) == TIM_DMABase_SMCR) || \
|
388 |
|
|
((BASE) == TIM_DMABase_DIER) || \
|
389 |
|
|
((BASE) == TIM_DMABase_SR) || \
|
390 |
|
|
((BASE) == TIM_DMABase_EGR) || \
|
391 |
|
|
((BASE) == TIM_DMABase_CCMR1) || \
|
392 |
|
|
((BASE) == TIM_DMABase_CCMR2) || \
|
393 |
|
|
((BASE) == TIM_DMABase_CCER) || \
|
394 |
|
|
((BASE) == TIM_DMABase_CNT) || \
|
395 |
|
|
((BASE) == TIM_DMABase_PSC) || \
|
396 |
|
|
((BASE) == TIM_DMABase_ARR) || \
|
397 |
|
|
((BASE) == TIM_DMABase_CCR1) || \
|
398 |
|
|
((BASE) == TIM_DMABase_CCR2) || \
|
399 |
|
|
((BASE) == TIM_DMABase_CCR3) || \
|
400 |
|
|
((BASE) == TIM_DMABase_CCR4) || \
|
401 |
|
|
((BASE) == TIM_DMABase_DCR))
|
402 |
|
|
/**
|
403 |
|
|
* @}
|
404 |
|
|
*/
|
405 |
|
|
|
406 |
|
|
/** @defgroup TIM_DMA_Burst_Length
|
407 |
|
|
* @{
|
408 |
|
|
*/
|
409 |
|
|
|
410 |
|
|
#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)
|
411 |
|
|
#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)
|
412 |
|
|
#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)
|
413 |
|
|
#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)
|
414 |
|
|
#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)
|
415 |
|
|
#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)
|
416 |
|
|
#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)
|
417 |
|
|
#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)
|
418 |
|
|
#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)
|
419 |
|
|
#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)
|
420 |
|
|
#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)
|
421 |
|
|
#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)
|
422 |
|
|
#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)
|
423 |
|
|
#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)
|
424 |
|
|
#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)
|
425 |
|
|
#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)
|
426 |
|
|
#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)
|
427 |
|
|
#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)
|
428 |
|
|
#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
|
429 |
|
|
((LENGTH) == TIM_DMABurstLength_2Bytes) || \
|
430 |
|
|
((LENGTH) == TIM_DMABurstLength_3Bytes) || \
|
431 |
|
|
((LENGTH) == TIM_DMABurstLength_4Bytes) || \
|
432 |
|
|
((LENGTH) == TIM_DMABurstLength_5Bytes) || \
|
433 |
|
|
((LENGTH) == TIM_DMABurstLength_6Bytes) || \
|
434 |
|
|
((LENGTH) == TIM_DMABurstLength_7Bytes) || \
|
435 |
|
|
((LENGTH) == TIM_DMABurstLength_8Bytes) || \
|
436 |
|
|
((LENGTH) == TIM_DMABurstLength_9Bytes) || \
|
437 |
|
|
((LENGTH) == TIM_DMABurstLength_10Bytes) || \
|
438 |
|
|
((LENGTH) == TIM_DMABurstLength_11Bytes) || \
|
439 |
|
|
((LENGTH) == TIM_DMABurstLength_12Bytes) || \
|
440 |
|
|
((LENGTH) == TIM_DMABurstLength_13Bytes) || \
|
441 |
|
|
((LENGTH) == TIM_DMABurstLength_14Bytes) || \
|
442 |
|
|
((LENGTH) == TIM_DMABurstLength_15Bytes) || \
|
443 |
|
|
((LENGTH) == TIM_DMABurstLength_16Bytes) || \
|
444 |
|
|
((LENGTH) == TIM_DMABurstLength_17Bytes) || \
|
445 |
|
|
((LENGTH) == TIM_DMABurstLength_18Bytes))
|
446 |
|
|
/**
|
447 |
|
|
* @}
|
448 |
|
|
*/
|
449 |
|
|
|
450 |
|
|
/** @defgroup TIM_DMA_sources
|
451 |
|
|
* @{
|
452 |
|
|
*/
|
453 |
|
|
|
454 |
|
|
#define TIM_DMA_Update ((uint16_t)0x0100)
|
455 |
|
|
#define TIM_DMA_CC1 ((uint16_t)0x0200)
|
456 |
|
|
#define TIM_DMA_CC2 ((uint16_t)0x0400)
|
457 |
|
|
#define TIM_DMA_CC3 ((uint16_t)0x0800)
|
458 |
|
|
#define TIM_DMA_CC4 ((uint16_t)0x1000)
|
459 |
|
|
#define TIM_DMA_Trigger ((uint16_t)0x4000)
|
460 |
|
|
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))
|
461 |
|
|
|
462 |
|
|
/**
|
463 |
|
|
* @}
|
464 |
|
|
*/
|
465 |
|
|
|
466 |
|
|
/** @defgroup TIM_External_Trigger_Prescaler
|
467 |
|
|
* @{
|
468 |
|
|
*/
|
469 |
|
|
|
470 |
|
|
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
|
471 |
|
|
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
|
472 |
|
|
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
473 |
|
|
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
474 |
|
|
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
|
475 |
|
|
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
|
476 |
|
|
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
|
477 |
|
|
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
|
478 |
|
|
/**
|
479 |
|
|
* @}
|
480 |
|
|
*/
|
481 |
|
|
|
482 |
|
|
/** @defgroup TIM_Internal_Trigger_Selection
|
483 |
|
|
* @{
|
484 |
|
|
*/
|
485 |
|
|
|
486 |
|
|
#define TIM_TS_ITR0 ((uint16_t)0x0000)
|
487 |
|
|
#define TIM_TS_ITR1 ((uint16_t)0x0010)
|
488 |
|
|
#define TIM_TS_ITR2 ((uint16_t)0x0020)
|
489 |
|
|
#define TIM_TS_ITR3 ((uint16_t)0x0030)
|
490 |
|
|
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
|
491 |
|
|
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
|
492 |
|
|
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
|
493 |
|
|
#define TIM_TS_ETRF ((uint16_t)0x0070)
|
494 |
|
|
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
495 |
|
|
((SELECTION) == TIM_TS_ITR1) || \
|
496 |
|
|
((SELECTION) == TIM_TS_ITR2) || \
|
497 |
|
|
((SELECTION) == TIM_TS_ITR3) || \
|
498 |
|
|
((SELECTION) == TIM_TS_TI1F_ED) || \
|
499 |
|
|
((SELECTION) == TIM_TS_TI1FP1) || \
|
500 |
|
|
((SELECTION) == TIM_TS_TI2FP2) || \
|
501 |
|
|
((SELECTION) == TIM_TS_ETRF))
|
502 |
|
|
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
503 |
|
|
((SELECTION) == TIM_TS_ITR1) || \
|
504 |
|
|
((SELECTION) == TIM_TS_ITR2) || \
|
505 |
|
|
((SELECTION) == TIM_TS_ITR3))
|
506 |
|
|
/**
|
507 |
|
|
* @}
|
508 |
|
|
*/
|
509 |
|
|
|
510 |
|
|
/** @defgroup TIM_TIx_External_Clock_Source
|
511 |
|
|
* @{
|
512 |
|
|
*/
|
513 |
|
|
|
514 |
|
|
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
|
515 |
|
|
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
|
516 |
|
|
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
|
517 |
|
|
|
518 |
|
|
/**
|
519 |
|
|
* @}
|
520 |
|
|
*/
|
521 |
|
|
|
522 |
|
|
/** @defgroup TIM_External_Trigger_Polarity
|
523 |
|
|
* @{
|
524 |
|
|
*/
|
525 |
|
|
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
526 |
|
|
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
527 |
|
|
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
|
528 |
|
|
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
|
529 |
|
|
/**
|
530 |
|
|
* @}
|
531 |
|
|
*/
|
532 |
|
|
|
533 |
|
|
/** @defgroup TIM_Prescaler_Reload_Mode
|
534 |
|
|
* @{
|
535 |
|
|
*/
|
536 |
|
|
|
537 |
|
|
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
|
538 |
|
|
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
|
539 |
|
|
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
|
540 |
|
|
((RELOAD) == TIM_PSCReloadMode_Immediate))
|
541 |
|
|
/**
|
542 |
|
|
* @}
|
543 |
|
|
*/
|
544 |
|
|
|
545 |
|
|
/** @defgroup TIM_Forced_Action
|
546 |
|
|
* @{
|
547 |
|
|
*/
|
548 |
|
|
|
549 |
|
|
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
|
550 |
|
|
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
|
551 |
|
|
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
|
552 |
|
|
((ACTION) == TIM_ForcedAction_InActive))
|
553 |
|
|
/**
|
554 |
|
|
* @}
|
555 |
|
|
*/
|
556 |
|
|
|
557 |
|
|
/** @defgroup TIM_Encoder_Mode
|
558 |
|
|
* @{
|
559 |
|
|
*/
|
560 |
|
|
|
561 |
|
|
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
|
562 |
|
|
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
|
563 |
|
|
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
|
564 |
|
|
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
|
565 |
|
|
((MODE) == TIM_EncoderMode_TI2) || \
|
566 |
|
|
((MODE) == TIM_EncoderMode_TI12))
|
567 |
|
|
/**
|
568 |
|
|
* @}
|
569 |
|
|
*/
|
570 |
|
|
|
571 |
|
|
|
572 |
|
|
/** @defgroup TIM_Event_Source
|
573 |
|
|
* @{
|
574 |
|
|
*/
|
575 |
|
|
|
576 |
|
|
#define TIM_EventSource_Update ((uint16_t)0x0001)
|
577 |
|
|
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
|
578 |
|
|
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
|
579 |
|
|
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
|
580 |
|
|
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
|
581 |
|
|
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
|
582 |
|
|
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))
|
583 |
|
|
|
584 |
|
|
/**
|
585 |
|
|
* @}
|
586 |
|
|
*/
|
587 |
|
|
|
588 |
|
|
/** @defgroup TIM_Update_Source
|
589 |
|
|
* @{
|
590 |
|
|
*/
|
591 |
|
|
|
592 |
|
|
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
|
593 |
|
|
or the setting of UG bit, or an update generation
|
594 |
|
|
through the slave mode controller. */
|
595 |
|
|
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
|
596 |
|
|
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
|
597 |
|
|
((SOURCE) == TIM_UpdateSource_Regular))
|
598 |
|
|
/**
|
599 |
|
|
* @}
|
600 |
|
|
*/
|
601 |
|
|
|
602 |
|
|
/** @defgroup TIM_Ouput_Compare_Preload_State
|
603 |
|
|
* @{
|
604 |
|
|
*/
|
605 |
|
|
|
606 |
|
|
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
|
607 |
|
|
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
|
608 |
|
|
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
|
609 |
|
|
((STATE) == TIM_OCPreload_Disable))
|
610 |
|
|
/**
|
611 |
|
|
* @}
|
612 |
|
|
*/
|
613 |
|
|
|
614 |
|
|
/** @defgroup TIM_Ouput_Compare_Fast_State
|
615 |
|
|
* @{
|
616 |
|
|
*/
|
617 |
|
|
|
618 |
|
|
#define TIM_OCFast_Enable ((uint16_t)0x0004)
|
619 |
|
|
#define TIM_OCFast_Disable ((uint16_t)0x0000)
|
620 |
|
|
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
|
621 |
|
|
((STATE) == TIM_OCFast_Disable))
|
622 |
|
|
|
623 |
|
|
/**
|
624 |
|
|
* @}
|
625 |
|
|
*/
|
626 |
|
|
|
627 |
|
|
/** @defgroup TIM_Ouput_Compare_Clear_State
|
628 |
|
|
* @{
|
629 |
|
|
*/
|
630 |
|
|
|
631 |
|
|
#define TIM_OCClear_Enable ((uint16_t)0x0080)
|
632 |
|
|
#define TIM_OCClear_Disable ((uint16_t)0x0000)
|
633 |
|
|
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
|
634 |
|
|
((STATE) == TIM_OCClear_Disable))
|
635 |
|
|
/**
|
636 |
|
|
* @}
|
637 |
|
|
*/
|
638 |
|
|
|
639 |
|
|
/** @defgroup TIM_Trigger_Output_Source
|
640 |
|
|
* @{
|
641 |
|
|
*/
|
642 |
|
|
|
643 |
|
|
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
|
644 |
|
|
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
|
645 |
|
|
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
|
646 |
|
|
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
|
647 |
|
|
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
|
648 |
|
|
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
|
649 |
|
|
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
|
650 |
|
|
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
|
651 |
|
|
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
|
652 |
|
|
((SOURCE) == TIM_TRGOSource_Enable) || \
|
653 |
|
|
((SOURCE) == TIM_TRGOSource_Update) || \
|
654 |
|
|
((SOURCE) == TIM_TRGOSource_OC1) || \
|
655 |
|
|
((SOURCE) == TIM_TRGOSource_OC1Ref) || \
|
656 |
|
|
((SOURCE) == TIM_TRGOSource_OC2Ref) || \
|
657 |
|
|
((SOURCE) == TIM_TRGOSource_OC3Ref) || \
|
658 |
|
|
((SOURCE) == TIM_TRGOSource_OC4Ref))
|
659 |
|
|
/**
|
660 |
|
|
* @}
|
661 |
|
|
*/
|
662 |
|
|
|
663 |
|
|
/** @defgroup TIM_Slave_Mode
|
664 |
|
|
* @{
|
665 |
|
|
*/
|
666 |
|
|
|
667 |
|
|
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
|
668 |
|
|
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
|
669 |
|
|
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
|
670 |
|
|
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
|
671 |
|
|
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
|
672 |
|
|
((MODE) == TIM_SlaveMode_Gated) || \
|
673 |
|
|
((MODE) == TIM_SlaveMode_Trigger) || \
|
674 |
|
|
((MODE) == TIM_SlaveMode_External1))
|
675 |
|
|
/**
|
676 |
|
|
* @}
|
677 |
|
|
*/
|
678 |
|
|
|
679 |
|
|
/** @defgroup TIM_Master_Slave_Mode
|
680 |
|
|
* @{
|
681 |
|
|
*/
|
682 |
|
|
|
683 |
|
|
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
|
684 |
|
|
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
|
685 |
|
|
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
|
686 |
|
|
((STATE) == TIM_MasterSlaveMode_Disable))
|
687 |
|
|
/**
|
688 |
|
|
* @}
|
689 |
|
|
*/
|
690 |
|
|
|
691 |
|
|
/** @defgroup TIM_Flags
|
692 |
|
|
* @{
|
693 |
|
|
*/
|
694 |
|
|
|
695 |
|
|
#define TIM_FLAG_Update ((uint16_t)0x0001)
|
696 |
|
|
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
|
697 |
|
|
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
|
698 |
|
|
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
|
699 |
|
|
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
|
700 |
|
|
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
|
701 |
|
|
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
|
702 |
|
|
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
|
703 |
|
|
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
|
704 |
|
|
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
|
705 |
|
|
#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
|
706 |
|
|
((FLAG) == TIM_FLAG_CC1) || \
|
707 |
|
|
((FLAG) == TIM_FLAG_CC2) || \
|
708 |
|
|
((FLAG) == TIM_FLAG_CC3) || \
|
709 |
|
|
((FLAG) == TIM_FLAG_CC4) || \
|
710 |
|
|
((FLAG) == TIM_FLAG_Trigger) || \
|
711 |
|
|
((FLAG) == TIM_FLAG_CC1OF) || \
|
712 |
|
|
((FLAG) == TIM_FLAG_CC2OF) || \
|
713 |
|
|
((FLAG) == TIM_FLAG_CC3OF) || \
|
714 |
|
|
((FLAG) == TIM_FLAG_CC4OF))
|
715 |
|
|
#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))
|
716 |
|
|
|
717 |
|
|
/**
|
718 |
|
|
* @}
|
719 |
|
|
*/
|
720 |
|
|
|
721 |
|
|
/** @defgroup TIM_Input_Capture_Filer_Value
|
722 |
|
|
* @{
|
723 |
|
|
*/
|
724 |
|
|
|
725 |
|
|
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
|
726 |
|
|
/**
|
727 |
|
|
* @}
|
728 |
|
|
*/
|
729 |
|
|
|
730 |
|
|
/** @defgroup TIM_External_Trigger_Filter
|
731 |
|
|
* @{
|
732 |
|
|
*/
|
733 |
|
|
|
734 |
|
|
#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
|
735 |
|
|
/**
|
736 |
|
|
* @}
|
737 |
|
|
*/
|
738 |
|
|
|
739 |
|
|
/** @defgroup TIM_OCReferenceClear
|
740 |
|
|
* @{
|
741 |
|
|
*/
|
742 |
|
|
#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
|
743 |
|
|
#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
|
744 |
|
|
#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
|
745 |
|
|
((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
|
746 |
|
|
|
747 |
|
|
/**
|
748 |
|
|
* @}
|
749 |
|
|
*/
|
750 |
|
|
|
751 |
|
|
/** @defgroup TIM_Remap
|
752 |
|
|
* @{
|
753 |
|
|
*/
|
754 |
|
|
|
755 |
|
|
#define TIM9_GPIO ((uint16_t)0x0000)
|
756 |
|
|
#define TIM9_LSE ((uint16_t)0x0001)
|
757 |
|
|
|
758 |
|
|
#define TIM10_GPIO ((uint16_t)0x0000)
|
759 |
|
|
#define TIM10_LSI ((uint16_t)0x0001)
|
760 |
|
|
#define TIM10_LSE ((uint16_t)0x0002)
|
761 |
|
|
#define TIM10_RTC ((uint16_t)0x0003)
|
762 |
|
|
|
763 |
|
|
#define TIM11_GPIO ((uint16_t)0x0000)
|
764 |
|
|
#define TIM11_MSI ((uint16_t)0x0001)
|
765 |
|
|
#define TIM11_HSE_RTC ((uint16_t)0x0002)
|
766 |
|
|
|
767 |
|
|
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM9_GPIO)||\
|
768 |
|
|
((TIM_REMAP) == TIM9_LSE)||\
|
769 |
|
|
((TIM_REMAP) == TIM10_GPIO)||\
|
770 |
|
|
((TIM_REMAP) == TIM10_LSI)||\
|
771 |
|
|
((TIM_REMAP) == TIM10_LSE)||\
|
772 |
|
|
((TIM_REMAP) == TIM10_RTC)||\
|
773 |
|
|
((TIM_REMAP) == TIM11_GPIO)||\
|
774 |
|
|
((TIM_REMAP) == TIM11_MSI)||\
|
775 |
|
|
((TIM_REMAP) == TIM11_HSE_RTC))
|
776 |
|
|
|
777 |
|
|
/**
|
778 |
|
|
* @}
|
779 |
|
|
*/
|
780 |
|
|
|
781 |
|
|
/**
|
782 |
|
|
* @}
|
783 |
|
|
*/
|
784 |
|
|
|
785 |
|
|
/** @defgroup TIM_Exported_Macros
|
786 |
|
|
* @{
|
787 |
|
|
*/
|
788 |
|
|
|
789 |
|
|
/**
|
790 |
|
|
* @}
|
791 |
|
|
*/
|
792 |
|
|
|
793 |
|
|
/** @defgroup TIM_Exported_Functions
|
794 |
|
|
* @{
|
795 |
|
|
*/
|
796 |
|
|
|
797 |
|
|
void TIM_DeInit(TIM_TypeDef* TIMx);
|
798 |
|
|
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
799 |
|
|
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
800 |
|
|
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
801 |
|
|
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
802 |
|
|
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
803 |
|
|
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
804 |
|
|
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
805 |
|
|
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
806 |
|
|
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
|
807 |
|
|
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
|
808 |
|
|
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
|
809 |
|
|
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
|
810 |
|
|
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
|
811 |
|
|
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
|
812 |
|
|
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
|
813 |
|
|
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
|
814 |
|
|
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
815 |
|
|
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
|
816 |
|
|
uint16_t TIM_ICPolarity, uint16_t ICFilter);
|
817 |
|
|
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
818 |
|
|
uint16_t ExtTRGFilter);
|
819 |
|
|
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
|
820 |
|
|
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
821 |
|
|
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
822 |
|
|
uint16_t ExtTRGFilter);
|
823 |
|
|
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
|
824 |
|
|
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
|
825 |
|
|
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
826 |
|
|
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
|
827 |
|
|
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
|
828 |
|
|
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
829 |
|
|
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
830 |
|
|
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
831 |
|
|
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
832 |
|
|
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
833 |
|
|
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
|
834 |
|
|
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
|
835 |
|
|
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
|
836 |
|
|
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
837 |
|
|
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
838 |
|
|
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
839 |
|
|
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
840 |
|
|
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
841 |
|
|
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
842 |
|
|
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
843 |
|
|
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
844 |
|
|
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
845 |
|
|
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
846 |
|
|
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
847 |
|
|
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
848 |
|
|
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
849 |
|
|
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
850 |
|
|
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
851 |
|
|
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
852 |
|
|
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
|
853 |
|
|
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
|
854 |
|
|
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
855 |
|
|
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
|
856 |
|
|
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
|
857 |
|
|
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
|
858 |
|
|
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
|
859 |
|
|
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
|
860 |
|
|
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
|
861 |
|
|
void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
|
862 |
|
|
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
|
863 |
|
|
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
|
864 |
|
|
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
|
865 |
|
|
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
|
866 |
|
|
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
|
867 |
|
|
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
868 |
|
|
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
869 |
|
|
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
870 |
|
|
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
871 |
|
|
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
|
872 |
|
|
uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
|
873 |
|
|
uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
|
874 |
|
|
uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
|
875 |
|
|
uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
|
876 |
|
|
uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
|
877 |
|
|
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
|
878 |
|
|
void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
|
879 |
|
|
void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
|
880 |
|
|
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
881 |
|
|
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
882 |
|
|
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
883 |
|
|
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
884 |
|
|
|
885 |
|
|
#ifdef __cplusplus
|
886 |
|
|
}
|
887 |
|
|
#endif
|
888 |
|
|
#endif /*__STM32L1xx_TIM_H */
|
889 |
|
|
/**
|
890 |
|
|
* @}
|
891 |
|
|
*/
|
892 |
|
|
|
893 |
|
|
/**
|
894 |
|
|
* @}
|
895 |
|
|
*/
|
896 |
|
|
|
897 |
|
|
/**
|
898 |
|
|
* @}
|
899 |
|
|
*/
|
900 |
|
|
|
901 |
|
|
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|