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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_STM32L152_IAR/] [system_and_ST_code/] [STM32L1xx_StdPeriph_Driver/] [src/] [stm32l1xx_pwr.c] - Blame information for rev 582

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1 582 jeremybenn
/**
2
  ******************************************************************************
3
  * @file    stm32l1xx_pwr.c
4
  * @author  MCD Application Team
5
  * @version V1.0.0RC1
6
  * @date    07/02/2010
7
  * @brief   This file provides all the PWR firmware functions.
8
  ******************************************************************************
9
  * @copy
10
  *
11
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17
  *
18
  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
19
  */
20
 
21
/* Includes ------------------------------------------------------------------*/
22
#include "stm32l1xx_pwr.h"
23
#include "stm32l1xx_rcc.h"
24
 
25
/** @addtogroup STM32L1xx_StdPeriph_Driver
26
  * @{
27
  */
28
 
29
/** @defgroup PWR
30
  * @brief PWR driver modules
31
  * @{
32
  */
33
 
34
/** @defgroup PWR_Private_TypesDefinitions
35
  * @{
36
  */
37
 
38
/**
39
  * @}
40
  */
41
 
42
/** @defgroup PWR_Private_Defines
43
  * @{
44
  */
45
 
46
/* --------- PWR registers bit address in the alias region ---------- */
47
#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
48
 
49
/* --- CR Register ---*/
50
 
51
/* Alias word address of DBP bit */
52
#define CR_OFFSET                (PWR_OFFSET + 0x00)
53
#define DBP_BitNumber            0x08
54
#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
55
 
56
/* Alias word address of PVDE bit */
57
#define PVDE_BitNumber           0x04
58
#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
59
 
60
/* Alias word address of ULP bit */
61
#define ULP_BitNumber           0x09
62
#define CR_ULP_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))
63
 
64
/* Alias word address of FWU bit */
65
#define FWU_BitNumber           0x0A
66
#define CR_FWU_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))
67
 
68
/* --- CSR Register ---*/
69
 
70
/* Alias word address of EWUP bit */
71
#define CSR_OFFSET               (PWR_OFFSET + 0x04)
72
#define EWUP_BitNumber           0x08
73
#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
74
 
75
/* ------------------ PWR registers bit mask ------------------------ */
76
 
77
/* CR register bit mask */
78
#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
79
#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
80
#define CR_VOS_MASK              ((uint32_t)0xFFFFE7FF)
81
 
82
/**
83
  * @}
84
  */
85
 
86
/** @defgroup PWR_Private_Macros
87
  * @{
88
  */
89
 
90
/**
91
  * @}
92
  */
93
 
94
/** @defgroup PWR_Private_Variables
95
  * @{
96
  */
97
 
98
/**
99
  * @}
100
  */
101
 
102
/** @defgroup PWR_Private_FunctionPrototypes
103
  * @{
104
  */
105
 
106
/**
107
  * @}
108
  */
109
 
110
/** @defgroup PWR_Private_Functions
111
  * @{
112
  */
113
 
114
/**
115
  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
116
  * @param  None
117
  * @retval None
118
  */
119
void PWR_DeInit(void)
120
{
121
  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
122
  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
123
}
124
 
125
/**
126
  * @brief  Enables or disables access to the RTC and backup registers.
127
  * @param  NewState: new state of the access to the RTC and backup registers.
128
  *   This parameter can be: ENABLE or DISABLE.
129
  * @retval None
130
  */
131
void PWR_RTCAccessCmd(FunctionalState NewState)
132
{
133
  /* Check the parameters */
134
  assert_param(IS_FUNCTIONAL_STATE(NewState));
135
 
136
  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
137
}
138
 
139
/**
140
  * @brief  Enables or disables the Power Voltage Detector(PVD).
141
  * @param  NewState: new state of the PVD.
142
  *   This parameter can be: ENABLE or DISABLE.
143
  * @retval None
144
  */
145
void PWR_PVDCmd(FunctionalState NewState)
146
{
147
  /* Check the parameters */
148
  assert_param(IS_FUNCTIONAL_STATE(NewState));
149
 
150
  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
151
}
152
 
153
/**
154
  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
155
  * @param  PWR_PVDLevel: specifies the PVD detection level
156
  *   This parameter can be one of the following values:
157
  *     @arg PWR_PVDLevel_0: PVD detection level set to 1.9V
158
  *     @arg PWR_PVDLevel_1: PVD detection level set to 2.1V
159
  *     @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
160
  *     @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
161
  *     @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
162
  *     @arg PWR_PVDLevel_5: PVD detection level set to 2.9V
163
  *     @arg PWR_PVDLevel_6: PVD detection level set to 3.1V
164
  *     @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)
165
  * @retval None
166
  */
167
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
168
{
169
  uint32_t tmpreg = 0;
170
 
171
  /* Check the parameters */
172
  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
173
 
174
  tmpreg = PWR->CR;
175
 
176
  /* Clear PLS[7:5] bits */
177
  tmpreg &= CR_PLS_MASK;
178
 
179
  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
180
  tmpreg |= PWR_PVDLevel;
181
 
182
  /* Store the new value */
183
  PWR->CR = tmpreg;
184
}
185
 
186
/**
187
  * @brief  Enables or disables the WakeUp Pin functionality.
188
  * @param  PWR_WakeUpPin: specifies the WakeUpPin.
189
  *   This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
190
  * @param  NewState: new state of the WakeUp Pin functionality.
191
  *   This parameter can be: ENABLE or DISABLE.
192
  * @retval None
193
  */
194
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
195
{
196
  __IO uint32_t tmp = 0;
197
 
198
  /* Check the parameters */
199
  assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
200
 
201
  assert_param(IS_FUNCTIONAL_STATE(NewState));
202
 
203
  tmp = CSR_EWUP_BB + PWR_WakeUpPin;
204
 
205
  *(__IO uint32_t *) (tmp) = (uint32_t)NewState;
206
}
207
 
208
/**
209
  * @brief  Enables or disables the Fast WakeUp from Ultra Low Power mode.
210
  * @param  NewState: new state of the Fast WakeUp  functionality.
211
  *   This parameter can be: ENABLE or DISABLE.
212
  * @retval None
213
  */
214
void PWR_FastWakeUpCmd(FunctionalState NewState)
215
{
216
  /* Check the parameters */
217
  assert_param(IS_FUNCTIONAL_STATE(NewState));
218
 
219
  *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;
220
}
221
 
222
/**
223
  * @brief  Enables or disables the Ultra Low Power mode.
224
  * @param  NewState: new state of the Ultra Low Power mode.
225
  *   This parameter can be: ENABLE or DISABLE.
226
  * @retval None
227
  */
228
void PWR_UltraLowPowerCmd(FunctionalState NewState)
229
{
230
  /* Check the parameters */
231
  assert_param(IS_FUNCTIONAL_STATE(NewState));
232
 
233
  *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;
234
}
235
 
236
/**
237
  * @brief  Configures the voltage scaling range.
238
  * @param  PWR_VoltageScaling: specifies the voltage scaling range.
239
  *   This parameter can be:
240
  *     @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1
241
  *     @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2
242
  *     @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3
243
  * @retval None
244
  */
245
void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)
246
{
247
  uint32_t tmp = 0;
248
 
249
  /* Check the parameters */
250
  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));
251
 
252
  tmp = PWR->CR;
253
 
254
  tmp &= CR_VOS_MASK;
255
  tmp |= PWR_VoltageScaling;
256
 
257
  PWR->CR = tmp & 0xFFFFFFF3;
258
 
259
}
260
 
261
/**
262
  * @brief  Enters/Exits the Low Power Run mode.
263
  * @param  NewState: new state of the Low Power Run mode.
264
  *   This parameter can be: ENABLE or DISABLE.
265
  * @retval None
266
  */
267
void PWR_EnterLowPowerRunMode(FunctionalState NewState)
268
{
269
  /* Check the parameters */
270
  assert_param(IS_FUNCTIONAL_STATE(NewState));
271
 
272
  if (NewState != DISABLE)
273
  {
274
    PWR->CR |= PWR_CR_LPSDSR;
275
    PWR->CR |= PWR_CR_LPRUN;
276
  }
277
  else
278
  {
279
    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN);
280
    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR);
281
  }
282
}
283
 
284
/**
285
  * @brief  Enters Sleep mode.
286
  * @param  PWR_Regulator: specifies the regulator state in Sleep mode.
287
  *   This parameter can be one of the following values:
288
  *     @arg PWR_Regulator_ON: Sleep mode with regulator ON
289
  *     @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode
290
  * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
291
  *   This parameter can be one of the following values:
292
  *     @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
293
  *     @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
294
  * @retval None
295
  */
296
void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
297
{
298
  uint32_t tmpreg = 0;
299
 
300
  /* Check the parameters */
301
  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
302
 
303
  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
304
 
305
  /* Select the regulator state in Sleep mode ---------------------------------*/
306
  tmpreg = PWR->CR;
307
 
308
  /* Clear PDDS and LPDSR bits */
309
  tmpreg &= CR_DS_MASK;
310
 
311
  /* Set LPDSR bit according to PWR_Regulator value */
312
  tmpreg |= PWR_Regulator;
313
 
314
  /* Store the new value */
315
  PWR->CR = tmpreg;
316
 
317
  /* Clear SLEEPDEEP bit of Cortex System Control Register */
318
  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
319
 
320
  /* Select SLEEP mode entry -------------------------------------------------*/
321
  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
322
  {
323
    /* Request Wait For Interrupt */
324
    __WFI();
325
  }
326
  else
327
  {
328
    /* Request Wait For Event */
329
    __WFE();
330
  }
331
}
332
 
333
/**
334
  * @brief  Enters STOP mode.
335
  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
336
  *   This parameter can be one of the following values:
337
  *     @arg PWR_Regulator_ON: STOP mode with regulator ON
338
  *     @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
339
  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
340
  *   This parameter can be one of the following values:
341
  *     @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
342
  *     @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
343
  * @retval None
344
  */
345
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
346
{
347
  uint32_t tmpreg = 0;
348
 
349
  /* Check the parameters */
350
  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
351
  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
352
 
353
  /* Select the regulator state in STOP mode ---------------------------------*/
354
  tmpreg = PWR->CR;
355
  /* Clear PDDS and LPDSR bits */
356
  tmpreg &= CR_DS_MASK;
357
 
358
  /* Set LPDSR bit according to PWR_Regulator value */
359
  tmpreg |= PWR_Regulator;
360
 
361
  /* Store the new value */
362
  PWR->CR = tmpreg;
363
 
364
  /* Set SLEEPDEEP bit of Cortex System Control Register */
365
  SCB->SCR |= SCB_SCR_SLEEPDEEP;
366
 
367
  /* Select STOP mode entry --------------------------------------------------*/
368
  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
369
  {
370
    /* Request Wait For Interrupt */
371
    __WFI();
372
  }
373
  else
374
  {
375
    /* Request Wait For Event */
376
    __WFE();
377
  }
378
  /* Reset SLEEPDEEP bit of Cortex System Control Register */
379
  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
380
}
381
 
382
/**
383
  * @brief  Enters STANDBY mode.
384
  * @param  None
385
  * @retval None
386
  */
387
void PWR_EnterSTANDBYMode(void)
388
{
389
  /* Clear Wake-up flag */
390
  PWR->CR |= PWR_CR_CWUF;
391
 
392
  /* Select STANDBY mode */
393
  PWR->CR |= PWR_CR_PDDS;
394
 
395
  /* Set SLEEPDEEP bit of Cortex System Control Register */
396
  SCB->SCR |= SCB_SCR_SLEEPDEEP;
397
 
398
/* This option is used to ensure that store operations are completed */
399
#if defined ( __CC_ARM   )
400
  __force_stores();
401
#endif
402
  /* Request Wait For Interrupt */
403
  __WFI();
404
}
405
 
406
/**
407
  * @brief  Checks whether the specified PWR flag is set or not.
408
  * @param  PWR_FLAG: specifies the flag to check.
409
  *   This parameter can be one of the following values:
410
  *     @arg PWR_FLAG_WU: Wake Up flag
411
  *     @arg PWR_FLAG_SB: StandBy flag
412
  *     @arg PWR_FLAG_PVDO: PVD Output
413
  *     @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag
414
  *     @arg PWR_FLAG_VOS: Voltage Scaling select flag
415
  *     @arg PWR_FLAG_REGLP: Regulator LP flag
416
  * @retval The new state of PWR_FLAG (SET or RESET).
417
  */
418
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
419
{
420
  FlagStatus bitstatus = RESET;
421
  /* Check the parameters */
422
  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
423
 
424
  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
425
  {
426
    bitstatus = SET;
427
  }
428
  else
429
  {
430
    bitstatus = RESET;
431
  }
432
  /* Return the flag status */
433
  return bitstatus;
434
}
435
 
436
/**
437
  * @brief  Clears the PWR's pending flags.
438
  * @param  PWR_FLAG: specifies the flag to clear.
439
  *   This parameter can be one of the following values:
440
  *     @arg PWR_FLAG_WU: Wake Up flag
441
  *     @arg PWR_FLAG_SB: StandBy flag
442
  * @retval None
443
  */
444
void PWR_ClearFlag(uint32_t PWR_FLAG)
445
{
446
  /* Check the parameters */
447
  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
448
 
449
  PWR->CR |=  PWR_FLAG << 2;
450
}
451
 
452
/**
453
  * @}
454
  */
455
 
456
/**
457
  * @}
458
  */
459
 
460
/**
461
  * @}
462
  */
463
 
464
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

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