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jeremybenn |
/**
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******************************************************************************
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* @file stm32l1xx_rcc.c
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* @author MCD Application Team
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* @version V1.0.0RC1
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* @date 07/02/2010
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* @brief This file provides all the RCC firmware functions.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx_rcc.h"
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/** @addtogroup STM32L1xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup RCC
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* @brief RCC driver modules
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* @{
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*/
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/** @defgroup RCC_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup RCC_Private_Defines
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* @{
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*/
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/* ------------ RCC registers bit address in the alias region ----------- */
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#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
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/* --- CR Register ---*/
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/* Alias word address of HSION bit */
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#define CR_OFFSET (RCC_OFFSET + 0x00)
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#define HSION_BitNumber 0x00
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#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
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/* Alias word address of MSION bit */
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#define MSION_BitNumber 0x08
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#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
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/* Alias word address of PLLON bit */
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#define PLLON_BitNumber 0x18
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#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
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/* Alias word address of CSSON bit */
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#define CSSON_BitNumber 0x1C
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#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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/* --- CSR Register ---*/
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/* Alias word address of LSION bit */
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#define CSR_OFFSET (RCC_OFFSET + 0x34)
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#define LSION_BitNumber 0x00
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#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
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/* Alias word address of RTCEN bit */
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#define RTCEN_BitNumber 0x16
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#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
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/* Alias word address of RTCRST bit */
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#define RTCRST_BitNumber 0x17
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#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
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/* ---------------------- RCC registers mask -------------------------------- */
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/* RCC Flag Mask */
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#define FLAG_MASK ((uint8_t)0x1F)
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/* CR register byte 3 (Bits[23:16]) base address */
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#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
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/* ICSCR register byte 4 (Bits[31:24]) base address */
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#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)
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/* CFGR register byte 3 (Bits[23:16]) base address */
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#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)
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/* CFGR register byte 4 (Bits[31:24]) base address */
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#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)
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/* CIR register byte 2 (Bits[15:8]) base address */
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#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)
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/* CIR register byte 3 (Bits[23:16]) base address */
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#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)
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/* CSR register byte 2 (Bits[15:8]) base address */
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#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)
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/**
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* @}
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*/
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/** @defgroup RCC_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup RCC_Private_Variables
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* @{
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*/
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static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
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static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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static __I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};
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/**
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* @}
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*/
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/** @defgroup RCC_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup RCC_Private_Functions
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* @{
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*/
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/**
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* @brief Resets the RCC clock configuration to the default reset state.
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* @param None
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* @retval None
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*/
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void RCC_DeInit(void)
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{
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/* Set MSION bit */
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RCC->CR |= (uint32_t)0x00000100;
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/* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
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RCC->CFGR &= (uint32_t)0x88FFC00C;
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/* Reset HSION, HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xEEFEFFFE;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
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RCC->CFGR &= (uint32_t)0xFF02FFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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}
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/**
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* @brief Configures the External High Speed oscillator (HSE).
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* @note HSE can not be stopped if it is used directly or through the PLL as system clock.
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* @param RCC_HSE: specifies the new state of the HSE.
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* This parameter can be one of the following values:
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* @arg RCC_HSE_OFF: HSE oscillator OFF
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* @arg RCC_HSE_ON: HSE oscillator ON
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* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
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* @retval None
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*/
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void RCC_HSEConfig(uint8_t RCC_HSE)
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{
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/* Check the parameters */
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assert_param(IS_RCC_HSE(RCC_HSE));
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/* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
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*(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
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/* Set the new HSE configuration -------------------------------------------*/
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*(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
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}
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/**
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* @brief Waits for HSE start-up.
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* @param None
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* @retval An ErrorStatus enumuration value:
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* - SUCCESS: HSE oscillator is stable and ready to use
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* - ERROR: HSE oscillator not yet ready
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*/
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ErrorStatus RCC_WaitForHSEStartUp(void)
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{
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__IO uint32_t StartUpCounter = 0;
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ErrorStatus status = ERROR;
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FlagStatus HSEStatus = RESET;
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
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StartUpCounter++;
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} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
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if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
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{
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status = SUCCESS;
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}
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else
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{
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status = ERROR;
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}
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return (status);
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}
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/**
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* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
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* @param HSICalibrationValue: specifies the HSI calibration trimming value.
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* This parameter must be a number between 0 and 0x1F.
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* @retval None
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*/
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void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
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tmpreg = RCC->ICSCR;
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/* Clear HSITRIM[4:0] bits */
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tmpreg &= ~RCC_ICSCR_HSITRIM;
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/* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
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tmpreg |= (uint32_t)HSICalibrationValue << 8;
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/* Store the new value */
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RCC->ICSCR = tmpreg;
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}
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/**
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* @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
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* @param MSICalibrationValue: specifies the MSI calibration trimming value.
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* This parameter must be a number between 0 and 0xFF.
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* @retval None
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*/
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void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)
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{
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/* Check the parameters */
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assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));
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*(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue;
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}
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/**
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* @brief Configures the Internal Multi Speed oscillator (MSI) clock range.
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* @param RCC_MSIRange: specifies the MSI Clcok range.
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* This parameter must be one of the following values:
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* @arg RCC_MSIRange_64KHz: MSI clock is around 64 KHz
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* @arg RCC_MSIRange_128KHz: MSI clock is around 128 KHz
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* @arg RCC_MSIRange_256KHz: MSI clock is around 256 KHz
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* @arg RCC_MSIRange_512KHz: MSI clock is around 512 KHz
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* @arg RCC_MSIRange_1MHz: MSI clock is around 1 MHz
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* @arg RCC_MSIRange_2MHz: MSI clock is around 2 MHz
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* @arg RCC_MSIRange_4MHz: MSI clock is around 4 MHz
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* @retval None
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*/
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void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));
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tmpreg = RCC->ICSCR;
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/* Clear MSIRANGE[2:0] bits */
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tmpreg &= ~RCC_ICSCR_MSIRANGE;
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/* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */
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tmpreg |= (uint32_t)RCC_MSIRange;
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/* Store the new value */
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RCC->ICSCR = tmpreg;
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}
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/**
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* @brief Enables or disables the Internal Multi Speed oscillator (MSI).
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* @note MSI can not be stopped if it is used directly as system clock.
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* @param NewState: new state of the MSI.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void RCC_MSICmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;
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}
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/**
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* @brief Enables or disables the Internal High Speed oscillator (HSI).
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* @note HSI can not be stopped if it is used directly or through the PLL as system clock.
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* @param NewState: new state of the HSI.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void RCC_HSICmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
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}
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/**
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* @brief Configures the PLL clock source and multiplication factor.
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* @note This function must be used only when the PLL is disabled.
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* @param RCC_PLLSource: specifies the PLL entry clock source.
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* This parameter can be one of the following values:
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* @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
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* @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
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* @param RCC_PLLMul: specifies the PLL multiplication factor.
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* This parameter can be:
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* @arg RCC_PLLMul_3: PLL Clock entry multiplied by 3
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* @arg RCC_PLLMul_4: PLL Clock entry multiplied by 4
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* @arg RCC_PLLMul_6: PLL Clock entry multiplied by 6
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* @arg RCC_PLLMul_8: PLL Clock entry multiplied by 8
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* @arg RCC_PLLMul_12: PLL Clock entry multiplied by 12
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* @arg RCC_PLLMul_16: PLL Clock entry multiplied by 16
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* @arg RCC_PLLMul_24: PLL Clock entry multiplied by 24
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* @arg RCC_PLLMul_32: PLL Clock entry multiplied by 32
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* @arg RCC_PLLMul_48: PLL Clock entry multiplied by 48
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* @param RCC_PLLDiv: specifies the PLL division factor.
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* This parameter can be:
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|
|
* @arg RCC_PLLDiv_2: PLL Clock output divided by 2
|
348 |
|
|
* @arg RCC_PLLDiv_3: PLL Clock output divided by 3
|
349 |
|
|
* @arg RCC_PLLDiv_4: PLL Clock output divided by 4
|
350 |
|
|
* @retval None
|
351 |
|
|
*/
|
352 |
|
|
void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
|
353 |
|
|
{
|
354 |
|
|
/* Check the parameters */
|
355 |
|
|
assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
|
356 |
|
|
assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
|
357 |
|
|
assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));
|
358 |
|
|
|
359 |
|
|
*(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));
|
360 |
|
|
}
|
361 |
|
|
|
362 |
|
|
/**
|
363 |
|
|
* @brief Enables or disables the PLL.
|
364 |
|
|
* @note The PLL can not be disabled if it is used as system clock.
|
365 |
|
|
* @param NewState: new state of the PLL.
|
366 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
367 |
|
|
* @retval None
|
368 |
|
|
*/
|
369 |
|
|
void RCC_PLLCmd(FunctionalState NewState)
|
370 |
|
|
{
|
371 |
|
|
/* Check the parameters */
|
372 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
373 |
|
|
|
374 |
|
|
*(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
|
375 |
|
|
}
|
376 |
|
|
|
377 |
|
|
/**
|
378 |
|
|
* @brief Configures the system clock (SYSCLK).
|
379 |
|
|
* @param RCC_SYSCLKSource: specifies the clock source used as system clock.
|
380 |
|
|
* This parameter can be one of the following values:
|
381 |
|
|
* @arg RCC_SYSCLKSource_MSI: MSI selected as system clock
|
382 |
|
|
* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
|
383 |
|
|
* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
|
384 |
|
|
* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
|
385 |
|
|
* @retval None
|
386 |
|
|
*/
|
387 |
|
|
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
|
388 |
|
|
{
|
389 |
|
|
uint32_t tmpreg = 0;
|
390 |
|
|
|
391 |
|
|
/* Check the parameters */
|
392 |
|
|
assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
|
393 |
|
|
|
394 |
|
|
tmpreg = RCC->CFGR;
|
395 |
|
|
|
396 |
|
|
/* Clear SW[1:0] bits */
|
397 |
|
|
tmpreg &= ~RCC_CFGR_SW;
|
398 |
|
|
|
399 |
|
|
/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
|
400 |
|
|
tmpreg |= RCC_SYSCLKSource;
|
401 |
|
|
|
402 |
|
|
/* Store the new value */
|
403 |
|
|
RCC->CFGR = tmpreg;
|
404 |
|
|
}
|
405 |
|
|
|
406 |
|
|
/**
|
407 |
|
|
* @brief Returns the clock source used as system clock.
|
408 |
|
|
* @param None
|
409 |
|
|
* @retval The clock source used as system clock. The returned value can be one
|
410 |
|
|
* of the following values:
|
411 |
|
|
* - 0x00: MSI used as system clock
|
412 |
|
|
* - 0x04: HSI used as system clock
|
413 |
|
|
* - 0x08: HSE used as system clock
|
414 |
|
|
* - 0x0C: PLL used as system clock
|
415 |
|
|
*/
|
416 |
|
|
uint8_t RCC_GetSYSCLKSource(void)
|
417 |
|
|
{
|
418 |
|
|
return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
|
419 |
|
|
}
|
420 |
|
|
|
421 |
|
|
/**
|
422 |
|
|
* @brief Configures the AHB clock (HCLK).
|
423 |
|
|
* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
|
424 |
|
|
* the system clock (SYSCLK).
|
425 |
|
|
* This parameter can be one of the following values:
|
426 |
|
|
* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
|
427 |
|
|
* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
|
428 |
|
|
* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
|
429 |
|
|
* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
|
430 |
|
|
* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
|
431 |
|
|
* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
|
432 |
|
|
* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
|
433 |
|
|
* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
|
434 |
|
|
* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
|
435 |
|
|
* @retval None
|
436 |
|
|
*/
|
437 |
|
|
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
|
438 |
|
|
{
|
439 |
|
|
uint32_t tmpreg = 0;
|
440 |
|
|
|
441 |
|
|
/* Check the parameters */
|
442 |
|
|
assert_param(IS_RCC_HCLK(RCC_SYSCLK));
|
443 |
|
|
|
444 |
|
|
tmpreg = RCC->CFGR;
|
445 |
|
|
|
446 |
|
|
/* Clear HPRE[3:0] bits */
|
447 |
|
|
tmpreg &= ~RCC_CFGR_HPRE;
|
448 |
|
|
|
449 |
|
|
/* Set HPRE[3:0] bits according to RCC_SYSCLK value */
|
450 |
|
|
tmpreg |= RCC_SYSCLK;
|
451 |
|
|
|
452 |
|
|
/* Store the new value */
|
453 |
|
|
RCC->CFGR = tmpreg;
|
454 |
|
|
}
|
455 |
|
|
|
456 |
|
|
/**
|
457 |
|
|
* @brief Configures the Low Speed APB clock (PCLK1).
|
458 |
|
|
* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
|
459 |
|
|
* the AHB clock (HCLK).
|
460 |
|
|
* This parameter can be one of the following values:
|
461 |
|
|
* @arg RCC_HCLK_Div1: APB1 clock = HCLK
|
462 |
|
|
* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
|
463 |
|
|
* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
|
464 |
|
|
* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
|
465 |
|
|
* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
|
466 |
|
|
* @retval None
|
467 |
|
|
*/
|
468 |
|
|
void RCC_PCLK1Config(uint32_t RCC_HCLK)
|
469 |
|
|
{
|
470 |
|
|
uint32_t tmpreg = 0;
|
471 |
|
|
|
472 |
|
|
/* Check the parameters */
|
473 |
|
|
assert_param(IS_RCC_PCLK(RCC_HCLK));
|
474 |
|
|
|
475 |
|
|
tmpreg = RCC->CFGR;
|
476 |
|
|
|
477 |
|
|
/* Clear PPRE1[2:0] bits */
|
478 |
|
|
tmpreg &= ~RCC_CFGR_PPRE1;
|
479 |
|
|
|
480 |
|
|
/* Set PPRE1[2:0] bits according to RCC_HCLK value */
|
481 |
|
|
tmpreg |= RCC_HCLK;
|
482 |
|
|
|
483 |
|
|
/* Store the new value */
|
484 |
|
|
RCC->CFGR = tmpreg;
|
485 |
|
|
}
|
486 |
|
|
|
487 |
|
|
/**
|
488 |
|
|
* @brief Configures the High Speed APB clock (PCLK2).
|
489 |
|
|
* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
|
490 |
|
|
* the AHB clock (HCLK).
|
491 |
|
|
* This parameter can be one of the following values:
|
492 |
|
|
* @arg RCC_HCLK_Div1: APB2 clock = HCLK
|
493 |
|
|
* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
|
494 |
|
|
* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
|
495 |
|
|
* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
|
496 |
|
|
* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
|
497 |
|
|
* @retval None
|
498 |
|
|
*/
|
499 |
|
|
void RCC_PCLK2Config(uint32_t RCC_HCLK)
|
500 |
|
|
{
|
501 |
|
|
uint32_t tmpreg = 0;
|
502 |
|
|
|
503 |
|
|
/* Check the parameters */
|
504 |
|
|
assert_param(IS_RCC_PCLK(RCC_HCLK));
|
505 |
|
|
|
506 |
|
|
tmpreg = RCC->CFGR;
|
507 |
|
|
|
508 |
|
|
/* Clear PPRE2[2:0] bits */
|
509 |
|
|
tmpreg &= ~RCC_CFGR_PPRE2;
|
510 |
|
|
|
511 |
|
|
/* Set PPRE2[2:0] bits according to RCC_HCLK value */
|
512 |
|
|
tmpreg |= RCC_HCLK << 3;
|
513 |
|
|
|
514 |
|
|
/* Store the new value */
|
515 |
|
|
RCC->CFGR = tmpreg;
|
516 |
|
|
}
|
517 |
|
|
|
518 |
|
|
/**
|
519 |
|
|
* @brief Enables or disables the specified RCC interrupts.
|
520 |
|
|
* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
|
521 |
|
|
* This parameter can be any combination of the following values:
|
522 |
|
|
* @arg RCC_IT_LSIRDY: LSI ready interrupt
|
523 |
|
|
* @arg RCC_IT_LSERDY: LSE ready interrupt
|
524 |
|
|
* @arg RCC_IT_HSIRDY: HSI ready interrupt
|
525 |
|
|
* @arg RCC_IT_HSERDY: HSE ready interrupt
|
526 |
|
|
* @arg RCC_IT_PLLRDY: PLL ready interrupt
|
527 |
|
|
* @arg RCC_IT_MSIRDY: MSI ready interrupt
|
528 |
|
|
* @param NewState: new state of the specified RCC interrupts.
|
529 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
530 |
|
|
* @retval None
|
531 |
|
|
*/
|
532 |
|
|
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
|
533 |
|
|
{
|
534 |
|
|
/* Check the parameters */
|
535 |
|
|
assert_param(IS_RCC_IT(RCC_IT));
|
536 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
537 |
|
|
|
538 |
|
|
if (NewState != DISABLE)
|
539 |
|
|
{
|
540 |
|
|
/* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
|
541 |
|
|
*(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
|
542 |
|
|
}
|
543 |
|
|
else
|
544 |
|
|
{
|
545 |
|
|
/* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
|
546 |
|
|
*(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
|
547 |
|
|
}
|
548 |
|
|
}
|
549 |
|
|
|
550 |
|
|
/**
|
551 |
|
|
* @brief Configures the External Low Speed oscillator (LSE).
|
552 |
|
|
* @param RCC_LSE: specifies the new state of the LSE.
|
553 |
|
|
* This parameter can be one of the following values:
|
554 |
|
|
* @arg RCC_LSE_OFF: LSE oscillator OFF
|
555 |
|
|
* @arg RCC_LSE_ON: LSE oscillator ON
|
556 |
|
|
* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
|
557 |
|
|
* @retval None
|
558 |
|
|
*/
|
559 |
|
|
void RCC_LSEConfig(uint8_t RCC_LSE)
|
560 |
|
|
{
|
561 |
|
|
/* Check the parameters */
|
562 |
|
|
assert_param(IS_RCC_LSE(RCC_LSE));
|
563 |
|
|
|
564 |
|
|
/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
|
565 |
|
|
*(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;
|
566 |
|
|
|
567 |
|
|
/* Set the new LSE configuration -------------------------------------------*/
|
568 |
|
|
*(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE;
|
569 |
|
|
}
|
570 |
|
|
|
571 |
|
|
/**
|
572 |
|
|
* @brief Enables or disables the Internal Low Speed oscillator (LSI).
|
573 |
|
|
* @note LSI can not be disabled if the IWDG is running.
|
574 |
|
|
* @param NewState: new state of the LSI.
|
575 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
576 |
|
|
* @retval None
|
577 |
|
|
*/
|
578 |
|
|
void RCC_LSICmd(FunctionalState NewState)
|
579 |
|
|
{
|
580 |
|
|
/* Check the parameters */
|
581 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
582 |
|
|
|
583 |
|
|
*(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
|
584 |
|
|
}
|
585 |
|
|
|
586 |
|
|
/**
|
587 |
|
|
* @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK).
|
588 |
|
|
* @note
|
589 |
|
|
* - Once the RTC clock is selected it can't be changed unless the RTC is
|
590 |
|
|
* reset using RCC_RTCResetCmd function.
|
591 |
|
|
* - This RTC clock (RTCCLK) is used to clock the LCD (LCDCLK).
|
592 |
|
|
* @param RCC_RTCCLKSource: specifies the RTC clock source.
|
593 |
|
|
* This parameter can be one of the following values:
|
594 |
|
|
* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
|
595 |
|
|
* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
|
596 |
|
|
* @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
|
597 |
|
|
* @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
|
598 |
|
|
* @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
|
599 |
|
|
* @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
|
600 |
|
|
* @retval None
|
601 |
|
|
*/
|
602 |
|
|
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
|
603 |
|
|
{
|
604 |
|
|
uint32_t tmpreg = 0;
|
605 |
|
|
|
606 |
|
|
/* Check the parameters */
|
607 |
|
|
assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
|
608 |
|
|
|
609 |
|
|
if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)
|
610 |
|
|
{
|
611 |
|
|
/* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
|
612 |
|
|
tmpreg = RCC->CR;
|
613 |
|
|
|
614 |
|
|
/* Clear RTCPRE[1:0] bits */
|
615 |
|
|
tmpreg &= ~RCC_CR_RTCPRE;
|
616 |
|
|
|
617 |
|
|
/* Configure HSE division factor for RTC clock */
|
618 |
|
|
tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);
|
619 |
|
|
|
620 |
|
|
/* Store the new value */
|
621 |
|
|
RCC->CR = tmpreg;
|
622 |
|
|
}
|
623 |
|
|
|
624 |
|
|
RCC->CSR &= ~RCC_CSR_RTCSEL;
|
625 |
|
|
|
626 |
|
|
/* Select the RTC clock source */
|
627 |
|
|
RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);
|
628 |
|
|
}
|
629 |
|
|
|
630 |
|
|
/**
|
631 |
|
|
* @brief Enables or disables the RTC clock.
|
632 |
|
|
* @note This function must be used only after the RTC clock was selected using the
|
633 |
|
|
* RCC_RTCCLKConfig function.
|
634 |
|
|
* @param NewState: new state of the RTC clock.
|
635 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
636 |
|
|
* @retval None
|
637 |
|
|
*/
|
638 |
|
|
void RCC_RTCCLKCmd(FunctionalState NewState)
|
639 |
|
|
{
|
640 |
|
|
/* Check the parameters */
|
641 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
642 |
|
|
|
643 |
|
|
*(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;
|
644 |
|
|
}
|
645 |
|
|
|
646 |
|
|
/**
|
647 |
|
|
* @brief Forces or releases the RTC peripheral reset.
|
648 |
|
|
* @param NewState: new state of the RTC reset.
|
649 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
650 |
|
|
* @retval None
|
651 |
|
|
*/
|
652 |
|
|
void RCC_RTCResetCmd(FunctionalState NewState)
|
653 |
|
|
{
|
654 |
|
|
/* Check the parameters */
|
655 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
656 |
|
|
|
657 |
|
|
*(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;
|
658 |
|
|
}
|
659 |
|
|
|
660 |
|
|
/**
|
661 |
|
|
* @brief Returns the frequencies of different on chip clocks.
|
662 |
|
|
* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
|
663 |
|
|
* the clocks frequencies.
|
664 |
|
|
* @retval None
|
665 |
|
|
*/
|
666 |
|
|
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
|
667 |
|
|
{
|
668 |
|
|
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;
|
669 |
|
|
|
670 |
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
671 |
|
|
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
672 |
|
|
|
673 |
|
|
switch (tmp)
|
674 |
|
|
{
|
675 |
|
|
case 0x00: /* MSI used as system clock */
|
676 |
|
|
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
|
677 |
|
|
RCC_Clocks->SYSCLK_Frequency = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));
|
678 |
|
|
break;
|
679 |
|
|
case 0x04: /* HSI used as system clock */
|
680 |
|
|
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
|
681 |
|
|
break;
|
682 |
|
|
case 0x08: /* HSE used as system clock */
|
683 |
|
|
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
|
684 |
|
|
break;
|
685 |
|
|
case 0x0C: /* PLL used as system clock */
|
686 |
|
|
/* Get PLL clock source and multiplication factor ----------------------*/
|
687 |
|
|
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
|
688 |
|
|
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
|
689 |
|
|
pllmul = PLLMulTable[(pllmul >> 18)];
|
690 |
|
|
plldiv = (plldiv >> 22) + 1;
|
691 |
|
|
|
692 |
|
|
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
693 |
|
|
|
694 |
|
|
if (pllsource == 0x00)
|
695 |
|
|
{
|
696 |
|
|
/* HSI oscillator clock selected as PLL clock entry */
|
697 |
|
|
RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);
|
698 |
|
|
}
|
699 |
|
|
else
|
700 |
|
|
{
|
701 |
|
|
/* HSE selected as PLL clock entry */
|
702 |
|
|
RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);
|
703 |
|
|
}
|
704 |
|
|
break;
|
705 |
|
|
default:
|
706 |
|
|
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
|
707 |
|
|
break;
|
708 |
|
|
}
|
709 |
|
|
/* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
|
710 |
|
|
/* Get HCLK prescaler */
|
711 |
|
|
tmp = RCC->CFGR & RCC_CFGR_HPRE;
|
712 |
|
|
tmp = tmp >> 4;
|
713 |
|
|
presc = APBAHBPrescTable[tmp];
|
714 |
|
|
/* HCLK clock frequency */
|
715 |
|
|
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
|
716 |
|
|
|
717 |
|
|
/* Get PCLK1 prescaler */
|
718 |
|
|
tmp = RCC->CFGR & RCC_CFGR_PPRE1;
|
719 |
|
|
tmp = tmp >> 8;
|
720 |
|
|
presc = APBAHBPrescTable[tmp];
|
721 |
|
|
/* PCLK1 clock frequency */
|
722 |
|
|
RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
|
723 |
|
|
|
724 |
|
|
/* Get PCLK2 prescaler */
|
725 |
|
|
tmp = RCC->CFGR & RCC_CFGR_PPRE2;
|
726 |
|
|
tmp = tmp >> 11;
|
727 |
|
|
presc = APBAHBPrescTable[tmp];
|
728 |
|
|
/* PCLK2 clock frequency */
|
729 |
|
|
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
|
730 |
|
|
}
|
731 |
|
|
|
732 |
|
|
/**
|
733 |
|
|
* @brief Enables or disables the AHB peripheral clock.
|
734 |
|
|
* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
|
735 |
|
|
* This parameter can be any combination of the following values:
|
736 |
|
|
* @arg RCC_AHBPeriph_GPIOA
|
737 |
|
|
* @arg RCC_AHBPeriph_GPIOB
|
738 |
|
|
* @arg RCC_AHBPeriph_GPIOC
|
739 |
|
|
* @arg RCC_AHBPeriph_GPIOD
|
740 |
|
|
* @arg RCC_AHBPeriph_GPIOE
|
741 |
|
|
* @arg RCC_AHBPeriph_GPIOH
|
742 |
|
|
* @arg RCC_AHBPeriph_CRC
|
743 |
|
|
* @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
|
744 |
|
|
* @arg RCC_AHBPeriph_DMA1
|
745 |
|
|
* @param NewState: new state of the specified peripheral clock.
|
746 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
747 |
|
|
* @retval None
|
748 |
|
|
*/
|
749 |
|
|
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
|
750 |
|
|
{
|
751 |
|
|
/* Check the parameters */
|
752 |
|
|
assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
|
753 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
754 |
|
|
|
755 |
|
|
if (NewState != DISABLE)
|
756 |
|
|
{
|
757 |
|
|
RCC->AHBENR |= RCC_AHBPeriph;
|
758 |
|
|
}
|
759 |
|
|
else
|
760 |
|
|
{
|
761 |
|
|
RCC->AHBENR &= ~RCC_AHBPeriph;
|
762 |
|
|
}
|
763 |
|
|
}
|
764 |
|
|
|
765 |
|
|
/**
|
766 |
|
|
* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
|
767 |
|
|
* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
|
768 |
|
|
* This parameter can be any combination of the following values:
|
769 |
|
|
* @arg RCC_APB2Periph_SYSCFG
|
770 |
|
|
* @arg RCC_APB2Periph_TIM9
|
771 |
|
|
* @arg RCC_APB2Periph_TIM10
|
772 |
|
|
* @arg RCC_APB2Periph_TIM11
|
773 |
|
|
* @arg RCC_APB2Periph_ADC1
|
774 |
|
|
* @arg RCC_APB2Periph_SPI1
|
775 |
|
|
* @arg RCC_APB2Periph_USART1
|
776 |
|
|
* @param NewState: new state of the specified peripheral clock.
|
777 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
778 |
|
|
* @retval None
|
779 |
|
|
*/
|
780 |
|
|
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
781 |
|
|
{
|
782 |
|
|
/* Check the parameters */
|
783 |
|
|
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
|
784 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
785 |
|
|
|
786 |
|
|
if (NewState != DISABLE)
|
787 |
|
|
{
|
788 |
|
|
RCC->APB2ENR |= RCC_APB2Periph;
|
789 |
|
|
}
|
790 |
|
|
else
|
791 |
|
|
{
|
792 |
|
|
RCC->APB2ENR &= ~RCC_APB2Periph;
|
793 |
|
|
}
|
794 |
|
|
}
|
795 |
|
|
|
796 |
|
|
/**
|
797 |
|
|
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
|
798 |
|
|
* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
|
799 |
|
|
* This parameter can be any combination of the following values:
|
800 |
|
|
* @arg RCC_APB1Periph_TIM2
|
801 |
|
|
* @arg RCC_APB1Periph_TIM3
|
802 |
|
|
* @arg RCC_APB1Periph_TIM4
|
803 |
|
|
* @arg RCC_APB1Periph_TIM6
|
804 |
|
|
* @arg RCC_APB1Periph_TIM7
|
805 |
|
|
* @arg RCC_APB1Periph_LCD
|
806 |
|
|
* @arg RCC_APB1Periph_WWDG
|
807 |
|
|
* @arg RCC_APB1Periph_SPI2
|
808 |
|
|
* @arg RCC_APB1Periph_USART2
|
809 |
|
|
* @arg RCC_APB1Periph_USART3
|
810 |
|
|
* @arg RCC_APB1Periph_I2C1
|
811 |
|
|
* @arg RCC_APB1Periph_I2C2
|
812 |
|
|
* @arg RCC_APB1Periph_USB
|
813 |
|
|
* @arg RCC_APB1Periph_PWR
|
814 |
|
|
* @arg RCC_APB1Periph_DAC
|
815 |
|
|
* @arg RCC_APB1Periph_COMP
|
816 |
|
|
* @param NewState: new state of the specified peripheral clock.
|
817 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
818 |
|
|
* @retval None
|
819 |
|
|
*/
|
820 |
|
|
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
821 |
|
|
{
|
822 |
|
|
/* Check the parameters */
|
823 |
|
|
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
|
824 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
825 |
|
|
|
826 |
|
|
if (NewState != DISABLE)
|
827 |
|
|
{
|
828 |
|
|
RCC->APB1ENR |= RCC_APB1Periph;
|
829 |
|
|
}
|
830 |
|
|
else
|
831 |
|
|
{
|
832 |
|
|
RCC->APB1ENR &= ~RCC_APB1Periph;
|
833 |
|
|
}
|
834 |
|
|
}
|
835 |
|
|
|
836 |
|
|
/**
|
837 |
|
|
* @brief Forces or releases AHB peripheral reset.
|
838 |
|
|
* @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
|
839 |
|
|
* This parameter can be any combination of the following values:
|
840 |
|
|
* @arg RCC_AHBPeriph_GPIOA
|
841 |
|
|
* @arg RCC_AHBPeriph_GPIOB
|
842 |
|
|
* @arg RCC_AHBPeriph_GPIOC
|
843 |
|
|
* @arg RCC_AHBPeriph_GPIOD
|
844 |
|
|
* @arg RCC_AHBPeriph_GPIOE
|
845 |
|
|
* @arg RCC_AHBPeriph_GPIOH
|
846 |
|
|
* @arg RCC_AHBPeriph_CRC
|
847 |
|
|
* @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
|
848 |
|
|
* @arg RCC_AHBPeriph_DMA1
|
849 |
|
|
* @param NewState: new state of the specified peripheral reset.
|
850 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
851 |
|
|
* @retval None
|
852 |
|
|
*/
|
853 |
|
|
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
|
854 |
|
|
{
|
855 |
|
|
/* Check the parameters */
|
856 |
|
|
assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
|
857 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
858 |
|
|
|
859 |
|
|
if (NewState != DISABLE)
|
860 |
|
|
{
|
861 |
|
|
RCC->AHBRSTR |= RCC_AHBPeriph;
|
862 |
|
|
}
|
863 |
|
|
else
|
864 |
|
|
{
|
865 |
|
|
RCC->AHBRSTR &= ~RCC_AHBPeriph;
|
866 |
|
|
}
|
867 |
|
|
}
|
868 |
|
|
|
869 |
|
|
/**
|
870 |
|
|
* @brief Forces or releases High Speed APB (APB2) peripheral reset.
|
871 |
|
|
* @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
|
872 |
|
|
* This parameter can be any combination of the following values:
|
873 |
|
|
* @arg RCC_APB2Periph_SYSCFG
|
874 |
|
|
* @arg RCC_APB2Periph_TIM9
|
875 |
|
|
* @arg RCC_APB2Periph_TIM10
|
876 |
|
|
* @arg RCC_APB2Periph_TIM11
|
877 |
|
|
* @arg RCC_APB2Periph_ADC1
|
878 |
|
|
* @arg RCC_APB2Periph_SPI1
|
879 |
|
|
* @arg RCC_APB2Periph_USART1
|
880 |
|
|
* @param NewState: new state of the specified peripheral reset.
|
881 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
882 |
|
|
* @retval None
|
883 |
|
|
*/
|
884 |
|
|
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
885 |
|
|
{
|
886 |
|
|
/* Check the parameters */
|
887 |
|
|
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
|
888 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
889 |
|
|
|
890 |
|
|
if (NewState != DISABLE)
|
891 |
|
|
{
|
892 |
|
|
RCC->APB2RSTR |= RCC_APB2Periph;
|
893 |
|
|
}
|
894 |
|
|
else
|
895 |
|
|
{
|
896 |
|
|
RCC->APB2RSTR &= ~RCC_APB2Periph;
|
897 |
|
|
}
|
898 |
|
|
}
|
899 |
|
|
|
900 |
|
|
/**
|
901 |
|
|
* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
|
902 |
|
|
* @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
|
903 |
|
|
* This parameter can be any combination of the following values:
|
904 |
|
|
* @arg RCC_APB1Periph_TIM2
|
905 |
|
|
* @arg RCC_APB1Periph_TIM3
|
906 |
|
|
* @arg RCC_APB1Periph_TIM4
|
907 |
|
|
* @arg RCC_APB1Periph_TIM6
|
908 |
|
|
* @arg RCC_APB1Periph_TIM7
|
909 |
|
|
* @arg RCC_APB1Periph_LCD
|
910 |
|
|
* @arg RCC_APB1Periph_WWDG
|
911 |
|
|
* @arg RCC_APB1Periph_SPI2
|
912 |
|
|
* @arg RCC_APB1Periph_USART2
|
913 |
|
|
* @arg RCC_APB1Periph_USART3
|
914 |
|
|
* @arg RCC_APB1Periph_I2C1
|
915 |
|
|
* @arg RCC_APB1Periph_I2C2
|
916 |
|
|
* @arg RCC_APB1Periph_USB
|
917 |
|
|
* @arg RCC_APB1Periph_PWR
|
918 |
|
|
* @arg RCC_APB1Periph_DAC
|
919 |
|
|
* @arg RCC_APB1Periph_COMP
|
920 |
|
|
* @param NewState: new state of the specified peripheral clock.
|
921 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
922 |
|
|
* @retval None
|
923 |
|
|
*/
|
924 |
|
|
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
925 |
|
|
{
|
926 |
|
|
/* Check the parameters */
|
927 |
|
|
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
|
928 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
929 |
|
|
|
930 |
|
|
if (NewState != DISABLE)
|
931 |
|
|
{
|
932 |
|
|
RCC->APB1RSTR |= RCC_APB1Periph;
|
933 |
|
|
}
|
934 |
|
|
else
|
935 |
|
|
{
|
936 |
|
|
RCC->APB1RSTR &= ~RCC_APB1Periph;
|
937 |
|
|
}
|
938 |
|
|
}
|
939 |
|
|
|
940 |
|
|
/**
|
941 |
|
|
* @brief Enables or disables the AHB peripheral clock during Low Power (SLEEP) mode.
|
942 |
|
|
* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
|
943 |
|
|
* This parameter can be any combination of the following values:
|
944 |
|
|
* @arg RCC_AHBPeriph_GPIOA
|
945 |
|
|
* @arg RCC_AHBPeriph_GPIOB
|
946 |
|
|
* @arg RCC_AHBPeriph_GPIOC
|
947 |
|
|
* @arg RCC_AHBPeriph_GPIOD
|
948 |
|
|
* @arg RCC_AHBPeriph_GPIOE
|
949 |
|
|
* @arg RCC_AHBPeriph_GPIOH
|
950 |
|
|
* @arg RCC_AHBPeriph_CRC
|
951 |
|
|
* @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
|
952 |
|
|
* @arg RCC_AHBPeriph_SRAM
|
953 |
|
|
* @arg RCC_AHBPeriph_DMA1
|
954 |
|
|
* @param NewState: new state of the specified peripheral clock.
|
955 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
956 |
|
|
* @retval None
|
957 |
|
|
*/
|
958 |
|
|
void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
|
959 |
|
|
{
|
960 |
|
|
/* Check the parameters */
|
961 |
|
|
assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));
|
962 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
963 |
|
|
|
964 |
|
|
if (NewState != DISABLE)
|
965 |
|
|
{
|
966 |
|
|
RCC->AHBLPENR |= RCC_AHBPeriph;
|
967 |
|
|
}
|
968 |
|
|
else
|
969 |
|
|
{
|
970 |
|
|
RCC->AHBLPENR &= ~RCC_AHBPeriph;
|
971 |
|
|
}
|
972 |
|
|
}
|
973 |
|
|
|
974 |
|
|
/**
|
975 |
|
|
* @brief Enables or disables the APB2 peripheral clock during Low Power (SLEEP) mode.
|
976 |
|
|
* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
|
977 |
|
|
* This parameter can be any combination of the following values:
|
978 |
|
|
* @arg RCC_APB2Periph_SYSCFG
|
979 |
|
|
* @arg RCC_APB2Periph_TIM9
|
980 |
|
|
* @arg RCC_APB2Periph_TIM10
|
981 |
|
|
* @arg RCC_APB2Periph_TIM11
|
982 |
|
|
* @arg RCC_APB2Periph_ADC1
|
983 |
|
|
* @arg RCC_APB2Periph_SPI1
|
984 |
|
|
* @arg RCC_APB2Periph_USART1
|
985 |
|
|
* @param NewState: new state of the specified peripheral clock.
|
986 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
987 |
|
|
* @retval None
|
988 |
|
|
*/
|
989 |
|
|
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
990 |
|
|
{
|
991 |
|
|
/* Check the parameters */
|
992 |
|
|
assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
|
993 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
994 |
|
|
|
995 |
|
|
if (NewState != DISABLE)
|
996 |
|
|
{
|
997 |
|
|
RCC->APB2LPENR |= RCC_APB2Periph;
|
998 |
|
|
}
|
999 |
|
|
else
|
1000 |
|
|
{
|
1001 |
|
|
RCC->APB2LPENR &= ~RCC_APB2Periph;
|
1002 |
|
|
}
|
1003 |
|
|
}
|
1004 |
|
|
|
1005 |
|
|
/**
|
1006 |
|
|
* @brief Enables or disables the APB1 peripheral clock during Low Power (SLEEP) mode.
|
1007 |
|
|
* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
|
1008 |
|
|
* This parameter can be any combination of the following values:
|
1009 |
|
|
* @arg RCC_APB1Periph_TIM2
|
1010 |
|
|
* @arg RCC_APB1Periph_TIM3
|
1011 |
|
|
* @arg RCC_APB1Periph_TIM4
|
1012 |
|
|
* @arg RCC_APB1Periph_TIM6
|
1013 |
|
|
* @arg RCC_APB1Periph_TIM7
|
1014 |
|
|
* @arg RCC_APB1Periph_LCD
|
1015 |
|
|
* @arg RCC_APB1Periph_WWDG
|
1016 |
|
|
* @arg RCC_APB1Periph_SPI2
|
1017 |
|
|
* @arg RCC_APB1Periph_USART2
|
1018 |
|
|
* @arg RCC_APB1Periph_USART3
|
1019 |
|
|
* @arg RCC_APB1Periph_I2C1
|
1020 |
|
|
* @arg RCC_APB1Periph_I2C2
|
1021 |
|
|
* @arg RCC_APB1Periph_USB
|
1022 |
|
|
* @arg RCC_APB1Periph_PWR
|
1023 |
|
|
* @arg RCC_APB1Periph_DAC
|
1024 |
|
|
* @arg RCC_APB1Periph_COMP
|
1025 |
|
|
* @param NewState: new state of the specified peripheral clock.
|
1026 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1027 |
|
|
* @retval None
|
1028 |
|
|
*/
|
1029 |
|
|
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
1030 |
|
|
{
|
1031 |
|
|
/* Check the parameters */
|
1032 |
|
|
assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
|
1033 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1034 |
|
|
|
1035 |
|
|
if (NewState != DISABLE)
|
1036 |
|
|
{
|
1037 |
|
|
RCC->APB1LPENR |= RCC_APB1Periph;
|
1038 |
|
|
}
|
1039 |
|
|
else
|
1040 |
|
|
{
|
1041 |
|
|
RCC->APB1LPENR &= ~RCC_APB1Periph;
|
1042 |
|
|
}
|
1043 |
|
|
}
|
1044 |
|
|
|
1045 |
|
|
/**
|
1046 |
|
|
* @brief Enables or disables the Clock Security System.
|
1047 |
|
|
* @param NewState: new state of the Clock Security System..
|
1048 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1049 |
|
|
* @retval None
|
1050 |
|
|
*/
|
1051 |
|
|
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
|
1052 |
|
|
{
|
1053 |
|
|
/* Check the parameters */
|
1054 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1055 |
|
|
|
1056 |
|
|
*(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
|
1057 |
|
|
}
|
1058 |
|
|
|
1059 |
|
|
/**
|
1060 |
|
|
* @brief Selects the clock source to output on MCO pin.
|
1061 |
|
|
* @param RCC_MCOSource: specifies the clock source to output.
|
1062 |
|
|
* This parameter can be one of the following values:
|
1063 |
|
|
* @arg RCC_MCOSource_NoClock: No clock selected
|
1064 |
|
|
* @arg RCC_MCOSource_SYSCLK: System clock selected
|
1065 |
|
|
* @arg RCC_MCOSource_HSI: HSI oscillator clock selected
|
1066 |
|
|
* @arg RCC_MCOSource_MSI: MSI oscillator clock selected
|
1067 |
|
|
* @arg RCC_MCOSource_HSE: HSE oscillator clock selected
|
1068 |
|
|
* @arg RCC_MCOSource_PLLCLK: PLL clock selected
|
1069 |
|
|
* @arg RCC_MCOSource_LSI: LSI clock selected
|
1070 |
|
|
* @arg RCC_MCOSource_LSE: LSE clock selected
|
1071 |
|
|
* @param RCC_MCODiv: specifies the MCO prescaler.
|
1072 |
|
|
* This parameter can be one of the following values:
|
1073 |
|
|
* @arg RCC_MCODiv_1: no division applied to MCO clock
|
1074 |
|
|
* @arg RCC_MCODiv_2: division by 2 applied to MCO clock
|
1075 |
|
|
* @arg RCC_MCODiv_4: division by 4 applied to MCO clock
|
1076 |
|
|
* @arg RCC_MCODiv_8: division by 8 applied to MCO clock
|
1077 |
|
|
* @arg RCC_MCODiv_16: division by 16 applied to MCO clock
|
1078 |
|
|
* @retval None
|
1079 |
|
|
*/
|
1080 |
|
|
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
|
1081 |
|
|
{
|
1082 |
|
|
/* Check the parameters */
|
1083 |
|
|
assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
|
1084 |
|
|
assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));
|
1085 |
|
|
|
1086 |
|
|
/* Select MCO clock source and prescaler */
|
1087 |
|
|
*(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv;
|
1088 |
|
|
}
|
1089 |
|
|
|
1090 |
|
|
/**
|
1091 |
|
|
* @brief Checks whether the specified RCC flag is set or not.
|
1092 |
|
|
* @param RCC_FLAG: specifies the flag to check.
|
1093 |
|
|
* This parameter can be one of the following values:
|
1094 |
|
|
* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
|
1095 |
|
|
* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
|
1096 |
|
|
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
|
1097 |
|
|
* @arg RCC_FLAG_PLLRDY: PLL clock ready
|
1098 |
|
|
* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
|
1099 |
|
|
* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
|
1100 |
|
|
* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
|
1101 |
|
|
* @arg RCC_FLAG_PINRST: Pin reset
|
1102 |
|
|
* @arg RCC_FLAG_PORRST: POR/PDR reset
|
1103 |
|
|
* @arg RCC_FLAG_SFTRST: Software reset
|
1104 |
|
|
* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
|
1105 |
|
|
* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
|
1106 |
|
|
* @arg RCC_FLAG_LPWRRST: Low Power reset
|
1107 |
|
|
* @retval The new state of RCC_FLAG (SET or RESET).
|
1108 |
|
|
*/
|
1109 |
|
|
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
|
1110 |
|
|
{
|
1111 |
|
|
uint32_t tmp = 0;
|
1112 |
|
|
uint32_t statusreg = 0;
|
1113 |
|
|
FlagStatus bitstatus = RESET;
|
1114 |
|
|
|
1115 |
|
|
/* Check the parameters */
|
1116 |
|
|
assert_param(IS_RCC_FLAG(RCC_FLAG));
|
1117 |
|
|
|
1118 |
|
|
/* Get the RCC register index */
|
1119 |
|
|
tmp = RCC_FLAG >> 5;
|
1120 |
|
|
|
1121 |
|
|
if (tmp == 1) /* The flag to check is in CR register */
|
1122 |
|
|
{
|
1123 |
|
|
statusreg = RCC->CR;
|
1124 |
|
|
}
|
1125 |
|
|
else /* The flag to check is in CSR register (tmp == 2) */
|
1126 |
|
|
{
|
1127 |
|
|
statusreg = RCC->CSR;
|
1128 |
|
|
}
|
1129 |
|
|
|
1130 |
|
|
/* Get the flag position */
|
1131 |
|
|
tmp = RCC_FLAG & FLAG_MASK;
|
1132 |
|
|
|
1133 |
|
|
if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
|
1134 |
|
|
{
|
1135 |
|
|
bitstatus = SET;
|
1136 |
|
|
}
|
1137 |
|
|
else
|
1138 |
|
|
{
|
1139 |
|
|
bitstatus = RESET;
|
1140 |
|
|
}
|
1141 |
|
|
/* Return the flag status */
|
1142 |
|
|
return bitstatus;
|
1143 |
|
|
}
|
1144 |
|
|
|
1145 |
|
|
/**
|
1146 |
|
|
* @brief Clears the RCC reset flags.
|
1147 |
|
|
* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
|
1148 |
|
|
* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
|
1149 |
|
|
* @param None
|
1150 |
|
|
* @retval None
|
1151 |
|
|
*/
|
1152 |
|
|
void RCC_ClearFlag(void)
|
1153 |
|
|
{
|
1154 |
|
|
/* Set RMVF bit to clear the reset flags */
|
1155 |
|
|
RCC->CSR |= RCC_CSR_RMVF;
|
1156 |
|
|
}
|
1157 |
|
|
|
1158 |
|
|
/**
|
1159 |
|
|
* @brief Checks whether the specified RCC interrupt has occurred or not.
|
1160 |
|
|
* @param RCC_IT: specifies the RCC interrupt source to check.
|
1161 |
|
|
* This parameter can be one of the following values:
|
1162 |
|
|
* @arg RCC_IT_LSIRDY: LSI ready interrupt
|
1163 |
|
|
* @arg RCC_IT_LSERDY: LSE ready interrupt
|
1164 |
|
|
* @arg RCC_IT_HSIRDY: HSI ready interrupt
|
1165 |
|
|
* @arg RCC_IT_HSERDY: HSE ready interrupt
|
1166 |
|
|
* @arg RCC_IT_PLLRDY: PLL ready interrupt
|
1167 |
|
|
* @arg RCC_IT_MSIRDY: MSI ready interrupt
|
1168 |
|
|
* @arg RCC_IT_CSS: Clock Security System interrupt
|
1169 |
|
|
* @retval The new state of RCC_IT (SET or RESET).
|
1170 |
|
|
*/
|
1171 |
|
|
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
|
1172 |
|
|
{
|
1173 |
|
|
ITStatus bitstatus = RESET;
|
1174 |
|
|
/* Check the parameters */
|
1175 |
|
|
assert_param(IS_RCC_GET_IT(RCC_IT));
|
1176 |
|
|
|
1177 |
|
|
/* Check the status of the specified RCC interrupt */
|
1178 |
|
|
if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
|
1179 |
|
|
{
|
1180 |
|
|
bitstatus = SET;
|
1181 |
|
|
}
|
1182 |
|
|
else
|
1183 |
|
|
{
|
1184 |
|
|
bitstatus = RESET;
|
1185 |
|
|
}
|
1186 |
|
|
/* Return the RCC_IT status */
|
1187 |
|
|
return bitstatus;
|
1188 |
|
|
}
|
1189 |
|
|
|
1190 |
|
|
/**
|
1191 |
|
|
* @brief Clears the RCC's interrupt pending bits.
|
1192 |
|
|
* @param RCC_IT: specifies the interrupt pending bit to clear.
|
1193 |
|
|
* This parameter can be any combination of the following values:
|
1194 |
|
|
* @arg RCC_IT_LSIRDY: LSI ready interrupt
|
1195 |
|
|
* @arg RCC_IT_LSERDY: LSE ready interrupt
|
1196 |
|
|
* @arg RCC_IT_HSIRDY: HSI ready interrupt
|
1197 |
|
|
* @arg RCC_IT_HSERDY: HSE ready interrupt
|
1198 |
|
|
* @arg RCC_IT_PLLRDY: PLL ready interrupt
|
1199 |
|
|
* @arg RCC_IT_MSIRDY: MSI ready interrupt
|
1200 |
|
|
* @arg RCC_IT_CSS: Clock Security System interrupt
|
1201 |
|
|
* @retval None
|
1202 |
|
|
*/
|
1203 |
|
|
void RCC_ClearITPendingBit(uint8_t RCC_IT)
|
1204 |
|
|
{
|
1205 |
|
|
/* Check the parameters */
|
1206 |
|
|
assert_param(IS_RCC_CLEAR_IT(RCC_IT));
|
1207 |
|
|
|
1208 |
|
|
/* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
|
1209 |
|
|
pending bits */
|
1210 |
|
|
*(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
|
1211 |
|
|
}
|
1212 |
|
|
|
1213 |
|
|
/**
|
1214 |
|
|
* @}
|
1215 |
|
|
*/
|
1216 |
|
|
|
1217 |
|
|
/**
|
1218 |
|
|
* @}
|
1219 |
|
|
*/
|
1220 |
|
|
|
1221 |
|
|
/**
|
1222 |
|
|
* @}
|
1223 |
|
|
*/
|
1224 |
|
|
|
1225 |
|
|
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|