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jeremybenn |
/**
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******************************************************************************
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* @file stm32l1xx_tim.c
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* @author MCD Application Team
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* @version V1.0.0RC1
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* @date 07/02/2010
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* @brief This file provides all the TIM firmware functions.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx_tim.h"
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#include "stm32l1xx_rcc.h"
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/** @addtogroup STM32L1xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup TIM
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* @brief TIM driver modules
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* @{
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*/
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/** @defgroup TIM_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Defines
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* @{
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*/
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/* ---------------------- TIM registers bit mask ------------------------ */
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#define SMCR_ETR_MASK ((uint16_t)0x00FF)
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#define CCMR_OFFSET ((uint16_t)0x0018)
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#define CCER_CCE_SET ((uint16_t)0x0001)
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_FunctionPrototypes
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* @{
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*/
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static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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uint16_t TIM_ICFilter);
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static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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uint16_t TIM_ICFilter);
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static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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uint16_t TIM_ICFilter);
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static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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uint16_t TIM_ICFilter);
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Functions
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* @{
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*/
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/**
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* @brief Deinitializes the TIMx peripheral registers to their default reset values.
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* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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* @retval None
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*
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*/
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void TIM_DeInit(TIM_TypeDef* TIMx)
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{
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/* Check the parameters */
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assert_param(IS_TIM_ALL_PERIPH(TIMx));
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if (TIMx == TIM2)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
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}
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else if (TIMx == TIM3)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
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}
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else if (TIMx == TIM4)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
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}
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else if (TIMx == TIM6)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
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}
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else if (TIMx == TIM7)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
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}
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else if (TIMx == TIM9)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
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}
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else if (TIMx == TIM10)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
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}
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else
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{
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if (TIMx == TIM11)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
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}
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}
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}
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/**
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* @brief Initializes the TIMx Time Base Unit peripheral according to
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* the specified parameters in the TIM_TimeBaseInitStruct.
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* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
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* structure that contains the configuration information for
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* the specified TIM peripheral.
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* @retval None
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*/
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void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
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{
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uint16_t tmpcr1 = 0;
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/* Check the parameters */
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assert_param(IS_TIM_ALL_PERIPH(TIMx));
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assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
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assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
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tmpcr1 = TIMx->CR1;
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if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4))
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{
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/* Select the Counter Mode */
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tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
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tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
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}
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if(((TIMx) != TIM6) && ((TIMx) != TIM7))
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{
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/* Set the clock division */
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tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
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tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
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}
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TIMx->CR1 = tmpcr1;
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/* Set the Autoreload value */
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TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
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/* Set the Prescaler value */
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TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
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/* Generate an update event to reload the Prescaler value immediatly */
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TIMx->EGR = TIM_PSCReloadMode_Immediate;
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}
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/**
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* @brief Initializes the TIMx Channel1 according to the specified
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* parameters in the TIM_OCInitStruct.
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* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
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* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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* that contains the configuration information for the specified TIM
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* peripheral.
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* @retval None
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*/
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void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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{
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uint16_t tmpccmrx = 0, tmpccer = 0;
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/* Check the parameters */
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assert_param(IS_TIM_23491011_PERIPH(TIMx));
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assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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/* Disable the Channel 1: Reset the CC1E Bit */
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TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
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/* Get the TIMx CCER register value */
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tmpccer = TIMx->CCER;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = TIMx->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
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tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
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/* Select the Output Compare Mode */
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tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
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/* Reset the Output Polarity level */
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tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
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/* Set the Output Compare Polarity */
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tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
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/* Set the Output State */
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tmpccer |= TIM_OCInitStruct->TIM_OutputState;
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/* Set the Capture Compare Register value */
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TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
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/* Write to TIMx CCMR1 */
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TIMx->CCMR1 = tmpccmrx;
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/* Write to TIMx CCER */
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TIMx->CCER = tmpccer;
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}
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/**
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* @brief Initializes the TIMx Channel2 according to the specified
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* parameters in the TIM_OCInitStruct.
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* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
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* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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* that contains the configuration information for the specified TIM
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* peripheral.
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* @retval None
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*/
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void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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{
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uint16_t tmpccmrx = 0, tmpccer = 0;
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/* Check the parameters */
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assert_param(IS_TIM_2349_PERIPH(TIMx));
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assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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/* Disable the Channel 2: Reset the CC2E Bit */
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TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
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/* Get the TIMx CCER register value */
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tmpccer = TIMx->CCER;
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/* Get the TIMx CCMR1 register value */
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tmpccmrx = TIMx->CCMR1;
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/* Reset the Output Compare Mode Bits */
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tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
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/* Select the Output Compare Mode */
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tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
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/* Reset the Output Polarity level */
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tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
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/* Set the Output Compare Polarity */
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tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
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/* Set the Output State */
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tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
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/* Set the Capture Compare Register value */
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TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
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/* Write to TIMx CCMR1 */
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TIMx->CCMR1 = tmpccmrx;
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/* Write to TIMx CCER */
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TIMx->CCER = tmpccer;
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}
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/**
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* @brief Initializes the TIMx Channel3 according to the specified
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* parameters in the TIM_OCInitStruct.
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* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
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* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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* that contains the configuration information for the specified TIM
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* peripheral.
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* @retval None
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*/
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void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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{
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uint16_t tmpccmrx = 0, tmpccer = 0;
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/* Check the parameters */
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assert_param(IS_TIM_234_PERIPH(TIMx));
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assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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/* Disable the Channel 2: Reset the CC2E Bit */
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TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
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/* Get the TIMx CCER register value */
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tmpccer = TIMx->CCER;
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348 |
|
|
/* Get the TIMx CCMR2 register value */
|
349 |
|
|
tmpccmrx = TIMx->CCMR2;
|
350 |
|
|
|
351 |
|
|
/* Reset the Output Compare Mode Bits */
|
352 |
|
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
|
353 |
|
|
|
354 |
|
|
/* Select the Output Compare Mode */
|
355 |
|
|
tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
|
356 |
|
|
|
357 |
|
|
/* Reset the Output Polarity level */
|
358 |
|
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
|
359 |
|
|
/* Set the Output Compare Polarity */
|
360 |
|
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
|
361 |
|
|
|
362 |
|
|
/* Set the Output State */
|
363 |
|
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
|
364 |
|
|
|
365 |
|
|
/* Set the Capture Compare Register value */
|
366 |
|
|
TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
|
367 |
|
|
|
368 |
|
|
/* Write to TIMx CCMR2 */
|
369 |
|
|
TIMx->CCMR2 = tmpccmrx;
|
370 |
|
|
|
371 |
|
|
/* Write to TIMx CCER */
|
372 |
|
|
TIMx->CCER = tmpccer;
|
373 |
|
|
}
|
374 |
|
|
|
375 |
|
|
/**
|
376 |
|
|
* @brief Initializes the TIMx Channel4 according to the specified
|
377 |
|
|
* parameters in the TIM_OCInitStruct.
|
378 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
379 |
|
|
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
|
380 |
|
|
* that contains the configuration information for the specified TIM
|
381 |
|
|
* peripheral.
|
382 |
|
|
* @retval None
|
383 |
|
|
*/
|
384 |
|
|
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
|
385 |
|
|
{
|
386 |
|
|
uint16_t tmpccmrx = 0, tmpccer = 0;
|
387 |
|
|
|
388 |
|
|
/* Check the parameters */
|
389 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
390 |
|
|
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
|
391 |
|
|
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
|
392 |
|
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
|
393 |
|
|
|
394 |
|
|
/* Disable the Channel 2: Reset the CC4E Bit */
|
395 |
|
|
TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
|
396 |
|
|
|
397 |
|
|
/* Get the TIMx CCER register value */
|
398 |
|
|
tmpccer = TIMx->CCER;
|
399 |
|
|
|
400 |
|
|
/* Get the TIMx CCMR2 register value */
|
401 |
|
|
tmpccmrx = TIMx->CCMR2;
|
402 |
|
|
|
403 |
|
|
/* Reset the Output Compare Mode Bits */
|
404 |
|
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
|
405 |
|
|
|
406 |
|
|
/* Select the Output Compare Mode */
|
407 |
|
|
tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
|
408 |
|
|
|
409 |
|
|
/* Reset the Output Polarity level */
|
410 |
|
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
|
411 |
|
|
/* Set the Output Compare Polarity */
|
412 |
|
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
|
413 |
|
|
|
414 |
|
|
/* Set the Output State */
|
415 |
|
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
|
416 |
|
|
|
417 |
|
|
/* Set the Capture Compare Register value */
|
418 |
|
|
TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
|
419 |
|
|
|
420 |
|
|
/* Write to TIMx CCMR2 */
|
421 |
|
|
TIMx->CCMR2 = tmpccmrx;
|
422 |
|
|
|
423 |
|
|
/* Write to TIMx CCER */
|
424 |
|
|
TIMx->CCER = tmpccer;
|
425 |
|
|
}
|
426 |
|
|
|
427 |
|
|
/**
|
428 |
|
|
* @brief Initializes the TIM peripheral according to the specified
|
429 |
|
|
* parameters in the TIM_ICInitStruct.
|
430 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
431 |
|
|
* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
|
432 |
|
|
* that contains the configuration information for the specified TIM
|
433 |
|
|
* peripheral.
|
434 |
|
|
* @retval None
|
435 |
|
|
*/
|
436 |
|
|
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
|
437 |
|
|
{
|
438 |
|
|
/* Check the parameters */
|
439 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
440 |
|
|
assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
|
441 |
|
|
assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
|
442 |
|
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
|
443 |
|
|
assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
|
444 |
|
|
|
445 |
|
|
if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
|
446 |
|
|
{
|
447 |
|
|
/* TI1 Configuration */
|
448 |
|
|
TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
|
449 |
|
|
TIM_ICInitStruct->TIM_ICSelection,
|
450 |
|
|
TIM_ICInitStruct->TIM_ICFilter);
|
451 |
|
|
/* Set the Input Capture Prescaler value */
|
452 |
|
|
TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
453 |
|
|
}
|
454 |
|
|
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
|
455 |
|
|
{
|
456 |
|
|
/* TI2 Configuration */
|
457 |
|
|
TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
|
458 |
|
|
TIM_ICInitStruct->TIM_ICSelection,
|
459 |
|
|
TIM_ICInitStruct->TIM_ICFilter);
|
460 |
|
|
/* Set the Input Capture Prescaler value */
|
461 |
|
|
TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
462 |
|
|
}
|
463 |
|
|
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
|
464 |
|
|
{
|
465 |
|
|
/* TI3 Configuration */
|
466 |
|
|
TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
|
467 |
|
|
TIM_ICInitStruct->TIM_ICSelection,
|
468 |
|
|
TIM_ICInitStruct->TIM_ICFilter);
|
469 |
|
|
/* Set the Input Capture Prescaler value */
|
470 |
|
|
TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
471 |
|
|
}
|
472 |
|
|
else
|
473 |
|
|
{
|
474 |
|
|
/* TI4 Configuration */
|
475 |
|
|
TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
|
476 |
|
|
TIM_ICInitStruct->TIM_ICSelection,
|
477 |
|
|
TIM_ICInitStruct->TIM_ICFilter);
|
478 |
|
|
/* Set the Input Capture Prescaler value */
|
479 |
|
|
TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
480 |
|
|
}
|
481 |
|
|
}
|
482 |
|
|
|
483 |
|
|
/**
|
484 |
|
|
* @brief Configures the TIM peripheral according to the specified
|
485 |
|
|
* parameters in the TIM_ICInitStruct to measure an external PWM signal.
|
486 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
487 |
|
|
* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
|
488 |
|
|
* that contains the configuration information for the specified TIM
|
489 |
|
|
* peripheral.
|
490 |
|
|
* @retval None
|
491 |
|
|
*/
|
492 |
|
|
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
|
493 |
|
|
{
|
494 |
|
|
uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
|
495 |
|
|
uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
|
496 |
|
|
/* Check the parameters */
|
497 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
498 |
|
|
/* Select the Opposite Input Polarity */
|
499 |
|
|
if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
|
500 |
|
|
{
|
501 |
|
|
icoppositepolarity = TIM_ICPolarity_Falling;
|
502 |
|
|
}
|
503 |
|
|
else
|
504 |
|
|
{
|
505 |
|
|
icoppositepolarity = TIM_ICPolarity_Rising;
|
506 |
|
|
}
|
507 |
|
|
/* Select the Opposite Input */
|
508 |
|
|
if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
|
509 |
|
|
{
|
510 |
|
|
icoppositeselection = TIM_ICSelection_IndirectTI;
|
511 |
|
|
}
|
512 |
|
|
else
|
513 |
|
|
{
|
514 |
|
|
icoppositeselection = TIM_ICSelection_DirectTI;
|
515 |
|
|
}
|
516 |
|
|
if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
|
517 |
|
|
{
|
518 |
|
|
/* TI1 Configuration */
|
519 |
|
|
TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
|
520 |
|
|
TIM_ICInitStruct->TIM_ICFilter);
|
521 |
|
|
/* Set the Input Capture Prescaler value */
|
522 |
|
|
TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
523 |
|
|
/* TI2 Configuration */
|
524 |
|
|
TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
|
525 |
|
|
/* Set the Input Capture Prescaler value */
|
526 |
|
|
TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
527 |
|
|
}
|
528 |
|
|
else
|
529 |
|
|
{
|
530 |
|
|
/* TI2 Configuration */
|
531 |
|
|
TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
|
532 |
|
|
TIM_ICInitStruct->TIM_ICFilter);
|
533 |
|
|
/* Set the Input Capture Prescaler value */
|
534 |
|
|
TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
535 |
|
|
/* TI1 Configuration */
|
536 |
|
|
TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
|
537 |
|
|
/* Set the Input Capture Prescaler value */
|
538 |
|
|
TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
539 |
|
|
}
|
540 |
|
|
}
|
541 |
|
|
|
542 |
|
|
/**
|
543 |
|
|
* @brief Fills each TIM_TimeBaseInitStruct member with its default value.
|
544 |
|
|
* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
|
545 |
|
|
* structure which will be initialized.
|
546 |
|
|
* @retval None
|
547 |
|
|
*/
|
548 |
|
|
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
|
549 |
|
|
{
|
550 |
|
|
/* Set the default configuration */
|
551 |
|
|
TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
|
552 |
|
|
TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
|
553 |
|
|
TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
|
554 |
|
|
TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
|
555 |
|
|
}
|
556 |
|
|
|
557 |
|
|
/**
|
558 |
|
|
* @brief Fills each TIM_OCInitStruct member with its default value.
|
559 |
|
|
* @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
|
560 |
|
|
* be initialized.
|
561 |
|
|
* @retval None
|
562 |
|
|
*/
|
563 |
|
|
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
|
564 |
|
|
{
|
565 |
|
|
/* Set the default configuration */
|
566 |
|
|
TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
|
567 |
|
|
TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
|
568 |
|
|
TIM_OCInitStruct->TIM_Pulse = 0x0000;
|
569 |
|
|
TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
|
570 |
|
|
}
|
571 |
|
|
|
572 |
|
|
/**
|
573 |
|
|
* @brief Fills each TIM_ICInitStruct member with its default value.
|
574 |
|
|
* @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
|
575 |
|
|
* be initialized.
|
576 |
|
|
* @retval None
|
577 |
|
|
*/
|
578 |
|
|
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
|
579 |
|
|
{
|
580 |
|
|
/* Set the default configuration */
|
581 |
|
|
TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
|
582 |
|
|
TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
|
583 |
|
|
TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
|
584 |
|
|
TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
|
585 |
|
|
TIM_ICInitStruct->TIM_ICFilter = 0x00;
|
586 |
|
|
}
|
587 |
|
|
|
588 |
|
|
/**
|
589 |
|
|
* @brief Enables or disables the specified TIM peripheral.
|
590 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.
|
591 |
|
|
* @param NewState: new state of the TIMx peripheral.
|
592 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
593 |
|
|
* @retval None
|
594 |
|
|
*/
|
595 |
|
|
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
|
596 |
|
|
{
|
597 |
|
|
/* Check the parameters */
|
598 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
599 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
600 |
|
|
|
601 |
|
|
if (NewState != DISABLE)
|
602 |
|
|
{
|
603 |
|
|
/* Enable the TIM Counter */
|
604 |
|
|
TIMx->CR1 |= TIM_CR1_CEN;
|
605 |
|
|
}
|
606 |
|
|
else
|
607 |
|
|
{
|
608 |
|
|
/* Disable the TIM Counter */
|
609 |
|
|
TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
|
610 |
|
|
}
|
611 |
|
|
}
|
612 |
|
|
|
613 |
|
|
/**
|
614 |
|
|
* @brief Enables or disables the specified TIM interrupts.
|
615 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.
|
616 |
|
|
* @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
|
617 |
|
|
* This parameter can be any combination of the following values:
|
618 |
|
|
* @arg TIM_IT_Update: TIM update Interrupt source
|
619 |
|
|
* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
|
620 |
|
|
* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
|
621 |
|
|
* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
|
622 |
|
|
* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
|
623 |
|
|
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
|
624 |
|
|
* @note
|
625 |
|
|
* - TIM6 and TIM7 can only generate an update interrupt.
|
626 |
|
|
* - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11
|
627 |
|
|
* - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9.
|
628 |
|
|
* @param NewState: new state of the TIM interrupts.
|
629 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
630 |
|
|
* @retval None
|
631 |
|
|
*/
|
632 |
|
|
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
|
633 |
|
|
{
|
634 |
|
|
/* Check the parameters */
|
635 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
636 |
|
|
assert_param(IS_TIM_IT(TIM_IT));
|
637 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
638 |
|
|
|
639 |
|
|
if (NewState != DISABLE)
|
640 |
|
|
{
|
641 |
|
|
/* Enable the Interrupt sources */
|
642 |
|
|
TIMx->DIER |= TIM_IT;
|
643 |
|
|
}
|
644 |
|
|
else
|
645 |
|
|
{
|
646 |
|
|
/* Disable the Interrupt sources */
|
647 |
|
|
TIMx->DIER &= (uint16_t)~TIM_IT;
|
648 |
|
|
}
|
649 |
|
|
}
|
650 |
|
|
|
651 |
|
|
/**
|
652 |
|
|
* @brief Configures the TIMx event to be generate by software.
|
653 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
654 |
|
|
* @param TIM_EventSource: specifies the event source.
|
655 |
|
|
* This parameter can be one or more of the following values:
|
656 |
|
|
* @arg TIM_EventSource_Update: Timer update Event source
|
657 |
|
|
* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
|
658 |
|
|
* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
|
659 |
|
|
* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
|
660 |
|
|
* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
|
661 |
|
|
* @arg TIM_EventSource_Trigger: Timer Trigger Event source
|
662 |
|
|
* @note
|
663 |
|
|
* - TIM6 and TIM7 can only generate an update event.
|
664 |
|
|
* - TIM9 can only generate an update event, Capture Compare 1 event,
|
665 |
|
|
* Capture Compare 2 event and TIM_EventSource_Trigger.
|
666 |
|
|
* - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event.
|
667 |
|
|
* @retval None
|
668 |
|
|
*/
|
669 |
|
|
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
|
670 |
|
|
{
|
671 |
|
|
/* Check the parameters */
|
672 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
673 |
|
|
assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
|
674 |
|
|
/* Set the event sources */
|
675 |
|
|
TIMx->EGR = TIM_EventSource;
|
676 |
|
|
}
|
677 |
|
|
|
678 |
|
|
/**
|
679 |
|
|
* @brief Configures the TIMx’s DMA interface.
|
680 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
681 |
|
|
* @param TIM_DMABase: DMA Base address.
|
682 |
|
|
* This parameter can be one of the following values:
|
683 |
|
|
* @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
|
684 |
|
|
* TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,
|
685 |
|
|
* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
|
686 |
|
|
* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
|
687 |
|
|
* TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3,
|
688 |
|
|
* TIM_DMABase_CCR4, TIM_DMABase_DCR.
|
689 |
|
|
* @param TIM_DMABurstLength: DMA Burst length.
|
690 |
|
|
* This parameter can be one value between:
|
691 |
|
|
* TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
|
692 |
|
|
* @retval None
|
693 |
|
|
*/
|
694 |
|
|
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
|
695 |
|
|
{
|
696 |
|
|
/* Check the parameters */
|
697 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
698 |
|
|
assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
|
699 |
|
|
assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
|
700 |
|
|
/* Set the DMA Base and the DMA Burst Length */
|
701 |
|
|
TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
|
702 |
|
|
}
|
703 |
|
|
|
704 |
|
|
/**
|
705 |
|
|
* @brief Enables or disables the TIMx’s DMA Requests.
|
706 |
|
|
* @param TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral.
|
707 |
|
|
* @param TIM_DMASource: specifies the DMA Request sources.
|
708 |
|
|
* This parameter can be any combination of the following values:
|
709 |
|
|
* @arg TIM_DMA_Update: TIM update Interrupt source
|
710 |
|
|
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
|
711 |
|
|
* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
|
712 |
|
|
* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
|
713 |
|
|
* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
|
714 |
|
|
* @arg TIM_DMA_Trigger: TIM Trigger DMA source
|
715 |
|
|
* @param NewState: new state of the DMA Request sources.
|
716 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
717 |
|
|
* @retval None
|
718 |
|
|
*/
|
719 |
|
|
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
|
720 |
|
|
{
|
721 |
|
|
/* Check the parameters */
|
722 |
|
|
assert_param(IS_TIM_23467_PERIPH(TIMx));
|
723 |
|
|
assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
|
724 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
725 |
|
|
|
726 |
|
|
if (NewState != DISABLE)
|
727 |
|
|
{
|
728 |
|
|
/* Enable the DMA sources */
|
729 |
|
|
TIMx->DIER |= TIM_DMASource;
|
730 |
|
|
}
|
731 |
|
|
else
|
732 |
|
|
{
|
733 |
|
|
/* Disable the DMA sources */
|
734 |
|
|
TIMx->DIER &= (uint16_t)~TIM_DMASource;
|
735 |
|
|
}
|
736 |
|
|
}
|
737 |
|
|
|
738 |
|
|
/**
|
739 |
|
|
* @brief Configures the TIMx interrnal Clock
|
740 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
741 |
|
|
* @retval None
|
742 |
|
|
*/
|
743 |
|
|
void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
|
744 |
|
|
{
|
745 |
|
|
/* Check the parameters */
|
746 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
747 |
|
|
/* Disable slave mode to clock the prescaler directly with the internal clock */
|
748 |
|
|
TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
|
749 |
|
|
}
|
750 |
|
|
|
751 |
|
|
/**
|
752 |
|
|
* @brief Configures the TIMx Internal Trigger as External Clock
|
753 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
754 |
|
|
* @param TIM_ITRSource: Trigger source.
|
755 |
|
|
* This parameter can be one of the following values:
|
756 |
|
|
* @param TIM_TS_ITR0: Internal Trigger 0
|
757 |
|
|
* @param TIM_TS_ITR1: Internal Trigger 1
|
758 |
|
|
* @param TIM_TS_ITR2: Internal Trigger 2
|
759 |
|
|
* @param TIM_TS_ITR3: Internal Trigger 3
|
760 |
|
|
* @retval None
|
761 |
|
|
*/
|
762 |
|
|
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
|
763 |
|
|
{
|
764 |
|
|
/* Check the parameters */
|
765 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
766 |
|
|
assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
|
767 |
|
|
/* Select the Internal Trigger */
|
768 |
|
|
TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
|
769 |
|
|
/* Select the External clock mode1 */
|
770 |
|
|
TIMx->SMCR |= TIM_SlaveMode_External1;
|
771 |
|
|
}
|
772 |
|
|
|
773 |
|
|
/**
|
774 |
|
|
* @brief Configures the TIMx Trigger as External Clock
|
775 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
776 |
|
|
* @param TIM_TIxExternalCLKSource: Trigger source.
|
777 |
|
|
* This parameter can be one of the following values:
|
778 |
|
|
* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
|
779 |
|
|
* @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
|
780 |
|
|
* @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
|
781 |
|
|
* @param TIM_ICPolarity: specifies the TIx Polarity.
|
782 |
|
|
* This parameter can be one of the following values:
|
783 |
|
|
* @arg TIM_ICPolarity_Rising
|
784 |
|
|
* @arg TIM_ICPolarity_Falling
|
785 |
|
|
* @param ICFilter : specifies the filter value.
|
786 |
|
|
* This parameter must be a value between 0x0 and 0xF.
|
787 |
|
|
* @retval None
|
788 |
|
|
*/
|
789 |
|
|
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
|
790 |
|
|
uint16_t TIM_ICPolarity, uint16_t ICFilter)
|
791 |
|
|
{
|
792 |
|
|
/* Check the parameters */
|
793 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
794 |
|
|
assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
|
795 |
|
|
assert_param(IS_TIM_IC_FILTER(ICFilter));
|
796 |
|
|
|
797 |
|
|
/* Configure the Timer Input Clock Source */
|
798 |
|
|
if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
|
799 |
|
|
{
|
800 |
|
|
TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
|
801 |
|
|
}
|
802 |
|
|
else
|
803 |
|
|
{
|
804 |
|
|
TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
|
805 |
|
|
}
|
806 |
|
|
/* Select the Trigger source */
|
807 |
|
|
TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
|
808 |
|
|
/* Select the External clock mode1 */
|
809 |
|
|
TIMx->SMCR |= TIM_SlaveMode_External1;
|
810 |
|
|
}
|
811 |
|
|
|
812 |
|
|
/**
|
813 |
|
|
* @brief Configures the External clock Mode1
|
814 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
815 |
|
|
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
816 |
|
|
* This parameter can be one of the following values:
|
817 |
|
|
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
818 |
|
|
* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
|
819 |
|
|
* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
|
820 |
|
|
* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
|
821 |
|
|
* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
822 |
|
|
* This parameter can be one of the following values:
|
823 |
|
|
* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
|
824 |
|
|
* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
|
825 |
|
|
* @param ExtTRGFilter: External Trigger Filter.
|
826 |
|
|
* This parameter must be a value between 0x00 and 0x0F
|
827 |
|
|
* @retval None
|
828 |
|
|
*/
|
829 |
|
|
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
830 |
|
|
uint16_t ExtTRGFilter)
|
831 |
|
|
{
|
832 |
|
|
uint16_t tmpsmcr = 0;
|
833 |
|
|
|
834 |
|
|
/* Check the parameters */
|
835 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
836 |
|
|
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
|
837 |
|
|
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
|
838 |
|
|
assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
|
839 |
|
|
|
840 |
|
|
/* Configure the ETR Clock source */
|
841 |
|
|
TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
|
842 |
|
|
|
843 |
|
|
/* Get the TIMx SMCR register value */
|
844 |
|
|
tmpsmcr = TIMx->SMCR;
|
845 |
|
|
/* Reset the SMS Bits */
|
846 |
|
|
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
|
847 |
|
|
/* Select the External clock mode1 */
|
848 |
|
|
tmpsmcr |= TIM_SlaveMode_External1;
|
849 |
|
|
/* Select the Trigger selection : ETRF */
|
850 |
|
|
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
|
851 |
|
|
tmpsmcr |= TIM_TS_ETRF;
|
852 |
|
|
/* Write to TIMx SMCR */
|
853 |
|
|
TIMx->SMCR = tmpsmcr;
|
854 |
|
|
}
|
855 |
|
|
|
856 |
|
|
/**
|
857 |
|
|
* @brief Configures the External clock Mode2
|
858 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
859 |
|
|
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
860 |
|
|
* This parameter can be one of the following values:
|
861 |
|
|
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
862 |
|
|
* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
|
863 |
|
|
* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
|
864 |
|
|
* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
|
865 |
|
|
* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
866 |
|
|
* This parameter can be one of the following values:
|
867 |
|
|
* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
|
868 |
|
|
* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
|
869 |
|
|
* @param ExtTRGFilter: External Trigger Filter.
|
870 |
|
|
* This parameter must be a value between 0x00 and 0x0F
|
871 |
|
|
* @retval None
|
872 |
|
|
*/
|
873 |
|
|
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
|
874 |
|
|
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
|
875 |
|
|
{
|
876 |
|
|
/* Check the parameters */
|
877 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
878 |
|
|
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
|
879 |
|
|
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
|
880 |
|
|
assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
|
881 |
|
|
|
882 |
|
|
/* Configure the ETR Clock source */
|
883 |
|
|
TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
|
884 |
|
|
/* Enable the External clock mode2 */
|
885 |
|
|
TIMx->SMCR |= TIM_SMCR_ECE;
|
886 |
|
|
}
|
887 |
|
|
|
888 |
|
|
/**
|
889 |
|
|
* @brief Configures the TIMx External Trigger (ETR).
|
890 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
891 |
|
|
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
892 |
|
|
* This parameter can be one of the following values:
|
893 |
|
|
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
894 |
|
|
* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
|
895 |
|
|
* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
|
896 |
|
|
* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
|
897 |
|
|
* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
898 |
|
|
* This parameter can be one of the following values:
|
899 |
|
|
* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
|
900 |
|
|
* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
|
901 |
|
|
* @param ExtTRGFilter: External Trigger Filter.
|
902 |
|
|
* This parameter must be a value between 0x00 and 0x0F
|
903 |
|
|
* @retval None
|
904 |
|
|
*/
|
905 |
|
|
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
906 |
|
|
uint16_t ExtTRGFilter)
|
907 |
|
|
{
|
908 |
|
|
uint16_t tmpsmcr = 0;
|
909 |
|
|
|
910 |
|
|
/* Check the parameters */
|
911 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
912 |
|
|
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
|
913 |
|
|
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
|
914 |
|
|
assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
|
915 |
|
|
|
916 |
|
|
tmpsmcr = TIMx->SMCR;
|
917 |
|
|
/* Reset the ETR Bits */
|
918 |
|
|
tmpsmcr &= SMCR_ETR_MASK;
|
919 |
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
920 |
|
|
tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
|
921 |
|
|
/* Write to TIMx SMCR */
|
922 |
|
|
TIMx->SMCR = tmpsmcr;
|
923 |
|
|
}
|
924 |
|
|
|
925 |
|
|
/**
|
926 |
|
|
* @brief Configures the TIMx Prescaler.
|
927 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
928 |
|
|
* @param Prescaler: specifies the Prescaler Register value
|
929 |
|
|
* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
|
930 |
|
|
* This parameter can be one of the following values:
|
931 |
|
|
* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
|
932 |
|
|
* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
|
933 |
|
|
* @retval None
|
934 |
|
|
*/
|
935 |
|
|
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
|
936 |
|
|
{
|
937 |
|
|
/* Check the parameters */
|
938 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
939 |
|
|
assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
|
940 |
|
|
|
941 |
|
|
/* Set the Prescaler value */
|
942 |
|
|
TIMx->PSC = Prescaler;
|
943 |
|
|
/* Set or reset the UG Bit */
|
944 |
|
|
TIMx->EGR = TIM_PSCReloadMode;
|
945 |
|
|
}
|
946 |
|
|
|
947 |
|
|
/**
|
948 |
|
|
* @brief Specifies the TIMx Counter Mode to be used.
|
949 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
950 |
|
|
* @param TIM_CounterMode: specifies the Counter Mode to be used
|
951 |
|
|
* This parameter can be one of the following values:
|
952 |
|
|
* @arg TIM_CounterMode_Up: TIM Up Counting Mode
|
953 |
|
|
* @arg TIM_CounterMode_Down: TIM Down Counting Mode
|
954 |
|
|
* @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
|
955 |
|
|
* @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
|
956 |
|
|
* @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
|
957 |
|
|
* @retval None
|
958 |
|
|
*/
|
959 |
|
|
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
|
960 |
|
|
{
|
961 |
|
|
uint16_t tmpcr1 = 0;
|
962 |
|
|
|
963 |
|
|
/* Check the parameters */
|
964 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
965 |
|
|
assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
|
966 |
|
|
|
967 |
|
|
tmpcr1 = TIMx->CR1;
|
968 |
|
|
/* Reset the CMS and DIR Bits */
|
969 |
|
|
tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
|
970 |
|
|
/* Set the Counter Mode */
|
971 |
|
|
tmpcr1 |= TIM_CounterMode;
|
972 |
|
|
/* Write to TIMx CR1 register */
|
973 |
|
|
TIMx->CR1 = tmpcr1;
|
974 |
|
|
}
|
975 |
|
|
|
976 |
|
|
/**
|
977 |
|
|
* @brief Selects the Input Trigger source
|
978 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
979 |
|
|
* @param TIM_InputTriggerSource: The Input Trigger source.
|
980 |
|
|
* This parameter can be one of the following values:
|
981 |
|
|
* @arg TIM_TS_ITR0: Internal Trigger 0
|
982 |
|
|
* @arg TIM_TS_ITR1: Internal Trigger 1
|
983 |
|
|
* @arg TIM_TS_ITR2: Internal Trigger 2
|
984 |
|
|
* @arg TIM_TS_ITR3: Internal Trigger 3
|
985 |
|
|
* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
|
986 |
|
|
* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
|
987 |
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
988 |
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
989 |
|
|
* @retval None
|
990 |
|
|
*/
|
991 |
|
|
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
|
992 |
|
|
{
|
993 |
|
|
uint16_t tmpsmcr = 0;
|
994 |
|
|
|
995 |
|
|
/* Check the parameters */
|
996 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
997 |
|
|
assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
|
998 |
|
|
|
999 |
|
|
/* Get the TIMx SMCR register value */
|
1000 |
|
|
tmpsmcr = TIMx->SMCR;
|
1001 |
|
|
/* Reset the TS Bits */
|
1002 |
|
|
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
|
1003 |
|
|
/* Set the Input Trigger source */
|
1004 |
|
|
tmpsmcr |= TIM_InputTriggerSource;
|
1005 |
|
|
/* Write to TIMx SMCR */
|
1006 |
|
|
TIMx->SMCR = tmpsmcr;
|
1007 |
|
|
}
|
1008 |
|
|
|
1009 |
|
|
/**
|
1010 |
|
|
* @brief Configures the TIMx Encoder Interface.
|
1011 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1012 |
|
|
* @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
|
1013 |
|
|
* This parameter can be one of the following values:
|
1014 |
|
|
* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
|
1015 |
|
|
* @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
|
1016 |
|
|
* @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
|
1017 |
|
|
* on the level of the other input.
|
1018 |
|
|
* @param TIM_IC1Polarity: specifies the IC1 Polarity
|
1019 |
|
|
* This parmeter can be one of the following values:
|
1020 |
|
|
* @arg TIM_ICPolarity_Falling: IC Falling edge.
|
1021 |
|
|
* @arg TIM_ICPolarity_Rising: IC Rising edge.
|
1022 |
|
|
* @param TIM_IC2Polarity: specifies the IC2 Polarity
|
1023 |
|
|
* This parmeter can be one of the following values:
|
1024 |
|
|
* @arg TIM_ICPolarity_Falling: IC Falling edge.
|
1025 |
|
|
* @arg TIM_ICPolarity_Rising: IC Rising edge.
|
1026 |
|
|
* @retval None
|
1027 |
|
|
*/
|
1028 |
|
|
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
|
1029 |
|
|
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
|
1030 |
|
|
{
|
1031 |
|
|
uint16_t tmpsmcr = 0;
|
1032 |
|
|
uint16_t tmpccmr1 = 0;
|
1033 |
|
|
uint16_t tmpccer = 0;
|
1034 |
|
|
|
1035 |
|
|
/* Check the parameters */
|
1036 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1037 |
|
|
assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
|
1038 |
|
|
assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
|
1039 |
|
|
assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
|
1040 |
|
|
|
1041 |
|
|
/* Get the TIMx SMCR register value */
|
1042 |
|
|
tmpsmcr = TIMx->SMCR;
|
1043 |
|
|
/* Get the TIMx CCMR1 register value */
|
1044 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
1045 |
|
|
/* Get the TIMx CCER register value */
|
1046 |
|
|
tmpccer = TIMx->CCER;
|
1047 |
|
|
/* Set the encoder Mode */
|
1048 |
|
|
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
|
1049 |
|
|
tmpsmcr |= TIM_EncoderMode;
|
1050 |
|
|
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
1051 |
|
|
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
|
1052 |
|
|
tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
|
1053 |
|
|
/* Set the TI1 and the TI2 Polarities */
|
1054 |
|
|
tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
|
1055 |
|
|
tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
|
1056 |
|
|
/* Write to TIMx SMCR */
|
1057 |
|
|
TIMx->SMCR = tmpsmcr;
|
1058 |
|
|
/* Write to TIMx CCMR1 */
|
1059 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
1060 |
|
|
/* Write to TIMx CCER */
|
1061 |
|
|
TIMx->CCER = tmpccer;
|
1062 |
|
|
}
|
1063 |
|
|
|
1064 |
|
|
/**
|
1065 |
|
|
* @brief Forces the TIMx output 1 waveform to active or inactive level.
|
1066 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
1067 |
|
|
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
|
1068 |
|
|
* This parameter can be one of the following values:
|
1069 |
|
|
* @arg TIM_ForcedAction_Active: Force active level on OC1REF
|
1070 |
|
|
* @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
|
1071 |
|
|
* @retval None
|
1072 |
|
|
*/
|
1073 |
|
|
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
|
1074 |
|
|
{
|
1075 |
|
|
uint16_t tmpccmr1 = 0;
|
1076 |
|
|
/* Check the parameters */
|
1077 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
1078 |
|
|
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
|
1079 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
1080 |
|
|
/* Reset the OC1M Bits */
|
1081 |
|
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
|
1082 |
|
|
/* Configure The Forced output Mode */
|
1083 |
|
|
tmpccmr1 |= TIM_ForcedAction;
|
1084 |
|
|
/* Write to TIMx CCMR1 register */
|
1085 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
1086 |
|
|
}
|
1087 |
|
|
|
1088 |
|
|
/**
|
1089 |
|
|
* @brief Forces the TIMx output 2 waveform to active or inactive level.
|
1090 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM
|
1091 |
|
|
* peripheral.
|
1092 |
|
|
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
|
1093 |
|
|
* This parameter can be one of the following values:
|
1094 |
|
|
* @arg TIM_ForcedAction_Active: Force active level on OC2REF
|
1095 |
|
|
* @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
|
1096 |
|
|
* @retval None
|
1097 |
|
|
*/
|
1098 |
|
|
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
|
1099 |
|
|
{
|
1100 |
|
|
uint16_t tmpccmr1 = 0;
|
1101 |
|
|
|
1102 |
|
|
/* Check the parameters */
|
1103 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
1104 |
|
|
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
|
1105 |
|
|
|
1106 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
1107 |
|
|
/* Reset the OC2M Bits */
|
1108 |
|
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
|
1109 |
|
|
/* Configure The Forced output Mode */
|
1110 |
|
|
tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
|
1111 |
|
|
/* Write to TIMx CCMR1 register */
|
1112 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
1113 |
|
|
}
|
1114 |
|
|
|
1115 |
|
|
/**
|
1116 |
|
|
* @brief Forces the TIMx output 3 waveform to active or inactive level.
|
1117 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1118 |
|
|
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
|
1119 |
|
|
* This parameter can be one of the following values:
|
1120 |
|
|
* @arg TIM_ForcedAction_Active: Force active level on OC3REF
|
1121 |
|
|
* @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
|
1122 |
|
|
* @retval None
|
1123 |
|
|
*/
|
1124 |
|
|
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
|
1125 |
|
|
{
|
1126 |
|
|
uint16_t tmpccmr2 = 0;
|
1127 |
|
|
|
1128 |
|
|
/* Check the parameters */
|
1129 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1130 |
|
|
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
|
1131 |
|
|
|
1132 |
|
|
tmpccmr2 = TIMx->CCMR2;
|
1133 |
|
|
/* Reset the OC1M Bits */
|
1134 |
|
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
|
1135 |
|
|
/* Configure The Forced output Mode */
|
1136 |
|
|
tmpccmr2 |= TIM_ForcedAction;
|
1137 |
|
|
/* Write to TIMx CCMR2 register */
|
1138 |
|
|
TIMx->CCMR2 = tmpccmr2;
|
1139 |
|
|
}
|
1140 |
|
|
|
1141 |
|
|
/**
|
1142 |
|
|
* @brief Forces the TIMx output 4 waveform to active or inactive level.
|
1143 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1144 |
|
|
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
|
1145 |
|
|
* This parameter can be one of the following values:
|
1146 |
|
|
* @arg TIM_ForcedAction_Active: Force active level on OC4REF
|
1147 |
|
|
* @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
|
1148 |
|
|
* @retval None
|
1149 |
|
|
*/
|
1150 |
|
|
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
|
1151 |
|
|
{
|
1152 |
|
|
uint16_t tmpccmr2 = 0;
|
1153 |
|
|
/* Check the parameters */
|
1154 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1155 |
|
|
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
|
1156 |
|
|
|
1157 |
|
|
tmpccmr2 = TIMx->CCMR2;
|
1158 |
|
|
/* Reset the OC2M Bits */
|
1159 |
|
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
|
1160 |
|
|
/* Configure The Forced output Mode */
|
1161 |
|
|
tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
|
1162 |
|
|
/* Write to TIMx CCMR2 register */
|
1163 |
|
|
TIMx->CCMR2 = tmpccmr2;
|
1164 |
|
|
}
|
1165 |
|
|
|
1166 |
|
|
/**
|
1167 |
|
|
* @brief Enables or disables TIMx peripheral Preload register on ARR.
|
1168 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
1169 |
|
|
* @param NewState: new state of the TIMx peripheral Preload register
|
1170 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1171 |
|
|
* @retval None
|
1172 |
|
|
*/
|
1173 |
|
|
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
|
1174 |
|
|
{
|
1175 |
|
|
/* Check the parameters */
|
1176 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
1177 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1178 |
|
|
|
1179 |
|
|
if (NewState != DISABLE)
|
1180 |
|
|
{
|
1181 |
|
|
/* Set the ARR Preload Bit */
|
1182 |
|
|
TIMx->CR1 |= TIM_CR1_ARPE;
|
1183 |
|
|
}
|
1184 |
|
|
else
|
1185 |
|
|
{
|
1186 |
|
|
/* Reset the ARR Preload Bit */
|
1187 |
|
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
|
1188 |
|
|
}
|
1189 |
|
|
}
|
1190 |
|
|
|
1191 |
|
|
/**
|
1192 |
|
|
* @brief Selects the TIMx peripheral Capture Compare DMA source.
|
1193 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1194 |
|
|
* @param NewState: new state of the Capture Compare DMA source
|
1195 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1196 |
|
|
* @retval None
|
1197 |
|
|
*/
|
1198 |
|
|
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
|
1199 |
|
|
{
|
1200 |
|
|
/* Check the parameters */
|
1201 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1202 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1203 |
|
|
|
1204 |
|
|
if (NewState != DISABLE)
|
1205 |
|
|
{
|
1206 |
|
|
/* Set the CCDS Bit */
|
1207 |
|
|
TIMx->CR2 |= TIM_CR2_CCDS;
|
1208 |
|
|
}
|
1209 |
|
|
else
|
1210 |
|
|
{
|
1211 |
|
|
/* Reset the CCDS Bit */
|
1212 |
|
|
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
|
1213 |
|
|
}
|
1214 |
|
|
}
|
1215 |
|
|
|
1216 |
|
|
/**
|
1217 |
|
|
* @brief Enables or disables the TIMx peripheral Preload register on CCR1.
|
1218 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
1219 |
|
|
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
|
1220 |
|
|
* This parameter can be one of the following values:
|
1221 |
|
|
* @arg TIM_OCPreload_Enable
|
1222 |
|
|
* @arg TIM_OCPreload_Disable
|
1223 |
|
|
* @retval None
|
1224 |
|
|
*/
|
1225 |
|
|
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
|
1226 |
|
|
{
|
1227 |
|
|
uint16_t tmpccmr1 = 0;
|
1228 |
|
|
/* Check the parameters */
|
1229 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
1230 |
|
|
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
|
1231 |
|
|
|
1232 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
1233 |
|
|
/* Reset the OC1PE Bit */
|
1234 |
|
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
|
1235 |
|
|
/* Enable or Disable the Output Compare Preload feature */
|
1236 |
|
|
tmpccmr1 |= TIM_OCPreload;
|
1237 |
|
|
/* Write to TIMx CCMR1 register */
|
1238 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
1239 |
|
|
}
|
1240 |
|
|
|
1241 |
|
|
/**
|
1242 |
|
|
* @brief Enables or disables the TIMx peripheral Preload register on CCR2.
|
1243 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
1244 |
|
|
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
|
1245 |
|
|
* This parameter can be one of the following values:
|
1246 |
|
|
* @arg TIM_OCPreload_Enable
|
1247 |
|
|
* @arg TIM_OCPreload_Disable
|
1248 |
|
|
* @retval None
|
1249 |
|
|
*/
|
1250 |
|
|
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
|
1251 |
|
|
{
|
1252 |
|
|
uint16_t tmpccmr1 = 0;
|
1253 |
|
|
/* Check the parameters */
|
1254 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
1255 |
|
|
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
|
1256 |
|
|
|
1257 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
1258 |
|
|
/* Reset the OC2PE Bit */
|
1259 |
|
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
|
1260 |
|
|
/* Enable or Disable the Output Compare Preload feature */
|
1261 |
|
|
tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
|
1262 |
|
|
/* Write to TIMx CCMR1 register */
|
1263 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
1264 |
|
|
}
|
1265 |
|
|
|
1266 |
|
|
/**
|
1267 |
|
|
* @brief Enables or disables the TIMx peripheral Preload register on CCR3.
|
1268 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1269 |
|
|
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
|
1270 |
|
|
* This parameter can be one of the following values:
|
1271 |
|
|
* @arg TIM_OCPreload_Enable
|
1272 |
|
|
* @arg TIM_OCPreload_Disable
|
1273 |
|
|
* @retval None
|
1274 |
|
|
*/
|
1275 |
|
|
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
|
1276 |
|
|
{
|
1277 |
|
|
uint16_t tmpccmr2 = 0;
|
1278 |
|
|
|
1279 |
|
|
/* Check the parameters */
|
1280 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1281 |
|
|
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
|
1282 |
|
|
|
1283 |
|
|
tmpccmr2 = TIMx->CCMR2;
|
1284 |
|
|
/* Reset the OC3PE Bit */
|
1285 |
|
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
|
1286 |
|
|
/* Enable or Disable the Output Compare Preload feature */
|
1287 |
|
|
tmpccmr2 |= TIM_OCPreload;
|
1288 |
|
|
/* Write to TIMx CCMR2 register */
|
1289 |
|
|
TIMx->CCMR2 = tmpccmr2;
|
1290 |
|
|
}
|
1291 |
|
|
|
1292 |
|
|
/**
|
1293 |
|
|
* @brief Enables or disables the TIMx peripheral Preload register on CCR4.
|
1294 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1295 |
|
|
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
|
1296 |
|
|
* This parameter can be one of the following values:
|
1297 |
|
|
* @arg TIM_OCPreload_Enable
|
1298 |
|
|
* @arg TIM_OCPreload_Disable
|
1299 |
|
|
* @retval None
|
1300 |
|
|
*/
|
1301 |
|
|
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
|
1302 |
|
|
{
|
1303 |
|
|
uint16_t tmpccmr2 = 0;
|
1304 |
|
|
|
1305 |
|
|
/* Check the parameters */
|
1306 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1307 |
|
|
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
|
1308 |
|
|
|
1309 |
|
|
tmpccmr2 = TIMx->CCMR2;
|
1310 |
|
|
/* Reset the OC4PE Bit */
|
1311 |
|
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
|
1312 |
|
|
/* Enable or Disable the Output Compare Preload feature */
|
1313 |
|
|
tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
|
1314 |
|
|
/* Write to TIMx CCMR2 register */
|
1315 |
|
|
TIMx->CCMR2 = tmpccmr2;
|
1316 |
|
|
}
|
1317 |
|
|
|
1318 |
|
|
/**
|
1319 |
|
|
* @brief Configures the TIMx Output Compare 1 Fast feature.
|
1320 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
1321 |
|
|
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
|
1322 |
|
|
* This parameter can be one of the following values:
|
1323 |
|
|
* @arg TIM_OCFast_Enable: TIM output compare fast enable
|
1324 |
|
|
* @arg TIM_OCFast_Disable: TIM output compare fast disable
|
1325 |
|
|
* @retval None
|
1326 |
|
|
*/
|
1327 |
|
|
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
|
1328 |
|
|
{
|
1329 |
|
|
uint16_t tmpccmr1 = 0;
|
1330 |
|
|
|
1331 |
|
|
/* Check the parameters */
|
1332 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
1333 |
|
|
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
|
1334 |
|
|
|
1335 |
|
|
/* Get the TIMx CCMR1 register value */
|
1336 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
1337 |
|
|
/* Reset the OC1FE Bit */
|
1338 |
|
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
|
1339 |
|
|
/* Enable or Disable the Output Compare Fast Bit */
|
1340 |
|
|
tmpccmr1 |= TIM_OCFast;
|
1341 |
|
|
/* Write to TIMx CCMR1 */
|
1342 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
1343 |
|
|
}
|
1344 |
|
|
|
1345 |
|
|
/**
|
1346 |
|
|
* @brief Configures the TIMx Output Compare 2 Fast feature.
|
1347 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
1348 |
|
|
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
|
1349 |
|
|
* This parameter can be one of the following values:
|
1350 |
|
|
* @arg TIM_OCFast_Enable: TIM output compare fast enable
|
1351 |
|
|
* @arg TIM_OCFast_Disable: TIM output compare fast disable
|
1352 |
|
|
* @retval None
|
1353 |
|
|
*/
|
1354 |
|
|
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
|
1355 |
|
|
{
|
1356 |
|
|
uint16_t tmpccmr1 = 0;
|
1357 |
|
|
|
1358 |
|
|
/* Check the parameters */
|
1359 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
1360 |
|
|
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
|
1361 |
|
|
|
1362 |
|
|
/* Get the TIMx CCMR1 register value */
|
1363 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
1364 |
|
|
/* Reset the OC2FE Bit */
|
1365 |
|
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
|
1366 |
|
|
/* Enable or Disable the Output Compare Fast Bit */
|
1367 |
|
|
tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
|
1368 |
|
|
/* Write to TIMx CCMR1 */
|
1369 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
1370 |
|
|
}
|
1371 |
|
|
|
1372 |
|
|
/**
|
1373 |
|
|
* @brief Configures the TIMx Output Compare 3 Fast feature.
|
1374 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1375 |
|
|
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
|
1376 |
|
|
* This parameter can be one of the following values:
|
1377 |
|
|
* @arg TIM_OCFast_Enable: TIM output compare fast enable
|
1378 |
|
|
* @arg TIM_OCFast_Disable: TIM output compare fast disable
|
1379 |
|
|
* @retval None
|
1380 |
|
|
*/
|
1381 |
|
|
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
|
1382 |
|
|
{
|
1383 |
|
|
uint16_t tmpccmr2 = 0;
|
1384 |
|
|
|
1385 |
|
|
/* Check the parameters */
|
1386 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1387 |
|
|
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
|
1388 |
|
|
|
1389 |
|
|
/* Get the TIMx CCMR2 register value */
|
1390 |
|
|
tmpccmr2 = TIMx->CCMR2;
|
1391 |
|
|
/* Reset the OC3FE Bit */
|
1392 |
|
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
|
1393 |
|
|
/* Enable or Disable the Output Compare Fast Bit */
|
1394 |
|
|
tmpccmr2 |= TIM_OCFast;
|
1395 |
|
|
/* Write to TIMx CCMR2 */
|
1396 |
|
|
TIMx->CCMR2 = tmpccmr2;
|
1397 |
|
|
}
|
1398 |
|
|
|
1399 |
|
|
/**
|
1400 |
|
|
* @brief Configures the TIMx Output Compare 4 Fast feature.
|
1401 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1402 |
|
|
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
|
1403 |
|
|
* This parameter can be one of the following values:
|
1404 |
|
|
* @arg TIM_OCFast_Enable: TIM output compare fast enable
|
1405 |
|
|
* @arg TIM_OCFast_Disable: TIM output compare fast disable
|
1406 |
|
|
* @retval None
|
1407 |
|
|
*/
|
1408 |
|
|
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
|
1409 |
|
|
{
|
1410 |
|
|
uint16_t tmpccmr2 = 0;
|
1411 |
|
|
|
1412 |
|
|
/* Check the parameters */
|
1413 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1414 |
|
|
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
|
1415 |
|
|
|
1416 |
|
|
/* Get the TIMx CCMR2 register value */
|
1417 |
|
|
tmpccmr2 = TIMx->CCMR2;
|
1418 |
|
|
/* Reset the OC4FE Bit */
|
1419 |
|
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
|
1420 |
|
|
/* Enable or Disable the Output Compare Fast Bit */
|
1421 |
|
|
tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
|
1422 |
|
|
/* Write to TIMx CCMR2 */
|
1423 |
|
|
TIMx->CCMR2 = tmpccmr2;
|
1424 |
|
|
}
|
1425 |
|
|
|
1426 |
|
|
/**
|
1427 |
|
|
* @brief Clears or safeguards the OCREF1 signal on an external event
|
1428 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
1429 |
|
|
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
1430 |
|
|
* This parameter can be one of the following values:
|
1431 |
|
|
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
1432 |
|
|
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
1433 |
|
|
* @retval None
|
1434 |
|
|
*/
|
1435 |
|
|
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
|
1436 |
|
|
{
|
1437 |
|
|
uint16_t tmpccmr1 = 0;
|
1438 |
|
|
|
1439 |
|
|
/* Check the parameters */
|
1440 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
1441 |
|
|
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
|
1442 |
|
|
|
1443 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
1444 |
|
|
/* Reset the OC1CE Bit */
|
1445 |
|
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
|
1446 |
|
|
/* Enable or Disable the Output Compare Clear Bit */
|
1447 |
|
|
tmpccmr1 |= TIM_OCClear;
|
1448 |
|
|
/* Write to TIMx CCMR1 register */
|
1449 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
1450 |
|
|
}
|
1451 |
|
|
|
1452 |
|
|
/**
|
1453 |
|
|
* @brief Clears or safeguards the OCREF2 signal on an external event
|
1454 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
1455 |
|
|
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
1456 |
|
|
|
1457 |
|
|
* This parameter can be one of the following values:
|
1458 |
|
|
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
1459 |
|
|
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
1460 |
|
|
* @retval None
|
1461 |
|
|
*/
|
1462 |
|
|
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
|
1463 |
|
|
{
|
1464 |
|
|
uint16_t tmpccmr1 = 0;
|
1465 |
|
|
|
1466 |
|
|
/* Check the parameters */
|
1467 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
1468 |
|
|
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
|
1469 |
|
|
|
1470 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
1471 |
|
|
/* Reset the OC2CE Bit */
|
1472 |
|
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
|
1473 |
|
|
/* Enable or Disable the Output Compare Clear Bit */
|
1474 |
|
|
tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
|
1475 |
|
|
/* Write to TIMx CCMR1 register */
|
1476 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
1477 |
|
|
}
|
1478 |
|
|
|
1479 |
|
|
/**
|
1480 |
|
|
* @brief Clears or safeguards the OCREF3 signal on an external event
|
1481 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1482 |
|
|
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
1483 |
|
|
* This parameter can be one of the following values:
|
1484 |
|
|
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
1485 |
|
|
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
1486 |
|
|
* @retval None
|
1487 |
|
|
*/
|
1488 |
|
|
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
|
1489 |
|
|
{
|
1490 |
|
|
uint16_t tmpccmr2 = 0;
|
1491 |
|
|
|
1492 |
|
|
/* Check the parameters */
|
1493 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1494 |
|
|
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
|
1495 |
|
|
|
1496 |
|
|
tmpccmr2 = TIMx->CCMR2;
|
1497 |
|
|
/* Reset the OC3CE Bit */
|
1498 |
|
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
|
1499 |
|
|
/* Enable or Disable the Output Compare Clear Bit */
|
1500 |
|
|
tmpccmr2 |= TIM_OCClear;
|
1501 |
|
|
/* Write to TIMx CCMR2 register */
|
1502 |
|
|
TIMx->CCMR2 = tmpccmr2;
|
1503 |
|
|
}
|
1504 |
|
|
|
1505 |
|
|
/**
|
1506 |
|
|
* @brief Clears or safeguards the OCREF4 signal on an external event
|
1507 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1508 |
|
|
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
1509 |
|
|
* This parameter can be one of the following values:
|
1510 |
|
|
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
1511 |
|
|
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
1512 |
|
|
* @retval None
|
1513 |
|
|
*/
|
1514 |
|
|
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
|
1515 |
|
|
{
|
1516 |
|
|
uint16_t tmpccmr2 = 0;
|
1517 |
|
|
|
1518 |
|
|
/* Check the parameters */
|
1519 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1520 |
|
|
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
|
1521 |
|
|
|
1522 |
|
|
tmpccmr2 = TIMx->CCMR2;
|
1523 |
|
|
/* Reset the OC4CE Bit */
|
1524 |
|
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
|
1525 |
|
|
/* Enable or Disable the Output Compare Clear Bit */
|
1526 |
|
|
tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
|
1527 |
|
|
/* Write to TIMx CCMR2 register */
|
1528 |
|
|
TIMx->CCMR2 = tmpccmr2;
|
1529 |
|
|
}
|
1530 |
|
|
|
1531 |
|
|
/**
|
1532 |
|
|
* @brief Configures the TIMx channel 1 polarity.
|
1533 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
1534 |
|
|
* @param TIM_OCPolarity: specifies the OC1 Polarity
|
1535 |
|
|
* This parmeter can be one of the following values:
|
1536 |
|
|
* @arg TIM_OCPolarity_High: Output Compare active high
|
1537 |
|
|
* @arg TIM_OCPolarity_Low: Output Compare active low
|
1538 |
|
|
* @retval None
|
1539 |
|
|
*/
|
1540 |
|
|
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
|
1541 |
|
|
{
|
1542 |
|
|
uint16_t tmpccer = 0;
|
1543 |
|
|
|
1544 |
|
|
/* Check the parameters */
|
1545 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
1546 |
|
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
|
1547 |
|
|
|
1548 |
|
|
tmpccer = TIMx->CCER;
|
1549 |
|
|
/* Set or Reset the CC1P Bit */
|
1550 |
|
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
|
1551 |
|
|
tmpccer |= TIM_OCPolarity;
|
1552 |
|
|
/* Write to TIMx CCER register */
|
1553 |
|
|
TIMx->CCER = tmpccer;
|
1554 |
|
|
}
|
1555 |
|
|
|
1556 |
|
|
/**
|
1557 |
|
|
* @brief Configures the TIMx channel 2 polarity.
|
1558 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
1559 |
|
|
* @param TIM_OCPolarity: specifies the OC2 Polarity
|
1560 |
|
|
* This parmeter can be one of the following values:
|
1561 |
|
|
* @arg TIM_OCPolarity_High: Output Compare active high
|
1562 |
|
|
* @arg TIM_OCPolarity_Low: Output Compare active low
|
1563 |
|
|
* @retval None
|
1564 |
|
|
*/
|
1565 |
|
|
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
|
1566 |
|
|
{
|
1567 |
|
|
uint16_t tmpccer = 0;
|
1568 |
|
|
|
1569 |
|
|
/* Check the parameters */
|
1570 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
1571 |
|
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
|
1572 |
|
|
|
1573 |
|
|
tmpccer = TIMx->CCER;
|
1574 |
|
|
/* Set or Reset the CC2P Bit */
|
1575 |
|
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
|
1576 |
|
|
tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
|
1577 |
|
|
/* Write to TIMx CCER register */
|
1578 |
|
|
TIMx->CCER = tmpccer;
|
1579 |
|
|
}
|
1580 |
|
|
|
1581 |
|
|
/**
|
1582 |
|
|
* @brief Configures the TIMx channel 3 polarity.
|
1583 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1584 |
|
|
* @param TIM_OCPolarity: specifies the OC3 Polarity
|
1585 |
|
|
* This parmeter can be one of the following values:
|
1586 |
|
|
* @arg TIM_OCPolarity_High: Output Compare active high
|
1587 |
|
|
* @arg TIM_OCPolarity_Low: Output Compare active low
|
1588 |
|
|
* @retval None
|
1589 |
|
|
*/
|
1590 |
|
|
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
|
1591 |
|
|
{
|
1592 |
|
|
uint16_t tmpccer = 0;
|
1593 |
|
|
|
1594 |
|
|
/* Check the parameters */
|
1595 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1596 |
|
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
|
1597 |
|
|
|
1598 |
|
|
tmpccer = TIMx->CCER;
|
1599 |
|
|
/* Set or Reset the CC3P Bit */
|
1600 |
|
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
|
1601 |
|
|
tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
|
1602 |
|
|
/* Write to TIMx CCER register */
|
1603 |
|
|
TIMx->CCER = tmpccer;
|
1604 |
|
|
}
|
1605 |
|
|
|
1606 |
|
|
/**
|
1607 |
|
|
* @brief Configures the TIMx channel 4 polarity.
|
1608 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1609 |
|
|
* @param TIM_OCPolarity: specifies the OC4 Polarity
|
1610 |
|
|
* This parmeter can be one of the following values:
|
1611 |
|
|
* @arg TIM_OCPolarity_High: Output Compare active high
|
1612 |
|
|
* @arg TIM_OCPolarity_Low: Output Compare active low
|
1613 |
|
|
* @retval None
|
1614 |
|
|
*/
|
1615 |
|
|
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
|
1616 |
|
|
{
|
1617 |
|
|
uint16_t tmpccer = 0;
|
1618 |
|
|
|
1619 |
|
|
/* Check the parameters */
|
1620 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1621 |
|
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
|
1622 |
|
|
|
1623 |
|
|
tmpccer = TIMx->CCER;
|
1624 |
|
|
/* Set or Reset the CC4P Bit */
|
1625 |
|
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
|
1626 |
|
|
tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
|
1627 |
|
|
/* Write to TIMx CCER register */
|
1628 |
|
|
TIMx->CCER = tmpccer;
|
1629 |
|
|
}
|
1630 |
|
|
|
1631 |
|
|
/**
|
1632 |
|
|
* @brief Enables or disables the TIM Capture Compare Channel x.
|
1633 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
1634 |
|
|
* @param TIM_Channel: specifies the TIM Channel
|
1635 |
|
|
* This parmeter can be one of the following values:
|
1636 |
|
|
* @arg TIM_Channel_1: TIM Channel 1
|
1637 |
|
|
* @arg TIM_Channel_2: TIM Channel 2
|
1638 |
|
|
* @arg TIM_Channel_3: TIM Channel 3
|
1639 |
|
|
* @arg TIM_Channel_4: TIM Channel 4
|
1640 |
|
|
* @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
|
1641 |
|
|
* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
|
1642 |
|
|
* @retval None
|
1643 |
|
|
*/
|
1644 |
|
|
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
|
1645 |
|
|
{
|
1646 |
|
|
uint16_t tmp = 0;
|
1647 |
|
|
|
1648 |
|
|
/* Check the parameters */
|
1649 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
1650 |
|
|
assert_param(IS_TIM_CCX(TIM_CCx));
|
1651 |
|
|
|
1652 |
|
|
tmp = CCER_CCE_SET << TIM_Channel;
|
1653 |
|
|
|
1654 |
|
|
/* Reset the CCxE Bit */
|
1655 |
|
|
TIMx->CCER &= (uint16_t)~ tmp;
|
1656 |
|
|
|
1657 |
|
|
/* Set or reset the CCxE Bit */
|
1658 |
|
|
TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
|
1659 |
|
|
}
|
1660 |
|
|
|
1661 |
|
|
/**
|
1662 |
|
|
* @brief Selects the TIM Ouput Compare Mode.
|
1663 |
|
|
* @note This function disables the selected channel before changing the Ouput
|
1664 |
|
|
* Compare Mode.
|
1665 |
|
|
* User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
|
1666 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
1667 |
|
|
* @param TIM_Channel: specifies the TIM Channel
|
1668 |
|
|
* This parmeter can be one of the following values:
|
1669 |
|
|
* @arg TIM_Channel_1: TIM Channel 1
|
1670 |
|
|
* @arg TIM_Channel_2: TIM Channel 2
|
1671 |
|
|
* @arg TIM_Channel_3: TIM Channel 3
|
1672 |
|
|
* @arg TIM_Channel_4: TIM Channel 4
|
1673 |
|
|
* @param TIM_OCMode: specifies the TIM Output Compare Mode.
|
1674 |
|
|
* This paramter can be one of the following values:
|
1675 |
|
|
* @arg TIM_OCMode_Timing
|
1676 |
|
|
* @arg TIM_OCMode_Active
|
1677 |
|
|
* @arg TIM_OCMode_Toggle
|
1678 |
|
|
* @arg TIM_OCMode_PWM1
|
1679 |
|
|
* @arg TIM_OCMode_PWM2
|
1680 |
|
|
* @arg TIM_ForcedAction_Active
|
1681 |
|
|
* @arg TIM_ForcedAction_InActive
|
1682 |
|
|
* @retval None
|
1683 |
|
|
*/
|
1684 |
|
|
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
|
1685 |
|
|
{
|
1686 |
|
|
uint32_t tmp = 0;
|
1687 |
|
|
uint16_t tmp1 = 0;
|
1688 |
|
|
|
1689 |
|
|
/* Check the parameters */
|
1690 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
1691 |
|
|
assert_param(IS_TIM_OCM(TIM_OCMode));
|
1692 |
|
|
|
1693 |
|
|
tmp = (uint32_t) TIMx;
|
1694 |
|
|
tmp += CCMR_OFFSET;
|
1695 |
|
|
|
1696 |
|
|
tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
|
1697 |
|
|
|
1698 |
|
|
/* Disable the Channel: Reset the CCxE Bit */
|
1699 |
|
|
TIMx->CCER &= (uint16_t) ~tmp1;
|
1700 |
|
|
|
1701 |
|
|
if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
|
1702 |
|
|
{
|
1703 |
|
|
tmp += (TIM_Channel>>1);
|
1704 |
|
|
|
1705 |
|
|
/* Reset the OCxM bits in the CCMRx register */
|
1706 |
|
|
*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
|
1707 |
|
|
|
1708 |
|
|
/* Configure the OCxM bits in the CCMRx register */
|
1709 |
|
|
*(__IO uint32_t *) tmp |= TIM_OCMode;
|
1710 |
|
|
}
|
1711 |
|
|
else
|
1712 |
|
|
{
|
1713 |
|
|
tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
|
1714 |
|
|
|
1715 |
|
|
/* Reset the OCxM bits in the CCMRx register */
|
1716 |
|
|
*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
|
1717 |
|
|
|
1718 |
|
|
/* Configure the OCxM bits in the CCMRx register */
|
1719 |
|
|
*(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
|
1720 |
|
|
}
|
1721 |
|
|
}
|
1722 |
|
|
|
1723 |
|
|
/**
|
1724 |
|
|
* @brief Enables or Disables the TIMx Update event.
|
1725 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
1726 |
|
|
* @param NewState: new state of the TIMx UDIS bit
|
1727 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1728 |
|
|
* @retval None
|
1729 |
|
|
*/
|
1730 |
|
|
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
|
1731 |
|
|
{
|
1732 |
|
|
/* Check the parameters */
|
1733 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
1734 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1735 |
|
|
|
1736 |
|
|
if (NewState != DISABLE)
|
1737 |
|
|
{
|
1738 |
|
|
/* Set the Update Disable Bit */
|
1739 |
|
|
TIMx->CR1 |= TIM_CR1_UDIS;
|
1740 |
|
|
}
|
1741 |
|
|
else
|
1742 |
|
|
{
|
1743 |
|
|
/* Reset the Update Disable Bit */
|
1744 |
|
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
|
1745 |
|
|
}
|
1746 |
|
|
}
|
1747 |
|
|
|
1748 |
|
|
/**
|
1749 |
|
|
* @brief Configures the TIMx Update Request Interrupt source.
|
1750 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
1751 |
|
|
* @param TIM_UpdateSource: specifies the Update source.
|
1752 |
|
|
* This parameter can be one of the following values:
|
1753 |
|
|
* @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
|
1754 |
|
|
or the setting of UG bit, or an update generation
|
1755 |
|
|
through the slave mode controller.
|
1756 |
|
|
* @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
|
1757 |
|
|
* @retval None
|
1758 |
|
|
*/
|
1759 |
|
|
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
|
1760 |
|
|
{
|
1761 |
|
|
/* Check the parameters */
|
1762 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
1763 |
|
|
assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
|
1764 |
|
|
|
1765 |
|
|
if (TIM_UpdateSource != TIM_UpdateSource_Global)
|
1766 |
|
|
{
|
1767 |
|
|
/* Set the URS Bit */
|
1768 |
|
|
TIMx->CR1 |= TIM_CR1_URS;
|
1769 |
|
|
}
|
1770 |
|
|
else
|
1771 |
|
|
{
|
1772 |
|
|
/* Reset the URS Bit */
|
1773 |
|
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
|
1774 |
|
|
}
|
1775 |
|
|
}
|
1776 |
|
|
|
1777 |
|
|
/**
|
1778 |
|
|
* @brief Enables or disables the TIMx’s Hall sensor interface.
|
1779 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1780 |
|
|
* @param NewState: new state of the TIMx Hall sensor interface.
|
1781 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
1782 |
|
|
* @retval None
|
1783 |
|
|
*/
|
1784 |
|
|
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
|
1785 |
|
|
{
|
1786 |
|
|
/* Check the parameters */
|
1787 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1788 |
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
1789 |
|
|
|
1790 |
|
|
if (NewState != DISABLE)
|
1791 |
|
|
{
|
1792 |
|
|
/* Set the TI1S Bit */
|
1793 |
|
|
TIMx->CR2 |= TIM_CR2_TI1S;
|
1794 |
|
|
}
|
1795 |
|
|
else
|
1796 |
|
|
{
|
1797 |
|
|
/* Reset the TI1S Bit */
|
1798 |
|
|
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
|
1799 |
|
|
}
|
1800 |
|
|
}
|
1801 |
|
|
|
1802 |
|
|
/**
|
1803 |
|
|
* @brief Selects the TIMx’s One Pulse Mode.
|
1804 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
1805 |
|
|
* @param TIM_OPMode: specifies the OPM Mode to be used.
|
1806 |
|
|
* This parameter can be one of the following values:
|
1807 |
|
|
* @arg TIM_OPMode_Single
|
1808 |
|
|
* @arg TIM_OPMode_Repetitive
|
1809 |
|
|
* @retval None
|
1810 |
|
|
*/
|
1811 |
|
|
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
|
1812 |
|
|
{
|
1813 |
|
|
/* Check the parameters */
|
1814 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
1815 |
|
|
assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
|
1816 |
|
|
|
1817 |
|
|
/* Reset the OPM Bit */
|
1818 |
|
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
|
1819 |
|
|
/* Configure the OPM Mode */
|
1820 |
|
|
TIMx->CR1 |= TIM_OPMode;
|
1821 |
|
|
}
|
1822 |
|
|
|
1823 |
|
|
/**
|
1824 |
|
|
* @brief Selects the TIMx Trigger Output Mode.
|
1825 |
|
|
* @param TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral.
|
1826 |
|
|
* @param TIM_TRGOSource: specifies the Trigger Output source.
|
1827 |
|
|
* This paramter can be one of the following values:
|
1828 |
|
|
*
|
1829 |
|
|
* - For all TIMx
|
1830 |
|
|
* @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
|
1831 |
|
|
* @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
|
1832 |
|
|
* @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
|
1833 |
|
|
*
|
1834 |
|
|
* - For all TIMx except TIM6 and TIM7
|
1835 |
|
|
* @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
|
1836 |
|
|
* is to be set, as soon as a capture or compare match occurs (TRGO).
|
1837 |
|
|
* @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
|
1838 |
|
|
|
1839 |
|
|
* - For all TIMx except TIM6, TIM7, TIM10 and TIM11
|
1840 |
|
|
* @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
|
1841 |
|
|
|
1842 |
|
|
* - For TIM2, TIM3 and TIM4
|
1843 |
|
|
* @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
|
1844 |
|
|
* @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
|
1845 |
|
|
*
|
1846 |
|
|
* @retval None
|
1847 |
|
|
*/
|
1848 |
|
|
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
|
1849 |
|
|
{
|
1850 |
|
|
/* Check the parameters */
|
1851 |
|
|
assert_param(IS_TIM_234679_PERIPH(TIMx));
|
1852 |
|
|
assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
|
1853 |
|
|
|
1854 |
|
|
/* Reset the MMS Bits */
|
1855 |
|
|
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
|
1856 |
|
|
/* Select the TRGO source */
|
1857 |
|
|
TIMx->CR2 |= TIM_TRGOSource;
|
1858 |
|
|
}
|
1859 |
|
|
|
1860 |
|
|
/**
|
1861 |
|
|
* @brief Selects the TIMx Slave Mode.
|
1862 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
1863 |
|
|
* @param TIM_SlaveMode: specifies the Timer Slave Mode.
|
1864 |
|
|
* This paramter can be one of the following values:
|
1865 |
|
|
* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
|
1866 |
|
|
* the counter and triggers an update of the registers.
|
1867 |
|
|
* @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
|
1868 |
|
|
* @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
|
1869 |
|
|
* @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
|
1870 |
|
|
* @retval None
|
1871 |
|
|
*/
|
1872 |
|
|
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
|
1873 |
|
|
{
|
1874 |
|
|
/* Check the parameters */
|
1875 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
1876 |
|
|
assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
|
1877 |
|
|
|
1878 |
|
|
/* Reset the SMS Bits */
|
1879 |
|
|
TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
|
1880 |
|
|
/* Select the Slave Mode */
|
1881 |
|
|
TIMx->SMCR |= TIM_SlaveMode;
|
1882 |
|
|
}
|
1883 |
|
|
|
1884 |
|
|
/**
|
1885 |
|
|
* @brief Sets or Resets the TIMx Master/Slave Mode.
|
1886 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
1887 |
|
|
* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
|
1888 |
|
|
* This paramter can be one of the following values:
|
1889 |
|
|
* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
|
1890 |
|
|
* and its slaves (through TRGO).
|
1891 |
|
|
* @arg TIM_MasterSlaveMode_Disable: No action
|
1892 |
|
|
* @retval None
|
1893 |
|
|
*/
|
1894 |
|
|
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
|
1895 |
|
|
{
|
1896 |
|
|
/* Check the parameters */
|
1897 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
1898 |
|
|
assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
|
1899 |
|
|
|
1900 |
|
|
/* Reset the MSM Bit */
|
1901 |
|
|
TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
|
1902 |
|
|
|
1903 |
|
|
/* Set or Reset the MSM Bit */
|
1904 |
|
|
TIMx->SMCR |= TIM_MasterSlaveMode;
|
1905 |
|
|
}
|
1906 |
|
|
|
1907 |
|
|
/**
|
1908 |
|
|
* @brief Sets the TIMx Counter Register value
|
1909 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
1910 |
|
|
* @param Counter: specifies the Counter register new value.
|
1911 |
|
|
* @retval None
|
1912 |
|
|
*/
|
1913 |
|
|
void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
|
1914 |
|
|
{
|
1915 |
|
|
/* Check the parameters */
|
1916 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
1917 |
|
|
|
1918 |
|
|
/* Set the Counter Register value */
|
1919 |
|
|
TIMx->CNT = Counter;
|
1920 |
|
|
}
|
1921 |
|
|
|
1922 |
|
|
/**
|
1923 |
|
|
* @brief Sets the TIMx Autoreload Register value
|
1924 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
1925 |
|
|
* @param Autoreload: specifies the Autoreload register new value.
|
1926 |
|
|
* @retval None
|
1927 |
|
|
*/
|
1928 |
|
|
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
|
1929 |
|
|
{
|
1930 |
|
|
/* Check the parameters */
|
1931 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
1932 |
|
|
|
1933 |
|
|
/* Set the Autoreload Register value */
|
1934 |
|
|
TIMx->ARR = Autoreload;
|
1935 |
|
|
}
|
1936 |
|
|
|
1937 |
|
|
/**
|
1938 |
|
|
* @brief Sets the TIMx Capture Compare1 Register value
|
1939 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
1940 |
|
|
* @param Compare1: specifies the Capture Compare1 register new value.
|
1941 |
|
|
* @retval None
|
1942 |
|
|
|
1943 |
|
|
*/
|
1944 |
|
|
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
|
1945 |
|
|
{
|
1946 |
|
|
/* Check the parameters */
|
1947 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
1948 |
|
|
|
1949 |
|
|
/* Set the Capture Compare1 Register value */
|
1950 |
|
|
TIMx->CCR1 = Compare1;
|
1951 |
|
|
}
|
1952 |
|
|
|
1953 |
|
|
/**
|
1954 |
|
|
* @brief Sets the TIMx Capture Compare2 Register value
|
1955 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
1956 |
|
|
* @param Compare2: specifies the Capture Compare2 register new value.
|
1957 |
|
|
* @retval None
|
1958 |
|
|
|
1959 |
|
|
*/
|
1960 |
|
|
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
|
1961 |
|
|
{
|
1962 |
|
|
/* Check the parameters */
|
1963 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
1964 |
|
|
|
1965 |
|
|
/* Set the Capture Compare2 Register value */
|
1966 |
|
|
TIMx->CCR2 = Compare2;
|
1967 |
|
|
}
|
1968 |
|
|
|
1969 |
|
|
/**
|
1970 |
|
|
* @brief Sets the TIMx Capture Compare3 Register value
|
1971 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1972 |
|
|
* @param Compare3: specifies the Capture Compare3 register new value.
|
1973 |
|
|
* @retval None
|
1974 |
|
|
|
1975 |
|
|
*/
|
1976 |
|
|
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
|
1977 |
|
|
{
|
1978 |
|
|
/* Check the parameters */
|
1979 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1980 |
|
|
|
1981 |
|
|
/* Set the Capture Compare3 Register value */
|
1982 |
|
|
TIMx->CCR3 = Compare3;
|
1983 |
|
|
}
|
1984 |
|
|
|
1985 |
|
|
/**
|
1986 |
|
|
* @brief Sets the TIMx Capture Compare4 Register value
|
1987 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
1988 |
|
|
* @param Compare4: specifies the Capture Compare4 register new value.
|
1989 |
|
|
* @retval None
|
1990 |
|
|
|
1991 |
|
|
*/
|
1992 |
|
|
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
|
1993 |
|
|
{
|
1994 |
|
|
/* Check the parameters */
|
1995 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
1996 |
|
|
|
1997 |
|
|
/* Set the Capture Compare4 Register value */
|
1998 |
|
|
TIMx->CCR4 = Compare4;
|
1999 |
|
|
}
|
2000 |
|
|
|
2001 |
|
|
/**
|
2002 |
|
|
* @brief Sets the TIMx Input Capture 1 prescaler.
|
2003 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
2004 |
|
|
* @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
|
2005 |
|
|
* This parameter can be one of the following values:
|
2006 |
|
|
* @arg TIM_ICPSC_DIV1: no prescaler
|
2007 |
|
|
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
2008 |
|
|
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
2009 |
|
|
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
2010 |
|
|
* @retval None
|
2011 |
|
|
*/
|
2012 |
|
|
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
|
2013 |
|
|
{
|
2014 |
|
|
/* Check the parameters */
|
2015 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
2016 |
|
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
|
2017 |
|
|
|
2018 |
|
|
/* Reset the IC1PSC Bits */
|
2019 |
|
|
TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
|
2020 |
|
|
/* Set the IC1PSC value */
|
2021 |
|
|
TIMx->CCMR1 |= TIM_ICPSC;
|
2022 |
|
|
}
|
2023 |
|
|
|
2024 |
|
|
/**
|
2025 |
|
|
* @brief Sets the TIMx Input Capture 2 prescaler.
|
2026 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
2027 |
|
|
* @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
|
2028 |
|
|
* This parameter can be one of the following values:
|
2029 |
|
|
* @arg TIM_ICPSC_DIV1: no prescaler
|
2030 |
|
|
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
2031 |
|
|
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
2032 |
|
|
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
2033 |
|
|
* @retval None
|
2034 |
|
|
*/
|
2035 |
|
|
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
|
2036 |
|
|
{
|
2037 |
|
|
/* Check the parameters */
|
2038 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
2039 |
|
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
|
2040 |
|
|
|
2041 |
|
|
/* Reset the IC2PSC Bits */
|
2042 |
|
|
TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
|
2043 |
|
|
/* Set the IC2PSC value */
|
2044 |
|
|
TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
|
2045 |
|
|
}
|
2046 |
|
|
|
2047 |
|
|
/**
|
2048 |
|
|
* @brief Sets the TIMx Input Capture 3 prescaler.
|
2049 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
2050 |
|
|
* @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
|
2051 |
|
|
* This parameter can be one of the following values:
|
2052 |
|
|
* @arg TIM_ICPSC_DIV1: no prescaler
|
2053 |
|
|
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
2054 |
|
|
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
2055 |
|
|
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
2056 |
|
|
* @retval None
|
2057 |
|
|
*/
|
2058 |
|
|
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
|
2059 |
|
|
{
|
2060 |
|
|
/* Check the parameters */
|
2061 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
2062 |
|
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
|
2063 |
|
|
|
2064 |
|
|
/* Reset the IC3PSC Bits */
|
2065 |
|
|
TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
|
2066 |
|
|
/* Set the IC3PSC value */
|
2067 |
|
|
TIMx->CCMR2 |= TIM_ICPSC;
|
2068 |
|
|
}
|
2069 |
|
|
|
2070 |
|
|
/**
|
2071 |
|
|
* @brief Sets the TIMx Input Capture 4 prescaler.
|
2072 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
2073 |
|
|
* @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
|
2074 |
|
|
* This parameter can be one of the following values:
|
2075 |
|
|
* @arg TIM_ICPSC_DIV1: no prescaler
|
2076 |
|
|
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
2077 |
|
|
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
2078 |
|
|
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
2079 |
|
|
* @retval None
|
2080 |
|
|
*/
|
2081 |
|
|
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
|
2082 |
|
|
{
|
2083 |
|
|
/* Check the parameters */
|
2084 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
2085 |
|
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
|
2086 |
|
|
|
2087 |
|
|
/* Reset the IC4PSC Bits */
|
2088 |
|
|
TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
|
2089 |
|
|
/* Set the IC4PSC value */
|
2090 |
|
|
TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
|
2091 |
|
|
}
|
2092 |
|
|
|
2093 |
|
|
/**
|
2094 |
|
|
* @brief Sets the TIMx Clock Division value.
|
2095 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
2096 |
|
|
* @param TIM_CKD: specifies the clock division value.
|
2097 |
|
|
* This parameter can be one of the following value:
|
2098 |
|
|
* @arg TIM_CKD_DIV1: TDTS = Tck_tim
|
2099 |
|
|
* @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
|
2100 |
|
|
* @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
|
2101 |
|
|
* @retval None
|
2102 |
|
|
*/
|
2103 |
|
|
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
|
2104 |
|
|
{
|
2105 |
|
|
/* Check the parameters */
|
2106 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
2107 |
|
|
assert_param(IS_TIM_CKD_DIV(TIM_CKD));
|
2108 |
|
|
|
2109 |
|
|
/* Reset the CKD Bits */
|
2110 |
|
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
|
2111 |
|
|
/* Set the CKD value */
|
2112 |
|
|
TIMx->CR1 |= TIM_CKD;
|
2113 |
|
|
}
|
2114 |
|
|
|
2115 |
|
|
/**
|
2116 |
|
|
* @brief Gets the TIMx Input Capture 1 value.
|
2117 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
2118 |
|
|
* @retval Capture Compare 1 Register value.
|
2119 |
|
|
|
2120 |
|
|
*/
|
2121 |
|
|
uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
|
2122 |
|
|
{
|
2123 |
|
|
/* Check the parameters */
|
2124 |
|
|
assert_param(IS_TIM_23491011_PERIPH(TIMx));
|
2125 |
|
|
|
2126 |
|
|
/* Get the Capture 1 Register value */
|
2127 |
|
|
return TIMx->CCR1;
|
2128 |
|
|
}
|
2129 |
|
|
|
2130 |
|
|
/**
|
2131 |
|
|
* @brief Gets the TIMx Input Capture 2 value.
|
2132 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
2133 |
|
|
* @retval Capture Compare 2 Register value.
|
2134 |
|
|
|
2135 |
|
|
*/
|
2136 |
|
|
uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
|
2137 |
|
|
{
|
2138 |
|
|
/* Check the parameters */
|
2139 |
|
|
assert_param(IS_TIM_2349_PERIPH(TIMx));
|
2140 |
|
|
|
2141 |
|
|
/* Get the Capture 2 Register value */
|
2142 |
|
|
return TIMx->CCR2;
|
2143 |
|
|
}
|
2144 |
|
|
|
2145 |
|
|
/**
|
2146 |
|
|
* @brief Gets the TIMx Input Capture 3 value.
|
2147 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
2148 |
|
|
* @retval Capture Compare 3 Register value.
|
2149 |
|
|
*/
|
2150 |
|
|
uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
|
2151 |
|
|
{
|
2152 |
|
|
/* Check the parameters */
|
2153 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
2154 |
|
|
|
2155 |
|
|
/* Get the Capture 3 Register value */
|
2156 |
|
|
return TIMx->CCR3;
|
2157 |
|
|
}
|
2158 |
|
|
|
2159 |
|
|
/**
|
2160 |
|
|
* @brief Gets the TIMx Input Capture 4 value.
|
2161 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
2162 |
|
|
* @retval Capture Compare 4 Register value.
|
2163 |
|
|
*/
|
2164 |
|
|
uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
|
2165 |
|
|
{
|
2166 |
|
|
/* Check the parameters */
|
2167 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
2168 |
|
|
|
2169 |
|
|
/* Get the Capture 4 Register value */
|
2170 |
|
|
return TIMx->CCR4;
|
2171 |
|
|
}
|
2172 |
|
|
|
2173 |
|
|
/**
|
2174 |
|
|
* @brief Gets the TIMx Counter value.
|
2175 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
2176 |
|
|
* @retval Counter Register value.
|
2177 |
|
|
*/
|
2178 |
|
|
uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
|
2179 |
|
|
{
|
2180 |
|
|
/* Check the parameters */
|
2181 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
2182 |
|
|
|
2183 |
|
|
/* Get the Counter Register value */
|
2184 |
|
|
return TIMx->CNT;
|
2185 |
|
|
}
|
2186 |
|
|
|
2187 |
|
|
/**
|
2188 |
|
|
* @brief Gets the TIMx Prescaler value.
|
2189 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
2190 |
|
|
* @retval Prescaler Register value.
|
2191 |
|
|
*/
|
2192 |
|
|
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
|
2193 |
|
|
{
|
2194 |
|
|
/* Check the parameters */
|
2195 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
2196 |
|
|
|
2197 |
|
|
/* Get the Prescaler Register value */
|
2198 |
|
|
return TIMx->PSC;
|
2199 |
|
|
}
|
2200 |
|
|
|
2201 |
|
|
/**
|
2202 |
|
|
* @brief Selects the OCReference Clear source.
|
2203 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
2204 |
|
|
* @param TIM_OCReferenceClear: specifies the OCReference Clear source.
|
2205 |
|
|
* This parameter can be one of the following values:
|
2206 |
|
|
* @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
|
2207 |
|
|
* @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
|
2208 |
|
|
* @retval None
|
2209 |
|
|
*/
|
2210 |
|
|
void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
|
2211 |
|
|
{
|
2212 |
|
|
/* Check the parameters */
|
2213 |
|
|
assert_param(IS_TIM_234_PERIPH(TIMx));
|
2214 |
|
|
assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
|
2215 |
|
|
|
2216 |
|
|
/* Set the TIM_OCReferenceClear source */
|
2217 |
|
|
TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
|
2218 |
|
|
TIMx->SMCR |= TIM_OCReferenceClear;
|
2219 |
|
|
}
|
2220 |
|
|
|
2221 |
|
|
/**
|
2222 |
|
|
* @brief Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities.
|
2223 |
|
|
* @param TIMx: where x can be 9, 10 or 11 to select the TIM peripheral.
|
2224 |
|
|
* @param TIM_Remap: specifies the TIM input reampping source.
|
2225 |
|
|
* This parameter can be one of the following values:
|
2226 |
|
|
* @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default)
|
2227 |
|
|
* @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.
|
2228 |
|
|
* @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default)
|
2229 |
|
|
* @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.
|
2230 |
|
|
* @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.
|
2231 |
|
|
* @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event.
|
2232 |
|
|
* @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default)
|
2233 |
|
|
* @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.
|
2234 |
|
|
* @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock.
|
2235 |
|
|
* @retval None
|
2236 |
|
|
*/
|
2237 |
|
|
void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
|
2238 |
|
|
{
|
2239 |
|
|
/* Check the parameters */
|
2240 |
|
|
assert_param(IS_TIM_91011_PERIPH(TIMx));
|
2241 |
|
|
assert_param(IS_TIM_REMAP(TIM_Remap));
|
2242 |
|
|
|
2243 |
|
|
/* Set the Timer remapping configuration */
|
2244 |
|
|
TIMx->OR = TIM_Remap;
|
2245 |
|
|
}
|
2246 |
|
|
|
2247 |
|
|
/**
|
2248 |
|
|
* @brief Checks whether the specified TIM flag is set or not.
|
2249 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
2250 |
|
|
* @param TIM_FLAG: specifies the flag to check.
|
2251 |
|
|
* This parameter can be one of the following values:
|
2252 |
|
|
* @arg TIM_FLAG_Update: TIM update Flag
|
2253 |
|
|
* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
|
2254 |
|
|
* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
|
2255 |
|
|
* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
|
2256 |
|
|
* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
|
2257 |
|
|
* @arg TIM_FLAG_Trigger: TIM Trigger Flag
|
2258 |
|
|
* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
|
2259 |
|
|
* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
|
2260 |
|
|
* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
|
2261 |
|
|
* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
|
2262 |
|
|
* @note
|
2263 |
|
|
* - TIM6 and TIM7 can have only one update flag.
|
2264 |
|
|
* - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,
|
2265 |
|
|
* TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags
|
2266 |
|
|
* - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags
|
2267 |
|
|
* @retval The new state of TIM_FLAG (SET or RESET).
|
2268 |
|
|
*/
|
2269 |
|
|
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
|
2270 |
|
|
{
|
2271 |
|
|
ITStatus bitstatus = RESET;
|
2272 |
|
|
|
2273 |
|
|
/* Check the parameters */
|
2274 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
2275 |
|
|
assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
|
2276 |
|
|
|
2277 |
|
|
if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
|
2278 |
|
|
{
|
2279 |
|
|
bitstatus = SET;
|
2280 |
|
|
}
|
2281 |
|
|
else
|
2282 |
|
|
{
|
2283 |
|
|
bitstatus = RESET;
|
2284 |
|
|
}
|
2285 |
|
|
return bitstatus;
|
2286 |
|
|
}
|
2287 |
|
|
|
2288 |
|
|
/**
|
2289 |
|
|
* @brief Clears the TIMx's pending flags.
|
2290 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
2291 |
|
|
* @param TIM_FLAG: specifies the flag bit to clear.
|
2292 |
|
|
* This parameter can be any combination of the following values:
|
2293 |
|
|
* @arg TIM_FLAG_Update: TIM update Flag
|
2294 |
|
|
* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
|
2295 |
|
|
* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
|
2296 |
|
|
* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
|
2297 |
|
|
* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
|
2298 |
|
|
* @arg TIM_FLAG_Trigger: TIM Trigger Flag
|
2299 |
|
|
* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
|
2300 |
|
|
* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
|
2301 |
|
|
* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
|
2302 |
|
|
* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
|
2303 |
|
|
* @note
|
2304 |
|
|
* - TIM6 and TIM7 can have only one update flag.
|
2305 |
|
|
* - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags
|
2306 |
|
|
* TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags
|
2307 |
|
|
* - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1
|
2308 |
|
|
* or TIM_FLAG_CC1OF flags
|
2309 |
|
|
* @retval None
|
2310 |
|
|
*/
|
2311 |
|
|
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
|
2312 |
|
|
{
|
2313 |
|
|
/* Check the parameters */
|
2314 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
2315 |
|
|
assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
|
2316 |
|
|
|
2317 |
|
|
/* Clear the flags */
|
2318 |
|
|
TIMx->SR = (uint16_t)~TIM_FLAG;
|
2319 |
|
|
}
|
2320 |
|
|
|
2321 |
|
|
/**
|
2322 |
|
|
* @brief Checks whether the TIM interrupt has occurred or not.
|
2323 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
2324 |
|
|
* @param TIM_IT: specifies the TIM interrupt source to check.
|
2325 |
|
|
* This parameter can be one of the following values:
|
2326 |
|
|
* @arg TIM_IT_Update: TIM update Interrupt source
|
2327 |
|
|
* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
|
2328 |
|
|
* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
|
2329 |
|
|
* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
|
2330 |
|
|
* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
|
2331 |
|
|
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
|
2332 |
|
|
* @note
|
2333 |
|
|
* - TIM6 and TIM7 can generate only an update interrupt.
|
2334 |
|
|
* - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,
|
2335 |
|
|
* interrupt and TIM_IT_Trigger interrupt.
|
2336 |
|
|
* - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1
|
2337 |
|
|
* interrupt
|
2338 |
|
|
* @retval The new state of the TIM_IT(SET or RESET).
|
2339 |
|
|
*/
|
2340 |
|
|
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
|
2341 |
|
|
{
|
2342 |
|
|
ITStatus bitstatus = RESET;
|
2343 |
|
|
uint16_t itstatus = 0x0, itenable = 0x0;
|
2344 |
|
|
|
2345 |
|
|
/* Check the parameters */
|
2346 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
2347 |
|
|
assert_param(IS_TIM_GET_IT(TIM_IT));
|
2348 |
|
|
|
2349 |
|
|
itstatus = TIMx->SR & TIM_IT;
|
2350 |
|
|
|
2351 |
|
|
itenable = TIMx->DIER & TIM_IT;
|
2352 |
|
|
if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
|
2353 |
|
|
{
|
2354 |
|
|
bitstatus = SET;
|
2355 |
|
|
}
|
2356 |
|
|
else
|
2357 |
|
|
{
|
2358 |
|
|
bitstatus = RESET;
|
2359 |
|
|
}
|
2360 |
|
|
return bitstatus;
|
2361 |
|
|
}
|
2362 |
|
|
|
2363 |
|
|
/**
|
2364 |
|
|
* @brief Clears the TIMx's interrupt pending bits.
|
2365 |
|
|
* @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
|
2366 |
|
|
* @param TIM_IT: specifies the pending bit to clear.
|
2367 |
|
|
* This parameter can be any combination of the following values:
|
2368 |
|
|
* @arg TIM_IT_Update: TIM update Interrupt source
|
2369 |
|
|
* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
|
2370 |
|
|
* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
|
2371 |
|
|
* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
|
2372 |
|
|
* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
|
2373 |
|
|
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
|
2374 |
|
|
* @note
|
2375 |
|
|
* - TIM6 and TIM7 can generate only an update interrupt.
|
2376 |
|
|
* - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,
|
2377 |
|
|
* and TIM_IT_Trigger interrupt.
|
2378 |
|
|
* - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1
|
2379 |
|
|
* interrupt
|
2380 |
|
|
* @retval None
|
2381 |
|
|
*/
|
2382 |
|
|
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
|
2383 |
|
|
{
|
2384 |
|
|
/* Check the parameters */
|
2385 |
|
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
2386 |
|
|
assert_param(IS_TIM_IT(TIM_IT));
|
2387 |
|
|
|
2388 |
|
|
/* Clear the IT pending Bit */
|
2389 |
|
|
TIMx->SR = (uint16_t)~TIM_IT;
|
2390 |
|
|
}
|
2391 |
|
|
|
2392 |
|
|
/**
|
2393 |
|
|
* @brief Configure the TI1 as Input.
|
2394 |
|
|
* @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
|
2395 |
|
|
* @param TIM_ICPolarity : The Input Polarity.
|
2396 |
|
|
* This parameter can be one of the following values:
|
2397 |
|
|
* @arg TIM_ICPolarity_Rising
|
2398 |
|
|
* @arg TIM_ICPolarity_Falling
|
2399 |
|
|
* @param TIM_ICSelection: specifies the input to be used.
|
2400 |
|
|
* This parameter can be one of the following values:
|
2401 |
|
|
* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
|
2402 |
|
|
* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
|
2403 |
|
|
* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
|
2404 |
|
|
* @param TIM_ICFilter: Specifies the Input Capture Filter.
|
2405 |
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
2406 |
|
|
* @retval None
|
2407 |
|
|
*/
|
2408 |
|
|
static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
|
2409 |
|
|
uint16_t TIM_ICFilter)
|
2410 |
|
|
{
|
2411 |
|
|
uint16_t tmpccmr1 = 0, tmpccer = 0;
|
2412 |
|
|
|
2413 |
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
2414 |
|
|
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
|
2415 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
2416 |
|
|
tmpccer = TIMx->CCER;
|
2417 |
|
|
/* Select the Input and set the filter */
|
2418 |
|
|
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
|
2419 |
|
|
tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
|
2420 |
|
|
/* Select the Polarity and set the CC1E Bit */
|
2421 |
|
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
|
2422 |
|
|
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
|
2423 |
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
2424 |
|
|
TIMx->CCMR1 = tmpccmr1;
|
2425 |
|
|
TIMx->CCER = tmpccer;
|
2426 |
|
|
}
|
2427 |
|
|
|
2428 |
|
|
/**
|
2429 |
|
|
* @brief Configure the TI2 as Input.
|
2430 |
|
|
* @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
|
2431 |
|
|
* @param TIM_ICPolarity : The Input Polarity.
|
2432 |
|
|
* This parameter can be one of the following values:
|
2433 |
|
|
* @arg TIM_ICPolarity_Rising
|
2434 |
|
|
* @arg TIM_ICPolarity_Falling
|
2435 |
|
|
* @param TIM_ICSelection: specifies the input to be used.
|
2436 |
|
|
* This parameter can be one of the following values:
|
2437 |
|
|
* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
|
2438 |
|
|
* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
|
2439 |
|
|
* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
|
2440 |
|
|
* @param TIM_ICFilter: Specifies the Input Capture Filter.
|
2441 |
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
2442 |
|
|
* @retval None
|
2443 |
|
|
*/
|
2444 |
|
|
static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
|
2445 |
|
|
uint16_t TIM_ICFilter)
|
2446 |
|
|
{
|
2447 |
|
|
uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
|
2448 |
|
|
|
2449 |
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
2450 |
|
|
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
|
2451 |
|
|
tmpccmr1 = TIMx->CCMR1;
|
2452 |
|
|
tmpccer = TIMx->CCER;
|
2453 |
|
|
tmp = (uint16_t)(TIM_ICPolarity << 4);
|
2454 |
|
|
/* Select the Input and set the filter */
|
2455 |
|
|
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
|
2456 |
|
|
tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
|
2457 |
|
|
tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
|
2458 |
|
|
/* Select the Polarity and set the CC2E Bit */
|
2459 |
|
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
|
2460 |
|
|
tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
|
2461 |
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
2462 |
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
2463 |
|
|
TIMx->CCER = tmpccer;
|
2464 |
|
|
}
|
2465 |
|
|
|
2466 |
|
|
/**
|
2467 |
|
|
* @brief Configure the TI3 as Input.
|
2468 |
|
|
* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
|
2469 |
|
|
* @param TIM_ICPolarity : The Input Polarity.
|
2470 |
|
|
* This parameter can be one of the following values:
|
2471 |
|
|
* @arg TIM_ICPolarity_Rising
|
2472 |
|
|
* @arg TIM_ICPolarity_Falling
|
2473 |
|
|
* @param TIM_ICSelection: specifies the input to be used.
|
2474 |
|
|
* This parameter can be one of the following values:
|
2475 |
|
|
* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
|
2476 |
|
|
* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
|
2477 |
|
|
* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
|
2478 |
|
|
* @param TIM_ICFilter: Specifies the Input Capture Filter.
|
2479 |
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
2480 |
|
|
* @retval None
|
2481 |
|
|
*/
|
2482 |
|
|
static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
|
2483 |
|
|
uint16_t TIM_ICFilter)
|
2484 |
|
|
{
|
2485 |
|
|
uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
|
2486 |
|
|
|
2487 |
|
|
/* Disable the Channel 3: Reset the CC3E Bit */
|
2488 |
|
|
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
|
2489 |
|
|
tmpccmr2 = TIMx->CCMR2;
|
2490 |
|
|
tmpccer = TIMx->CCER;
|
2491 |
|
|
tmp = (uint16_t)(TIM_ICPolarity << 8);
|
2492 |
|
|
/* Select the Input and set the filter */
|
2493 |
|
|
tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
|
2494 |
|
|
tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
|
2495 |
|
|
/* Select the Polarity and set the CC3E Bit */
|
2496 |
|
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
|
2497 |
|
|
tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
|
2498 |
|
|
/* Write to TIMx CCMR2 and CCER registers */
|
2499 |
|
|
TIMx->CCMR2 = tmpccmr2;
|
2500 |
|
|
TIMx->CCER = tmpccer;
|
2501 |
|
|
}
|
2502 |
|
|
|
2503 |
|
|
/**
|
2504 |
|
|
* @brief Configure the TI4 as Input.
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2505 |
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* @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
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2506 |
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* @param TIM_ICPolarity : The Input Polarity.
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2507 |
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* This parameter can be one of the following values:
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2508 |
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* @arg TIM_ICPolarity_Rising
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2509 |
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* @arg TIM_ICPolarity_Falling
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2510 |
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* @param TIM_ICSelection: specifies the input to be used.
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2511 |
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* This parameter can be one of the following values:
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2512 |
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* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
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2513 |
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* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
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2514 |
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* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
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2515 |
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* @param TIM_ICFilter: Specifies the Input Capture Filter.
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2516 |
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* This parameter must be a value between 0x00 and 0x0F.
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2517 |
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* @retval None
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2518 |
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*/
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2519 |
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static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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2520 |
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uint16_t TIM_ICFilter)
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2521 |
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{
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2522 |
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uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
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2523 |
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2524 |
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/* Disable the Channel 4: Reset the CC4E Bit */
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2525 |
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TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
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2526 |
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tmpccmr2 = TIMx->CCMR2;
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2527 |
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tmpccer = TIMx->CCER;
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2528 |
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tmp = (uint16_t)(TIM_ICPolarity << 12);
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2529 |
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/* Select the Input and set the filter */
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2530 |
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tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
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2531 |
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tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
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2532 |
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tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
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2533 |
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2534 |
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/* Select the Polarity and set the CC4E Bit */
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2535 |
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tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));
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2536 |
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tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
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2537 |
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/* Write to TIMx CCMR2 and CCER registers */
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2538 |
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TIMx->CCMR2 = tmpccmr2;
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2539 |
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TIMx->CCER = tmpccer ;
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2540 |
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}
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2541 |
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|
2542 |
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/**
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2543 |
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* @}
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2544 |
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*/
|
2545 |
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|
2546 |
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/**
|
2547 |
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* @}
|
2548 |
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*/
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2549 |
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|
2550 |
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/**
|
2551 |
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* @}
|
2552 |
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*/
|
2553 |
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|
2554 |
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/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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