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jeremybenn |
/**
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******************************************************************************
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* @file system_stm32l1xx.c
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* @author MCD Application Team
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* @version V1.0.0RC1
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* @date 07/02/2010
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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******************************************************************************
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32l1xx_system
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* @{
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*/
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/** @addtogroup STM32L1xx_System_Private_Includes
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* @{
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*/
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#include "stm32l1xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Defines
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* @{
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*/
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/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
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frequency (after reset the MSI is used as SYSCLK source)
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IMPORTANT NOTE:
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==============
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1. After each device reset the MSI is used as System clock source.
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2. Please make sure that the selected System clock doesn't exceed your device's
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maximum frequency.
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3. If none of the define below is enabled, the MSI (2MHz default) is used as
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System clock source.
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4. The System clock configuration functions provided within this file assume that:
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- For Ultra Low Power Medium Mensity devices an external 8MHz crystal is
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used to drive the System clock.
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If you are using different crystal you have to adapt those functions accordingly.
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*/
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/* #define SYSCLK_FREQ_MSI */
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#ifndef SYSCLK_FREQ_MSI
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/* #define SYSCLK_FREQ_HSI HSI_VALUE */
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/* #define SYSCLK_FREQ_HSE HSE_VALUE */
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/* #define SYSCLK_FREQ_4MHz 4000000 */
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/* #define SYSCLK_FREQ_8MHz 8000000 */
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/* #define SYSCLK_FREQ_16MHz 16000000 */
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#define SYSCLK_FREQ_32MHz 32000000
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#else
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/* #define SYSCLK_FREQ_MSI_64KHz 64000 */
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/* #define SYSCLK_FREQ_MSI_128KHz 128000 */
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/* #define SYSCLK_FREQ_MSI_256KHz 256000 */
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/* #define SYSCLK_FREQ_MSI_512KHz 512000 */
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/* #define SYSCLK_FREQ_MSI_1MHz 1000000 */
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/* #define SYSCLK_FREQ_MSI_2MHz 2000000 */
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/* #define SYSCLK_FREQ_MSI_4MHz 4000000 */
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#endif
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Variables
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* @{
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*/
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/*******************************************************************************
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* Clock Definitions
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*******************************************************************************/
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#ifndef SYSCLK_FREQ_MSI
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#ifdef SYSCLK_FREQ_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_HSI; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_4MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_4MHz; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_8MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_16MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_32MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_32MHz; /*!< System Clock Frequency (Core Clock) */
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#else /*!< MSI Selected as System Clock source */
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uint32_t SystemCoreClock = MSI_VALUE; /*!< System Clock Frequency (Core Clock) */
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#endif
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#else
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#ifdef SYSCLK_FREQ_MSI_64KHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_64KHz; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_MSI_128KHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_128KHz; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_MSI_256KHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_256KHz; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_MSI_512KHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_512KHz; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_MSI_1MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_1MHz; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_MSI_2MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_2MHz; /*!< System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_MSI_4MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_MSI_4MHz; /*!< System Clock Frequency (Core Clock) */
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#else
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uint32_t SystemCoreClock = MSI_VALUE; /*!< System Clock Frequency (Core Clock) */
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#endif
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#endif
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__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
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__I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
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* @{
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*/
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static void SetSysClock(void);
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#ifdef SYSCLK_FREQ_HSI
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static void SetSysClockToHSI(void);
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#elif defined SYSCLK_FREQ_HSE
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static void SetSysClockToHSE(void);
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#elif defined SYSCLK_FREQ_4MHz
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static void SetSysClockTo4(void);
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#elif defined SYSCLK_FREQ_8MHz
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static void SetSysClockTo8(void);
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#elif defined SYSCLK_FREQ_16MHz
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static void SetSysClockTo16(void);
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#elif defined SYSCLK_FREQ_32MHz
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static void SetSysClockTo32(void);
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#else
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static void SetSysClockToMSI(void);
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#endif
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemCoreClock variable
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* @note This function should be used only after reset.
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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{
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/*!< Set MSION bit */
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RCC->CR |= (uint32_t)0x00000100;
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/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
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RCC->CFGR &= (uint32_t)0x88FFC00C;
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/*!< Reset HSION, HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xEEFEFFFE;
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/*!< Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
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RCC->CFGR &= (uint32_t)0xFF02FFFF;
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/*!< Disable all interrupts */
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RCC->CIR = 0x00000000;
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/*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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/*!< Configure the Flash Latency cycles and enable prefetch buffer */
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SetSysClock();
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}
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/**
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* @brief Update SystemCoreClock according to Clock Register Values
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* @note None
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* MSI used as system clock */
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msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
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SystemCoreClock = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));
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break;
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case 0x04: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x08: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x0C: /* PLL used as system clock */
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/* Get PLL clock source and multiplication factor ----------------------*/
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pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
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plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
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pllmul = PLLMulTable[(pllmul >> 18)];
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plldiv = (plldiv >> 22) + 1;
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pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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if (pllsource == 0x00)
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{
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/* HSI oscillator clock selected as PLL clock entry */
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SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
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}
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else
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{
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/* HSE selected as PLL clock entry */
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SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
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}
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break;
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default:
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SystemCoreClock = MSI_VALUE;
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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* @param None
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* @retval None
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*/
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static void SetSysClock(void)
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{
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#ifdef SYSCLK_FREQ_HSI
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SetSysClockToHSI();
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#elif defined SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_4MHz
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SetSysClockTo4();
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#elif defined SYSCLK_FREQ_8MHz
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SetSysClockTo8();
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#elif defined SYSCLK_FREQ_16MHz
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SetSysClockTo16();
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#elif defined SYSCLK_FREQ_32MHz
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SetSysClockTo32();
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#else
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SetSysClockToMSI();
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#endif
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/* If none of the define above is enabled, the MSI (2MHz default) is used as
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System clock source (default after reset) */
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}
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#ifdef SYSCLK_FREQ_HSI
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/**
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* @brief Selects HSI as System clock source and configure HCLK, PCLK2
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* and PCLK1 prescalers.
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* @note This function should be used only after reset.
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* @param None
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* @retval None
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*/
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static void SetSysClockToHSI(void)
|
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{
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__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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/* Enable HSI */
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RCC->CR |= ((uint32_t)RCC_CR_HSION);
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/* Wait till HSI is ready and if Time out is reached exit */
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do
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{
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HSIStatus = RCC->CR & RCC_CR_HSIRDY;
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StartUpCounter++;
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} while((HSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
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{
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HSIStatus = (uint32_t)0x01;
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}
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else
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{
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HSIStatus = (uint32_t)0x00;
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}
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if (HSIStatus == (uint32_t)0x01)
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{
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/* Enable 64-bit access */
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FLASH->ACR |= FLASH_ACR_ACC64;
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/* Enable Prefetch Buffer */
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FLASH->ACR |= FLASH_ACR_PRFTEN;
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/* Flash 1 wait state */
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FLASH->ACR |= FLASH_ACR_LATENCY;
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/* Enable the PWR APB1 Clock */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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/* Select the Voltage Range 1 (1.8V) */
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PWR->CR = PWR_CR_VOS_0;
|
347 |
|
|
|
348 |
|
|
/* Wait Until the Voltage Regulator is ready */
|
349 |
|
|
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
|
350 |
|
|
{
|
351 |
|
|
}
|
352 |
|
|
|
353 |
|
|
/* HCLK = SYSCLK */
|
354 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
355 |
|
|
|
356 |
|
|
/* PCLK2 = HCLK */
|
357 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
358 |
|
|
|
359 |
|
|
/* PCLK1 = HCLK */
|
360 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
361 |
|
|
|
362 |
|
|
/* Select HSI as system clock source */
|
363 |
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
364 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
|
365 |
|
|
|
366 |
|
|
/* Wait till HSI is used as system clock source */
|
367 |
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
|
368 |
|
|
{
|
369 |
|
|
}
|
370 |
|
|
}
|
371 |
|
|
else
|
372 |
|
|
{
|
373 |
|
|
/* If HSI fails to start-up, the application will have wrong clock
|
374 |
|
|
configuration. User can add here some code to deal with this error */
|
375 |
|
|
}
|
376 |
|
|
}
|
377 |
|
|
|
378 |
|
|
#elif defined SYSCLK_FREQ_HSE
|
379 |
|
|
/**
|
380 |
|
|
* @brief Selects HSE as System clock source and configure HCLK, PCLK2
|
381 |
|
|
* and PCLK1 prescalers.
|
382 |
|
|
* @note This function should be used only after reset.
|
383 |
|
|
* @param None
|
384 |
|
|
* @retval None
|
385 |
|
|
*/
|
386 |
|
|
static void SetSysClockToHSE(void)
|
387 |
|
|
{
|
388 |
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
389 |
|
|
|
390 |
|
|
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
391 |
|
|
/* Enable HSE */
|
392 |
|
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
393 |
|
|
|
394 |
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
395 |
|
|
do
|
396 |
|
|
{
|
397 |
|
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
398 |
|
|
StartUpCounter++;
|
399 |
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
400 |
|
|
|
401 |
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
402 |
|
|
{
|
403 |
|
|
HSEStatus = (uint32_t)0x01;
|
404 |
|
|
}
|
405 |
|
|
else
|
406 |
|
|
{
|
407 |
|
|
HSEStatus = (uint32_t)0x00;
|
408 |
|
|
}
|
409 |
|
|
|
410 |
|
|
if (HSEStatus == (uint32_t)0x01)
|
411 |
|
|
{
|
412 |
|
|
/* Flash 0 wait state */
|
413 |
|
|
FLASH->ACR &= ~FLASH_ACR_LATENCY;
|
414 |
|
|
|
415 |
|
|
/* Disable Prefetch Buffer */
|
416 |
|
|
FLASH->ACR &= ~FLASH_ACR_PRFTEN;
|
417 |
|
|
|
418 |
|
|
/* Disable 64-bit access */
|
419 |
|
|
FLASH->ACR &= ~FLASH_ACR_ACC64;
|
420 |
|
|
|
421 |
|
|
/* Enable the PWR APB1 Clock */
|
422 |
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
423 |
|
|
|
424 |
|
|
/* Select the Voltage Range 2 (1.5V) */
|
425 |
|
|
PWR->CR = PWR_CR_VOS_1;
|
426 |
|
|
|
427 |
|
|
/* Wait Until the Voltage Regulator is ready */
|
428 |
|
|
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
|
429 |
|
|
{
|
430 |
|
|
}
|
431 |
|
|
|
432 |
|
|
/* HCLK = SYSCLK */
|
433 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
434 |
|
|
|
435 |
|
|
/* PCLK2 = HCLK */
|
436 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
437 |
|
|
|
438 |
|
|
/* PCLK1 = HCLK */
|
439 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
440 |
|
|
|
441 |
|
|
/* Select HSE as system clock source */
|
442 |
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
443 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
|
444 |
|
|
|
445 |
|
|
/* Wait till HSE is used as system clock source */
|
446 |
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
447 |
|
|
{
|
448 |
|
|
}
|
449 |
|
|
}
|
450 |
|
|
else
|
451 |
|
|
{
|
452 |
|
|
/* If HSE fails to start-up, the application will have wrong clock
|
453 |
|
|
configuration. User can add here some code to deal with this error */
|
454 |
|
|
}
|
455 |
|
|
}
|
456 |
|
|
#elif defined SYSCLK_FREQ_4MHz
|
457 |
|
|
/**
|
458 |
|
|
* @brief Sets System clock frequency to 4MHz and configure HCLK, PCLK2
|
459 |
|
|
* and PCLK1 prescalers.
|
460 |
|
|
* @note This function should be used only after reset.
|
461 |
|
|
* @param None
|
462 |
|
|
* @retval None
|
463 |
|
|
*/
|
464 |
|
|
static void SetSysClockTo4(void)
|
465 |
|
|
{
|
466 |
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
467 |
|
|
|
468 |
|
|
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
469 |
|
|
/* Enable HSE */
|
470 |
|
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
471 |
|
|
|
472 |
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
473 |
|
|
do
|
474 |
|
|
{
|
475 |
|
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
476 |
|
|
StartUpCounter++;
|
477 |
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
478 |
|
|
|
479 |
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
480 |
|
|
{
|
481 |
|
|
HSEStatus = (uint32_t)0x01;
|
482 |
|
|
}
|
483 |
|
|
else
|
484 |
|
|
{
|
485 |
|
|
HSEStatus = (uint32_t)0x00;
|
486 |
|
|
}
|
487 |
|
|
|
488 |
|
|
if (HSEStatus == (uint32_t)0x01)
|
489 |
|
|
{
|
490 |
|
|
/* Flash 0 wait state */
|
491 |
|
|
FLASH->ACR &= ~FLASH_ACR_LATENCY;
|
492 |
|
|
|
493 |
|
|
/* Disable Prefetch Buffer */
|
494 |
|
|
FLASH->ACR &= ~FLASH_ACR_PRFTEN;
|
495 |
|
|
|
496 |
|
|
/* Disable 64-bit access */
|
497 |
|
|
FLASH->ACR &= ~FLASH_ACR_ACC64;
|
498 |
|
|
|
499 |
|
|
/* Enable the PWR APB1 Clock */
|
500 |
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
501 |
|
|
|
502 |
|
|
/* Select the Voltage Range 2 (1.5V) */
|
503 |
|
|
PWR->CR = PWR_CR_VOS_1;
|
504 |
|
|
|
505 |
|
|
/* Wait Until the Voltage Regulator is ready */
|
506 |
|
|
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
|
507 |
|
|
{
|
508 |
|
|
}
|
509 |
|
|
|
510 |
|
|
/* HCLK = SYSCLK */
|
511 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;
|
512 |
|
|
|
513 |
|
|
/* PCLK2 = HCLK */
|
514 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
515 |
|
|
|
516 |
|
|
/* PCLK1 = HCLK */
|
517 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
518 |
|
|
|
519 |
|
|
/* Select HSE as system clock source */
|
520 |
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
521 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
|
522 |
|
|
|
523 |
|
|
/* Wait till HSE is used as system clock source */
|
524 |
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
525 |
|
|
{
|
526 |
|
|
}
|
527 |
|
|
}
|
528 |
|
|
else
|
529 |
|
|
{
|
530 |
|
|
/* If HSE fails to start-up, the application will have wrong clock
|
531 |
|
|
configuration. User can add here some code to deal with this error */
|
532 |
|
|
}
|
533 |
|
|
}
|
534 |
|
|
|
535 |
|
|
#elif defined SYSCLK_FREQ_8MHz
|
536 |
|
|
/**
|
537 |
|
|
* @brief Sets System clock frequency to 8MHz and configure HCLK, PCLK2
|
538 |
|
|
* and PCLK1 prescalers.
|
539 |
|
|
* @note This function should be used only after reset.
|
540 |
|
|
* @param None
|
541 |
|
|
* @retval None
|
542 |
|
|
*/
|
543 |
|
|
static void SetSysClockTo8(void)
|
544 |
|
|
{
|
545 |
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
546 |
|
|
|
547 |
|
|
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
548 |
|
|
/* Enable HSE */
|
549 |
|
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
550 |
|
|
|
551 |
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
552 |
|
|
do
|
553 |
|
|
{
|
554 |
|
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
555 |
|
|
StartUpCounter++;
|
556 |
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
557 |
|
|
|
558 |
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
559 |
|
|
{
|
560 |
|
|
HSEStatus = (uint32_t)0x01;
|
561 |
|
|
}
|
562 |
|
|
else
|
563 |
|
|
{
|
564 |
|
|
HSEStatus = (uint32_t)0x00;
|
565 |
|
|
}
|
566 |
|
|
|
567 |
|
|
if (HSEStatus == (uint32_t)0x01)
|
568 |
|
|
{
|
569 |
|
|
/* Flash 0 wait state */
|
570 |
|
|
FLASH->ACR &= ~FLASH_ACR_LATENCY;
|
571 |
|
|
|
572 |
|
|
/* Disable Prefetch Buffer */
|
573 |
|
|
FLASH->ACR &= ~FLASH_ACR_PRFTEN;
|
574 |
|
|
|
575 |
|
|
/* Disable 64-bit access */
|
576 |
|
|
FLASH->ACR &= ~FLASH_ACR_ACC64;
|
577 |
|
|
|
578 |
|
|
/* Enable the PWR APB1 Clock */
|
579 |
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
580 |
|
|
|
581 |
|
|
/* Select the Voltage Range 2 (1.5V) */
|
582 |
|
|
PWR->CR = PWR_CR_VOS_1;
|
583 |
|
|
|
584 |
|
|
/* Wait Until the Voltage Regulator is ready */
|
585 |
|
|
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
|
586 |
|
|
{
|
587 |
|
|
}
|
588 |
|
|
|
589 |
|
|
/* HCLK = SYSCLK */
|
590 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
591 |
|
|
|
592 |
|
|
/* PCLK2 = HCLK */
|
593 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
594 |
|
|
|
595 |
|
|
/* PCLK1 = HCLK */
|
596 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
597 |
|
|
|
598 |
|
|
/* Select HSE as system clock source */
|
599 |
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
600 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
|
601 |
|
|
|
602 |
|
|
/* Wait till HSE is used as system clock source */
|
603 |
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
604 |
|
|
{
|
605 |
|
|
}
|
606 |
|
|
}
|
607 |
|
|
else
|
608 |
|
|
{
|
609 |
|
|
/* If HSE fails to start-up, the application will have wrong clock
|
610 |
|
|
configuration. User can add here some code to deal with this error */
|
611 |
|
|
}
|
612 |
|
|
}
|
613 |
|
|
|
614 |
|
|
#elif defined SYSCLK_FREQ_16MHz
|
615 |
|
|
/**
|
616 |
|
|
* @brief Sets System clock frequency to 16MHz and configure HCLK, PCLK2
|
617 |
|
|
* and PCLK1 prescalers.
|
618 |
|
|
* @note This function should be used only after reset.
|
619 |
|
|
* @param None
|
620 |
|
|
* @retval None
|
621 |
|
|
*/
|
622 |
|
|
static void SetSysClockTo16(void)
|
623 |
|
|
{
|
624 |
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
625 |
|
|
|
626 |
|
|
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
627 |
|
|
/* Enable HSE */
|
628 |
|
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
629 |
|
|
|
630 |
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
631 |
|
|
do
|
632 |
|
|
{
|
633 |
|
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
634 |
|
|
StartUpCounter++;
|
635 |
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
636 |
|
|
|
637 |
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
638 |
|
|
{
|
639 |
|
|
HSEStatus = (uint32_t)0x01;
|
640 |
|
|
}
|
641 |
|
|
else
|
642 |
|
|
{
|
643 |
|
|
HSEStatus = (uint32_t)0x00;
|
644 |
|
|
}
|
645 |
|
|
|
646 |
|
|
if (HSEStatus == (uint32_t)0x01)
|
647 |
|
|
{
|
648 |
|
|
/* Enable 64-bit access */
|
649 |
|
|
FLASH->ACR |= FLASH_ACR_ACC64;
|
650 |
|
|
|
651 |
|
|
/* Enable Prefetch Buffer */
|
652 |
|
|
FLASH->ACR |= FLASH_ACR_PRFTEN;
|
653 |
|
|
|
654 |
|
|
/* Flash 1 wait state */
|
655 |
|
|
FLASH->ACR |= FLASH_ACR_LATENCY;
|
656 |
|
|
|
657 |
|
|
/* Enable the PWR APB1 Clock */
|
658 |
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
659 |
|
|
|
660 |
|
|
/* Select the Voltage Range 2 (1.5V) */
|
661 |
|
|
PWR->CR = PWR_CR_VOS_1;
|
662 |
|
|
|
663 |
|
|
/* Wait Until the Voltage Regulator is ready */
|
664 |
|
|
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
|
665 |
|
|
{
|
666 |
|
|
}
|
667 |
|
|
|
668 |
|
|
/* HCLK = SYSCLK */
|
669 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;
|
670 |
|
|
|
671 |
|
|
/* PCLK2 = HCLK */
|
672 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
673 |
|
|
|
674 |
|
|
/* PCLK1 = HCLK */
|
675 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
676 |
|
|
|
677 |
|
|
/* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */
|
678 |
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
|
679 |
|
|
RCC_CFGR_PLLDIV));
|
680 |
|
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
|
681 |
|
|
|
682 |
|
|
/* Enable PLL */
|
683 |
|
|
RCC->CR |= RCC_CR_PLLON;
|
684 |
|
|
|
685 |
|
|
/* Wait till PLL is ready */
|
686 |
|
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
687 |
|
|
{
|
688 |
|
|
}
|
689 |
|
|
|
690 |
|
|
/* Select PLL as system clock source */
|
691 |
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
692 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
693 |
|
|
|
694 |
|
|
/* Wait till PLL is used as system clock source */
|
695 |
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)
|
696 |
|
|
{
|
697 |
|
|
}
|
698 |
|
|
}
|
699 |
|
|
else
|
700 |
|
|
{
|
701 |
|
|
/* If HSE fails to start-up, the application will have wrong clock
|
702 |
|
|
configuration. User can add here some code to deal with this error */
|
703 |
|
|
}
|
704 |
|
|
}
|
705 |
|
|
|
706 |
|
|
#elif defined SYSCLK_FREQ_32MHz
|
707 |
|
|
/**
|
708 |
|
|
* @brief Sets System clock frequency to 32MHz and configure HCLK, PCLK2
|
709 |
|
|
* and PCLK1 prescalers.
|
710 |
|
|
* @note This function should be used only after reset.
|
711 |
|
|
* @param None
|
712 |
|
|
* @retval None
|
713 |
|
|
*/
|
714 |
|
|
static void SetSysClockTo32(void)
|
715 |
|
|
{
|
716 |
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
717 |
|
|
|
718 |
|
|
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
719 |
|
|
/* Enable HSE */
|
720 |
|
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
721 |
|
|
|
722 |
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
723 |
|
|
do
|
724 |
|
|
{
|
725 |
|
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
726 |
|
|
StartUpCounter++;
|
727 |
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
728 |
|
|
|
729 |
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
730 |
|
|
{
|
731 |
|
|
HSEStatus = (uint32_t)0x01;
|
732 |
|
|
}
|
733 |
|
|
else
|
734 |
|
|
{
|
735 |
|
|
HSEStatus = (uint32_t)0x00;
|
736 |
|
|
}
|
737 |
|
|
|
738 |
|
|
if (HSEStatus == (uint32_t)0x01)
|
739 |
|
|
{
|
740 |
|
|
/* Enable 64-bit access */
|
741 |
|
|
FLASH->ACR |= FLASH_ACR_ACC64;
|
742 |
|
|
|
743 |
|
|
/* Enable Prefetch Buffer */
|
744 |
|
|
FLASH->ACR |= FLASH_ACR_PRFTEN;
|
745 |
|
|
|
746 |
|
|
/* Flash 1 wait state */
|
747 |
|
|
FLASH->ACR |= FLASH_ACR_LATENCY;
|
748 |
|
|
|
749 |
|
|
/* Enable the PWR APB1 Clock */
|
750 |
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
751 |
|
|
|
752 |
|
|
/* Select the Voltage Range 1 (1.8V) */
|
753 |
|
|
PWR->CR = PWR_CR_VOS_0;
|
754 |
|
|
|
755 |
|
|
/* Wait Until the Voltage Regulator is ready */
|
756 |
|
|
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
|
757 |
|
|
{
|
758 |
|
|
}
|
759 |
|
|
|
760 |
|
|
/* HCLK = SYSCLK */
|
761 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
762 |
|
|
|
763 |
|
|
/* PCLK2 = HCLK */
|
764 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
765 |
|
|
|
766 |
|
|
/* PCLK1 = HCLK */
|
767 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
768 |
|
|
|
769 |
|
|
/* PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */
|
770 |
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
|
771 |
|
|
RCC_CFGR_PLLDIV));
|
772 |
|
|
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
|
773 |
|
|
|
774 |
|
|
/* Enable PLL */
|
775 |
|
|
RCC->CR |= RCC_CR_PLLON;
|
776 |
|
|
|
777 |
|
|
/* Wait till PLL is ready */
|
778 |
|
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
779 |
|
|
{
|
780 |
|
|
}
|
781 |
|
|
|
782 |
|
|
/* Select PLL as system clock source */
|
783 |
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
784 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
785 |
|
|
|
786 |
|
|
/* Wait till PLL is used as system clock source */
|
787 |
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)
|
788 |
|
|
{
|
789 |
|
|
}
|
790 |
|
|
}
|
791 |
|
|
else
|
792 |
|
|
{
|
793 |
|
|
/* If HSE fails to start-up, the application will have wrong clock
|
794 |
|
|
configuration. User can add here some code to deal with this error */
|
795 |
|
|
}
|
796 |
|
|
}
|
797 |
|
|
|
798 |
|
|
#else
|
799 |
|
|
/**
|
800 |
|
|
* @brief Selects MSI as System clock source and configure HCLK, PCLK2
|
801 |
|
|
* and PCLK1 prescalers.
|
802 |
|
|
* @note This function should be used only after reset.
|
803 |
|
|
* @param None
|
804 |
|
|
* @retval None
|
805 |
|
|
*/
|
806 |
|
|
static void SetSysClockToMSI(void)
|
807 |
|
|
{
|
808 |
|
|
__IO uint32_t StartUpCounter = 0, MSIStatus = 0;
|
809 |
|
|
|
810 |
|
|
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
811 |
|
|
/* Enable MSI */
|
812 |
|
|
RCC->CR |= ((uint32_t)RCC_CR_MSION);
|
813 |
|
|
|
814 |
|
|
/* Wait till MSI is ready and if Time out is reached exit */
|
815 |
|
|
do
|
816 |
|
|
{
|
817 |
|
|
MSIStatus = RCC->CR & RCC_CR_MSIRDY;
|
818 |
|
|
StartUpCounter++;
|
819 |
|
|
} while((MSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
820 |
|
|
|
821 |
|
|
if ((RCC->CR & RCC_CR_MSIRDY) != RESET)
|
822 |
|
|
{
|
823 |
|
|
MSIStatus = (uint32_t)0x01;
|
824 |
|
|
}
|
825 |
|
|
else
|
826 |
|
|
{
|
827 |
|
|
MSIStatus = (uint32_t)0x00;
|
828 |
|
|
}
|
829 |
|
|
|
830 |
|
|
if (MSIStatus == (uint32_t)0x01)
|
831 |
|
|
{
|
832 |
|
|
#ifdef SYSCLK_FREQ_MSI
|
833 |
|
|
#ifdef SYSCLK_FREQ_MSI_4MHz
|
834 |
|
|
/* Enable 64-bit access */
|
835 |
|
|
FLASH->ACR |= FLASH_ACR_ACC64;
|
836 |
|
|
|
837 |
|
|
/* Enable Prefetch Buffer */
|
838 |
|
|
FLASH->ACR |= FLASH_ACR_PRFTEN;
|
839 |
|
|
|
840 |
|
|
/* Flash 1 wait state */
|
841 |
|
|
FLASH->ACR |= FLASH_ACR_LATENCY;
|
842 |
|
|
#else
|
843 |
|
|
/* Flash 0 wait state */
|
844 |
|
|
FLASH->ACR &= ~FLASH_ACR_LATENCY;
|
845 |
|
|
|
846 |
|
|
/* Disable Prefetch Buffer */
|
847 |
|
|
FLASH->ACR &= ~FLASH_ACR_PRFTEN;
|
848 |
|
|
|
849 |
|
|
/* Disable 64-bit access */
|
850 |
|
|
FLASH->ACR &= ~FLASH_ACR_ACC64;
|
851 |
|
|
#endif
|
852 |
|
|
#endif
|
853 |
|
|
/* Enable the PWR APB1 Clock */
|
854 |
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
855 |
|
|
|
856 |
|
|
/* Select the Voltage Range 3 (1.2V) */
|
857 |
|
|
PWR->CR = PWR_CR_VOS;
|
858 |
|
|
|
859 |
|
|
/* Wait Until the Voltage Regulator is ready */
|
860 |
|
|
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
|
861 |
|
|
{
|
862 |
|
|
}
|
863 |
|
|
|
864 |
|
|
/* HCLK = SYSCLK */
|
865 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
866 |
|
|
|
867 |
|
|
/* PCLK2 = HCLK */
|
868 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
869 |
|
|
|
870 |
|
|
/* PCLK1 = HCLK */
|
871 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
872 |
|
|
|
873 |
|
|
#ifdef SYSCLK_FREQ_MSI
|
874 |
|
|
#ifdef SYSCLK_FREQ_MSI_64KHz
|
875 |
|
|
/* Set MSI clock range */
|
876 |
|
|
RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
|
877 |
|
|
RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_64KHz;
|
878 |
|
|
#elif defined SYSCLK_FREQ_MSI_128KHz
|
879 |
|
|
/* Set MSI clock range */
|
880 |
|
|
RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
|
881 |
|
|
RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_128KHz;
|
882 |
|
|
#elif defined SYSCLK_FREQ_MSI_256KHz
|
883 |
|
|
/* Set MSI clock range */
|
884 |
|
|
RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
|
885 |
|
|
RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_256KHz;
|
886 |
|
|
#elif defined SYSCLK_FREQ_MSI_512KHz
|
887 |
|
|
/* Set MSI clock range */
|
888 |
|
|
RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
|
889 |
|
|
RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_512KHz;
|
890 |
|
|
#elif defined SYSCLK_FREQ_MSI_1MHz
|
891 |
|
|
/* Set MSI clock range */
|
892 |
|
|
RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
|
893 |
|
|
RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_1MHz;
|
894 |
|
|
#elif defined SYSCLK_FREQ_MSI_2MHz
|
895 |
|
|
/* Set MSI clock range */
|
896 |
|
|
RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
|
897 |
|
|
RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_2MHz;
|
898 |
|
|
#elif defined SYSCLK_FREQ_MSI_4MHz
|
899 |
|
|
/* Set MSI clock range */
|
900 |
|
|
RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));
|
901 |
|
|
RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_4MHz;
|
902 |
|
|
#endif
|
903 |
|
|
#endif
|
904 |
|
|
|
905 |
|
|
/* Select MSI as system clock source */
|
906 |
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
907 |
|
|
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_MSI;
|
908 |
|
|
|
909 |
|
|
/* Wait till MSI is used as system clock source */
|
910 |
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x00)
|
911 |
|
|
{
|
912 |
|
|
}
|
913 |
|
|
}
|
914 |
|
|
else
|
915 |
|
|
{
|
916 |
|
|
/* If MSI fails to start-up, the application will have wrong clock
|
917 |
|
|
configuration. User can add here some code to deal with this error */
|
918 |
|
|
}
|
919 |
|
|
}
|
920 |
|
|
#endif
|
921 |
|
|
|
922 |
|
|
/**
|
923 |
|
|
* @}
|
924 |
|
|
*/
|
925 |
|
|
|
926 |
|
|
/**
|
927 |
|
|
* @}
|
928 |
|
|
*/
|
929 |
|
|
|
930 |
|
|
/**
|
931 |
|
|
* @}
|
932 |
|
|
*/
|
933 |
|
|
|
934 |
|
|
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|