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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF51CN128_CodeWarrior/] [Sources/] [eth_phy.h] - Blame information for rev 866

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/*!
 * \file    eth.h
 * \brief   Definitions for Ethernet Physical Layer Interface
 * \version $Revision: 2 $
 * \author  Michael Norman
 */
 
#ifndef _ETH_PHY_H
#define _ETH_PHY_H
 
/*******************************************************************/
 
/* MII Register Addresses */
#define PHY_BMCR                                    (0x00)
#define PHY_BMSR                    (0x01)
#define PHY_PHYIDR1                                 (0x02)
#define PHY_PHYIDR2                                 (0x03)
#define PHY_ANAR                                    (0x04)
#define PHY_ANLPAR                          (0x05)
 
/* Bit definitions and macros for PHY_CTRL */
#define PHY_BMCR_RESET                  (0x8000)
#define PHY_BMCR_LOOP                       (0x4000)
#define PHY_BMCR_SPEED                  (0x2000)
#define PHY_BMCR_AN_ENABLE                  (0x1000)
#define PHY_BMCR_POWERDOWN          (0x0800)
#define PHY_BMCR_ISOLATE                (0x0400)
#define PHY_BMCR_AN_RESTART             (0x0200)
#define PHY_BMCR_FDX                        (0x0100)
#define PHY_BMCR_COL_TEST               (0x0080)
 
/* Bit definitions and macros for PHY_STAT */
#define PHY_BMSR_100BT4             (0x8000)
#define PHY_BMSR_100BTX_FDX         (0x4000)
#define PHY_BMSR_100BTX             (0x2000)
#define PHY_BMSR_10BT_FDX           (0x1000)
#define PHY_BMSR_10BT               (0x0800)
#define PHY_BMSR_NO_PREAMBLE        (0x0040)
#define PHY_BMSR_AN_COMPLETE        (0x0020)
#define PHY_BMSR_REMOTE_FAULT       (0x0010)
#define PHY_BMSR_AN_ABILITY         (0x0008)
#define PHY_BMSR_LINK               (0x0004)
#define PHY_BMSR_JABBER             (0x0002)
#define PHY_BMSR_EXTENDED           (0x0001)
 
/* Bit definitions and macros for PHY_AN_ADV */
#define PHY_ANAR_NEXT_PAGE          (0x8001)
#define PHY_ANAR_REM_FAULT              (0x2001)
#define PHY_ANAR_PAUSE                  (0x0401)
#define PHY_ANAR_100BT4                 (0x0201)
#define PHY_ANAR_100BTX_FDX             (0x0101)
#define PHY_ANAR_100BTX                 (0x0081)
#define PHY_ANAR_10BT_FDX                   (0x0041)
#define PHY_ANAR_10BT                   (0x0021)
#define PHY_ANAR_802_3                  (0x0001)
 
/* Bit definitions and macros for PHY_AN_LINK_PAR */
#define PHY_ANLPAR_NEXT_PAGE        (0x8000)
#define PHY_ANLPAR_ACK              (0x4000)
#define PHY_ANLPAR_REM_FAULT        (0x2000)
#define PHY_ANLPAR_PAUSE                    (0x0400)
#define PHY_ANLPAR_100BT4                   (0x0200)
#define PHY_ANLPAR_100BTX_FDX       (0x0100)
#define PHY_ANLPAR_100BTX                   (0x0080)
#define PHY_ANLPAR_10BTX_FDX        (0x0040)
#define PHY_ANLPAR_10BT                 (0x0020)
 
/*******************************************************************/
 
#endif  /* _ETH_PHY_H */

Line No.	Rev	Author	Line
1	578	jeremybenn	`/*!`
2			`* \file eth.h`
3			`* \brief Definitions for Ethernet Physical Layer Interface`
4			`* \version $Revision: 2 $`
5			`* \author Michael Norman`
6			`*/`
7
8			`#ifndef _ETH_PHY_H`
9			`#define _ETH_PHY_H`
10
11			`/*******************************************************************/`
12
13			`/* MII Register Addresses */`
14			`#define PHY_BMCR (0x00)`
15			`#define PHY_BMSR (0x01)`
16			`#define PHY_PHYIDR1 (0x02)`
17			`#define PHY_PHYIDR2 (0x03)`
18			`#define PHY_ANAR (0x04)`
19			`#define PHY_ANLPAR (0x05)`
20
21			`/* Bit definitions and macros for PHY_CTRL */`
22			`#define PHY_BMCR_RESET (0x8000)`
23			`#define PHY_BMCR_LOOP (0x4000)`
24			`#define PHY_BMCR_SPEED (0x2000)`
25			`#define PHY_BMCR_AN_ENABLE (0x1000)`
26			`#define PHY_BMCR_POWERDOWN (0x0800)`
27			`#define PHY_BMCR_ISOLATE (0x0400)`
28			`#define PHY_BMCR_AN_RESTART (0x0200)`
29			`#define PHY_BMCR_FDX (0x0100)`
30			`#define PHY_BMCR_COL_TEST (0x0080)`
31
32			`/* Bit definitions and macros for PHY_STAT */`
33			`#define PHY_BMSR_100BT4 (0x8000)`
34			`#define PHY_BMSR_100BTX_FDX (0x4000)`
35			`#define PHY_BMSR_100BTX (0x2000)`
36			`#define PHY_BMSR_10BT_FDX (0x1000)`
37			`#define PHY_BMSR_10BT (0x0800)`
38			`#define PHY_BMSR_NO_PREAMBLE (0x0040)`
39			`#define PHY_BMSR_AN_COMPLETE (0x0020)`
40			`#define PHY_BMSR_REMOTE_FAULT (0x0010)`
41			`#define PHY_BMSR_AN_ABILITY (0x0008)`
42			`#define PHY_BMSR_LINK (0x0004)`
43			`#define PHY_BMSR_JABBER (0x0002)`
44			`#define PHY_BMSR_EXTENDED (0x0001)`
45
46			`/* Bit definitions and macros for PHY_AN_ADV */`
47			`#define PHY_ANAR_NEXT_PAGE (0x8001)`
48			`#define PHY_ANAR_REM_FAULT (0x2001)`
49			`#define PHY_ANAR_PAUSE (0x0401)`
50			`#define PHY_ANAR_100BT4 (0x0201)`
51			`#define PHY_ANAR_100BTX_FDX (0x0101)`
52			`#define PHY_ANAR_100BTX (0x0081)`
53			`#define PHY_ANAR_10BT_FDX (0x0041)`
54			`#define PHY_ANAR_10BT (0x0021)`
55			`#define PHY_ANAR_802_3 (0x0001)`
56
57			`/* Bit definitions and macros for PHY_AN_LINK_PAR */`
58			`#define PHY_ANLPAR_NEXT_PAGE (0x8000)`
59			`#define PHY_ANLPAR_ACK (0x4000)`
60			`#define PHY_ANLPAR_REM_FAULT (0x2000)`
61			`#define PHY_ANLPAR_PAUSE (0x0400)`
62			`#define PHY_ANLPAR_100BT4 (0x0200)`
63			`#define PHY_ANLPAR_100BTX_FDX (0x0100)`
64			`#define PHY_ANLPAR_100BTX (0x0080)`
65			`#define PHY_ANLPAR_10BTX_FDX (0x0040)`
66			`#define PHY_ANLPAR_10BT (0x0020)`
67
68			`/*******************************************************************/`
69
70			`#endif /* _ETH_PHY_H */`

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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF51CN128_CodeWarrior/] [Sources/] [eth_phy.h] - Blame information for rev 866