OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF51CN128_CodeWarrior/] [Sources/] [main.c] - Blame information for rev 578

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 jeremybenn
/*
2
    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
3
 
4
    ***************************************************************************
5
    *                                                                         *
6
    * If you are:                                                             *
7
    *                                                                         *
8
    *    + New to FreeRTOS,                                                   *
9
    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
10
    *    + Looking for basic training,                                        *
11
    *    + Wanting to improve your FreeRTOS skills and productivity           *
12
    *                                                                         *
13
    * then take a look at the FreeRTOS books - available as PDF or paperback  *
14
    *                                                                         *
15
    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
16
    *                  http://www.FreeRTOS.org/Documentation                  *
17
    *                                                                         *
18
    * A pdf reference manual is also available.  Both are usually delivered   *
19
    * to your inbox within 20 minutes to two hours when purchased between 8am *
20
    * and 8pm GMT (although please allow up to 24 hours in case of            *
21
    * exceptional circumstances).  Thank you for your support!                *
22
    *                                                                         *
23
    ***************************************************************************
24
 
25
    This file is part of the FreeRTOS distribution.
26
 
27
    FreeRTOS is free software; you can redistribute it and/or modify it under
28
    the terms of the GNU General Public License (version 2) as published by the
29
    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
30
    ***NOTE*** The exception to the GPL is included to allow you to distribute
31
    a combined work that includes FreeRTOS without being obliged to provide the
32
    source code for proprietary components outside of the FreeRTOS kernel.
33
    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
34
    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
36
    more details. You should have received a copy of the GNU General Public
37
    License and the FreeRTOS license exception along with FreeRTOS; if not it
38
    can be viewed here: http://www.freertos.org/a00114.html and also obtained
39
    by writing to Richard Barry, contact details for whom are available on the
40
    FreeRTOS WEB site.
41
 
42
    1 tab == 4 spaces!
43
 
44
    http://www.FreeRTOS.org - Documentation, latest information, license and
45
    contact details.
46
 
47
    http://www.SafeRTOS.com - A version that is certified for use in safety
48
    critical systems.
49
 
50
    http://www.OpenRTOS.com - Commercial support, development, porting,
51
    licensing and training services.
52
*/
53
 
54
 
55
/*
56
 * Creates all the demo application tasks, then starts the scheduler.  The WEB
57
 * documentation provides more details of the standard demo application tasks.
58
 * In addition to the standard demo tasks, the following tasks and tests are
59
 * defined and/or created within this file:
60
 *
61
 * "Web server" - Very basic demonstration of the uIP stack.  The WEB server
62
 * simply generates a page that shows the current state of all the tasks within
63
 * the system, including the high water mark of each task stack. The high water
64
 * mark is displayed as the amount of stack that has never been used, so the
65
 * closer the value is to zero the closer the task has come to overflowing its
66
 * stack.  The IP address and net mask are set within FreeRTOSConfig.h.  Sub
67
 * pages display some TCP/IP status information and permit LED3 to be turned on
68
 * and off using a check box.
69
 *
70
 * Tick hook function that implements a "Check" function -  This is executed
71
 * every 5 seconds from the tick hook function.  It checks to ensure that all
72
 * the standard demo tasks are still operational and running without error.
73
 * The system status (pass/fail) is then displayed underneith the task table on
74
 * the served WEB pages.
75
 *
76
 * "Reg test" tasks - These fill the registers with known values, then check
77
 * that each register still contains its expected value.  Each task uses
78
 * different values.  The tasks run with very low priority so get preempted very
79
 * frequently.  A register containing an unexpected value is indicative of an
80
 * error in the context switching mechanism.
81
 *
82
 */
83
 
84
/* Standard includes. */
85
#include <stdio.h>
86
 
87
/* Scheduler includes. */
88
#include "FreeRTOS.h"
89
#include "task.h"
90
#include "queue.h"
91
#include "semphr.h"
92
 
93
/* Demo app includes. */
94
#include "BlockQ.h"
95
#include "death.h"
96
#include "flash.h"
97
#include "partest.h"
98
#include "GenQTest.h"
99
#include "QPeek.h"
100
#include "recmutex.h"
101
 
102
/*-----------------------------------------------------------*/
103
 
104
/* ComTest constants - there is no free LED for the comtest tasks. */
105
#define mainCOM_TEST_BAUD_RATE                          ( ( unsigned long ) 19200 )
106
#define mainCOM_TEST_LED                                        ( 5 )
107
 
108
/* Task priorities. */
109
#define mainQUEUE_POLL_PRIORITY                         ( tskIDLE_PRIORITY + 2 )
110
#define mainCHECK_TASK_PRIORITY                         ( tskIDLE_PRIORITY + 3 )
111
#define mainSEM_TEST_PRIORITY                           ( tskIDLE_PRIORITY + 1 )
112
#define mainBLOCK_Q_PRIORITY                            ( tskIDLE_PRIORITY + 2 )
113
#define mainCREATOR_TASK_PRIORITY           ( tskIDLE_PRIORITY + 2 )
114
#define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )
115
#define mainGEN_QUEUE_TASK_PRIORITY                     ( tskIDLE_PRIORITY )
116
#define mainWEB_TASK_PRIORITY                   ( tskIDLE_PRIORITY + 2 )
117
 
118
/* WEB server requires enough stack for the string handling functions. */
119
#define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 2 )
120
 
121
/*
122
 * Configure the hardware for the demo.
123
 */
124
static void prvSetupHardware( void );
125
 
126
/*
127
 * Implements the 'check' function as described at the top of this file.
128
 */
129
static void prvCheckFunction( void );
130
 
131
/*
132
 * Implement the 'Reg test' functionality as described at the top of this file.
133
 */
134
static void vRegTest1Task( void *pvParameters );
135
static void vRegTest2Task( void *pvParameters );
136
 
137
/*
138
 * The task that handles the uIP stack.  All TCP/IP processing is performed in
139
 * this task.
140
 */
141
extern void vuIP_Task( void *pvParameters );
142
 
143
/*-----------------------------------------------------------*/
144
 
145
/* Counters used to detect errors within the reg test tasks. */
146
static volatile unsigned long ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;
147
 
148
/* Flag that latches any errors detected in the system. */
149
unsigned long ulCheckErrors = 0;
150
 
151
/*-----------------------------------------------------------*/
152
 
153
int main( void )
154
{
155
extern void vBasicWEBServer( void *pv );
156
 
157
        /* Setup the hardware ready for this demo. */
158
        prvSetupHardware();
159
 
160
        xTaskCreate( vuIP_Task, ( signed char * ) "uIP", mainBASIC_WEB_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );
161
 
162
        /* Start the standard demo tasks. */
163
        vStartLEDFlashTasks( tskIDLE_PRIORITY );
164
        vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
165
        vStartQueuePeekTasks();
166
        vStartRecursiveMutexTasks();
167
        vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
168
 
169
        /* Start the reg test tasks - defined in this file. */
170
        xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );
171
        xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );
172
 
173
        /* Start the scheduler. */
174
        vTaskStartScheduler();
175
 
176
    /* Will only get here if there was insufficient memory to create the idle
177
    task. */
178
        for( ;; )
179
        {
180
        }
181
}
182
/*-----------------------------------------------------------*/
183
 
184
void vApplicationTickHook( void )
185
{
186
static unsigned long ulExecutionCount = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;
187
const unsigned long ulExecutionRate = 5000 / portTICK_RATE_MS;
188
 
189
    /* Increment the count of how many times the tick hook has been called. */
190
    ulExecutionCount++;
191
 
192
    /* Is it time to perform the check again? */
193
        if( ulExecutionCount >= ulExecutionRate )
194
        {
195
                /* Reset the execution count so this function is called again in 5
196
                seconds time. */
197
                ulExecutionCount = 0;
198
 
199
                /* Has an error been found in any task? */
200
                if( xAreGenericQueueTasksStillRunning() != pdTRUE )
201
                {
202
                        ulCheckErrors |= 0x01UL;
203
                }
204
 
205
                if( xAreQueuePeekTasksStillRunning() != pdTRUE )
206
                {
207
                        ulCheckErrors |= 0x02UL;
208
                }
209
 
210
                if( xAreBlockingQueuesStillRunning() != pdTRUE )
211
                {
212
                        ulCheckErrors |= 0x04UL;
213
                }
214
 
215
                if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
216
            {
217
                ulCheckErrors |= 0x200UL;
218
            }
219
 
220
                if( ulLastRegTest1Count == ulRegTest1Counter )
221
                {
222
                        ulCheckErrors |= 0x1000UL;
223
                }
224
 
225
                if( ulLastRegTest2Count == ulRegTest2Counter )
226
                {
227
                        ulCheckErrors |= 0x1000UL;
228
                }
229
 
230
                ulLastRegTest1Count = ulRegTest1Counter;
231
                ulLastRegTest2Count = ulRegTest2Counter;
232
        }
233
}
234
/*-----------------------------------------------------------*/
235
 
236
static void prvSetupHardware( void )
237
{
238
        /* Disable the watchdog, STOP and WAIT modes. */
239
        SOPT1 = 0;
240
 
241
        /* --- Setup clock to use external 25MHz source. --- */
242
 
243
        /* Extal and xtal pin ON. */
244
        PTDPF1_D4 = 0x03;
245
        PTDPF1_D5 = 0x03;
246
 
247
        /* Switch from FEI to FBE (FLL bypassed external)
248
        enable external clock source */
249
        MCGC2 = MCGC2_ERCLKEN_MASK  /* Activate external reference clock */
250
              | MCGC2_EREFS_MASK    /* Because crystal is being used */
251
              | MCGC2_RANGE_MASK;   /* High range */
252
 
253
        /* Select clock mode and clear IREFs. */
254
        MCGC1 = (0x02 << 6 )        /* CLKS = 10 -> external reference clock. */
255
              | (0x04 << 3 )        /* RDIV = 2^4 -> 25MHz/16 = 1.5625 MHz */
256
              | MCGC1_IRCLKEN_MASK; /* IRCLK to RTC enabled */
257
 
258
        /* Wait for Reference and Clock status bits to update. */
259
        while( MCGSC_IREFST | ( MCGSC_CLKST != 0x02 ) )
260
        {
261
                /* Nothing to do here. */
262
        }
263
 
264
        /* Switch from FBE to PBE (PLL bypassed internal) mode. */
265
        MCGC3 =  0x08               /* Set PLL multi 50MHz. */
266
              |  MCGC3_PLLS_MASK;   /* Select PLL. */
267
 
268
        /* Wait for PLL status and lock bits to update. */
269
        while( !MCGSC_PLLST | !MCGSC_LOCK )
270
        {
271
                /* Nothing to do here. */
272
        }
273
 
274
 
275
        /* Now in PBE Mode, finally switch from PBE to PEE (PLL enabled external
276
        mode). */
277
        MCGC1_CLKS  = 0b00; /* PLL clock to system (MCGOUT) */
278
 
279
        /* Wait for the clock status bits to update. */
280
        while( MCGSC_CLKST != 0x03 )
281
        {
282
                /* Nothing to do here. */
283
        }
284
 
285
        /* Setup the IO for the LED outputs. */
286
        vParTestInitialise();
287
}
288
/*-----------------------------------------------------------*/
289
 
290
void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )
291
{
292
        /* This will get called if a stack overflow is detected during the context
293
        switch.  Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack
294
        problems within nested interrupts, but only do this for debug purposes as
295
        it will increase the context switch time. */
296
 
297
        ( void ) pxTask;
298
        ( void ) pcTaskName;
299
 
300
        for( ;; )
301
        {
302
        }
303
}
304
/*-----------------------------------------------------------*/
305
 
306
static void vRegTest1Task( void *pvParameters )
307
{
308
  /* Just to remove compiler warnings. */
309
  ( void ) pvParameters;
310
 
311
        /* Set all the registers to known values, then check that each retains its
312
        expected value - as described at the top of this file.  If an error is
313
        found then the loop counter will no longer be incremented allowing the check
314
        task to recognise the error. */
315
        asm volatile    (       "reg_test_1_start:                                              \n\t"
316
                                                "       moveq           #1, d0                                  \n\t"
317
                                                "       moveq           #2, d1                                  \n\t"
318
                                                "       moveq           #3, d2                                  \n\t"
319
                                                "       moveq           #4, d3                                  \n\t"
320
                                                "       moveq           #5, d4                                  \n\t"
321
                                                "       moveq           #6, d5                                  \n\t"
322
                                                "       moveq           #7, d6                                  \n\t"
323
                                                "       moveq           #8, d7                                  \n\t"
324
                                                "       move            #9, a0                                  \n\t"
325
                                                "       move            #10, a1                                 \n\t"
326
                                                "       move            #11, a2                                 \n\t"
327
                                                "       move            #12, a3                                 \n\t"
328
                                                "       move            #13, a4                                 \n\t"
329
                                                "       move            #15, a6                                 \n\t"
330
                                                "                                                                               \n\t"
331
                                                "       cmpi.l          #1, d0                                  \n\t"
332
                                                "       bne                     reg_test_1_error                \n\t"
333
                                                "       cmpi.l          #2, d1                                  \n\t"
334
                                                "       bne                     reg_test_1_error                \n\t"
335
                                                "       cmpi.l          #3, d2                                  \n\t"
336
                                                "       bne                     reg_test_1_error                \n\t"
337
                                                "       cmpi.l          #4, d3                                  \n\t"
338
                                                "       bne                     reg_test_1_error                \n\t"
339
                                                "       cmpi.l          #5, d4                                  \n\t"
340
                                                "       bne                     reg_test_1_error                \n\t"
341
                                                "       cmpi.l          #6, d5                                  \n\t"
342
                                                "       bne                     reg_test_1_error                \n\t"
343
                                                "       cmpi.l          #7, d6                                  \n\t"
344
                                                "       bne                     reg_test_1_error                \n\t"
345
                                                "       cmpi.l          #8, d7                                  \n\t"
346
                                                "       bne                     reg_test_1_error                \n\t"
347
                                                "       move            a0, d0                                  \n\t"
348
                                                "       cmpi.l          #9, d0                                  \n\t"
349
                                                "       bne                     reg_test_1_error                \n\t"
350
                                                "       move            a1, d0                                  \n\t"
351
                                                "       cmpi.l          #10, d0                                 \n\t"
352
                                                "       bne                     reg_test_1_error                \n\t"
353
                                                "       move            a2, d0                                  \n\t"
354
                                                "       cmpi.l          #11, d0                                 \n\t"
355
                                                "       bne                     reg_test_1_error                \n\t"
356
                                                "       move            a3, d0                                  \n\t"
357
                                                "       cmpi.l          #12, d0                                 \n\t"
358
                                                "       bne                     reg_test_1_error                \n\t"
359
                                                "       move            a4, d0                                  \n\t"
360
                                                "       cmpi.l          #13, d0                                 \n\t"
361
                                                "       bne                     reg_test_1_error                \n\t"
362
                                                "       move            a6, d0                                  \n\t"
363
                                                "       cmpi.l          #15, d0                                 \n\t"
364
                                                "       bne                     reg_test_1_error                \n\t"
365
                                                "       move            ulRegTest1Counter, d0   \n\t"
366
                                                "       addq            #1, d0                                  \n\t"
367
                                                "       move            d0, ulRegTest1Counter   \n\t"
368
                                                "       bra                     reg_test_1_start                \n\t"
369
                                                "reg_test_1_error:                                              \n\t"
370
                                                "       bra                     reg_test_1_error                \n\t"
371
                                        );
372
}
373
/*-----------------------------------------------------------*/
374
 
375
static void vRegTest2Task( void *pvParameters )
376
{
377
  /* Just to remove compiler warnings. */
378
  ( void ) pvParameters;
379
 
380
        /* Set all the registers to known values, then check that each retains its
381
        expected value - as described at the top of this file.  If an error is
382
        found then the loop counter will no longer be incremented allowing the check
383
        task to recognise the error. */
384
        asm volatile    (       "reg_test_2_start:                                              \n\t"
385
                                                "       moveq           #10, d0                                 \n\t"
386
                                                "       moveq           #20, d1                                 \n\t"
387
                                                "       moveq           #30, d2                                 \n\t"
388
                                                "       moveq           #40, d3                                 \n\t"
389
                                                "       moveq           #50, d4                                 \n\t"
390
                                                "       moveq           #60, d5                                 \n\t"
391
                                                "       moveq           #70, d6                                 \n\t"
392
                                                "       moveq           #80, d7                                 \n\t"
393
                                                "       move            #90, a0                                 \n\t"
394
                                                "       move            #100, a1                                \n\t"
395
                                                "       move            #110, a2                                \n\t"
396
                                                "       move            #120, a3                                \n\t"
397
                                                "       move            #130, a4                                \n\t"
398
                                                "       move            #150, a6                                \n\t"
399
                                                "                                                                               \n\t"
400
                                                "       cmpi.l          #10, d0                                 \n\t"
401
                                                "       bne                     reg_test_2_error                \n\t"
402
                                                "       cmpi.l          #20, d1                                 \n\t"
403
                                                "       bne                     reg_test_2_error                \n\t"
404
                                                "       cmpi.l          #30, d2                                 \n\t"
405
                                                "       bne                     reg_test_2_error                \n\t"
406
                                                "       cmpi.l          #40, d3                                 \n\t"
407
                                                "       bne                     reg_test_2_error                \n\t"
408
                                                "       cmpi.l          #50, d4                                 \n\t"
409
                                                "       bne                     reg_test_2_error                \n\t"
410
                                                "       cmpi.l          #60, d5                                 \n\t"
411
                                                "       bne                     reg_test_2_error                \n\t"
412
                                                "       cmpi.l          #70, d6                                 \n\t"
413
                                                "       bne                     reg_test_2_error                \n\t"
414
                                                "       cmpi.l          #80, d7                                 \n\t"
415
                                                "       bne                     reg_test_2_error                \n\t"
416
                                                "       move            a0, d0                                  \n\t"
417
                                                "       cmpi.l          #90, d0                                 \n\t"
418
                                                "       bne                     reg_test_2_error                \n\t"
419
                                                "       move            a1, d0                                  \n\t"
420
                                                "       cmpi.l          #100, d0                                \n\t"
421
                                                "       bne                     reg_test_2_error                \n\t"
422
                                                "       move            a2, d0                                  \n\t"
423
                                                "       cmpi.l          #110, d0                                \n\t"
424
                                                "       bne                     reg_test_2_error                \n\t"
425
                                                "       move            a3, d0                                  \n\t"
426
                                                "       cmpi.l          #120, d0                                \n\t"
427
                                                "       bne                     reg_test_2_error                \n\t"
428
                                                "       move            a4, d0                                  \n\t"
429
                                                "       cmpi.l          #130, d0                                \n\t"
430
                                                "       bne                     reg_test_2_error                \n\t"
431
                                                "       move            a6, d0                                  \n\t"
432
                                                "       cmpi.l          #150, d0                                \n\t"
433
                                                "       bne                     reg_test_2_error                \n\t"
434
                                                "       move            ulRegTest1Counter, d0   \n\t"
435
                                                "       addq            #1, d0                                  \n\t"
436
                                                "       move            d0, ulRegTest2Counter   \n\t"
437
                                                "       bra                     reg_test_2_start                \n\t"
438
                                                "reg_test_2_error:                                              \n\t"
439
                                                "       bra                     reg_test_2_error                \n\t"
440
                                        );
441
}
442
/*-----------------------------------------------------------*/
443
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.