OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF51CN128_CodeWarrior/] [prm/] [Project.lcf] - Blame information for rev 578

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 jeremybenn
# Sample Linker Command File for CodeWarrior for ColdFire MCF51CN128
2
 
3
# Memory ranges
4
 
5
MEMORY {
6
   code        (RX)  : ORIGIN = 0x00000410, LENGTH = 0x0001FBF0
7
   userram     (RWX) : ORIGIN = 0x00800000, LENGTH = 0x00006000
8
}
9
 
10
SECTIONS {
11
 
12
# Heap and Stack sizes definition
13
  ___heap_size     = 0x04;
14
  ___stack_size    = 0x0200;
15
 
16
# MCF51CN128 Derivative Memory map definitions from linker command files:
17
# ___RAM_ADDRESS, ___RAM_SIZE, ___FLASH_ADDRESS, ___FLASH_SIZE linker
18
# symbols must be defined in the linker command file.
19
 
20
# 24 Kbytes Internal SRAM
21
   ___RAM_ADDRESS = 0x00800000;
22
   ___RAM_SIZE    = 0x00006000;
23
 
24
# 128 KByte Internal Flash Memory
25
   ___FLASH_ADDRESS  = 0x00000000;
26
   ___FLASH_SIZE     = 0x00020000;
27
 
28
  .userram        : {} > userram
29
  .code     : {} > code
30
 
31
  .text :
32
  {
33
    *(.text)
34
    . = ALIGN (0x4);
35
    *(.rodata)
36
    . = ALIGN (0x4);
37
    ___ROM_AT = .;
38
    ___DATA_ROM = .;
39
  } >> code
40
 
41
  .data : AT(___ROM_AT)
42
  {
43
    ___DATA_RAM = .;
44
    . = ALIGN(0x4);
45
    *(.exception)
46
    . = ALIGN(0x4);
47
    __exception_table_start__ = .;
48
    EXCEPTION
49
    __exception_table_end__ = .;
50
 
51
    ___sinit__ = .;
52
      STATICINIT
53
    __START_DATA = .;
54
 
55
    *(.data)
56
    . = ALIGN (0x4);
57
    __END_DATA = .;
58
 
59
    __START_SDATA = .;
60
    *(.sdata)
61
    . = ALIGN (0x4);
62
    __END_SDATA = .;
63
 
64
    ___DATA_END = .;
65
    __SDA_BASE = .;
66
    . = ALIGN (0x4);
67
  } >> userram
68
 
69
  .bss :
70
  {
71
    ___BSS_START = .;
72
    __START_SBSS = .;
73
    *(.sbss)
74
    . = ALIGN (0x4);
75
    *(SCOMMON)
76
    __END_SBSS = .;
77
 
78
    __START_BSS = .;
79
    *(.bss)
80
    . = ALIGN (0x4);
81
    *(COMMON)
82
    __END_BSS = .;
83
    ___BSS_END = .;
84
 
85
    . = ALIGN(0x4);
86
  } >> userram
87
 
88
  .custom :
89
  {
90
    ___HEAP_START       = .;
91
    ___heap_addr        = ___HEAP_START;
92
    ___HEAP_END         = ___HEAP_START + ___heap_size;
93
    ___SP_END             = ___HEAP_END;
94
    ___SP_INIT          = ___SP_END + ___stack_size;
95
 
96
    . = ALIGN (0x4);
97
  } >> userram
98
 
99
  __SP_INIT             = ___SP_INIT;
100
 
101
  ___SP_AFTER_RESET     = __SP_INIT;
102
 
103
  _romp_at = ___ROM_AT + SIZEOF(.data);
104
  .romp : AT(_romp_at)
105
  {
106
    __S_romp = _romp_at;
107
    WRITEW(___ROM_AT);
108
    WRITEW(ADDR(.data));
109
    WRITEW(SIZEOF(.data));
110
    WRITEW(0);
111
    WRITEW(0);
112
    WRITEW(0);
113
  }
114
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.