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jeremybenn |
/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2008/05/23 Revision: 0.95
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*
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* (c) Copyright UNIS, a.s. 1997-2008
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* UNIS, a.s.
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* Jundrovska 33
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* 624 00 Brno
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* Czech Republic
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* http : www.processorexpert.com
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* mail : info@processorexpert.com
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*/
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#ifndef __MCF52221_INTC_H__
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#define __MCF52221_INTC_H__
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/*********************************************************************
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*
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* Interrupt Controller (INTC)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_INTC0_IPRH (*(vuint32*)(0x40000C00))
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#define MCF_INTC0_IPRL (*(vuint32*)(0x40000C04))
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#define MCF_INTC0_IMRH (*(vuint32*)(0x40000C08))
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#define MCF_INTC0_IMRL (*(vuint32*)(0x40000C0C))
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#define MCF_INTC0_INTFRCH (*(vuint32*)(0x40000C10))
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#define MCF_INTC0_INTFRCL (*(vuint32*)(0x40000C14))
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#define MCF_INTC0_IRLR (*(vuint8 *)(0x40000C18))
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#define MCF_INTC0_IACKLPR (*(vuint8 *)(0x40000C19))
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#define MCF_INTC0_ICR01 (*(vuint8 *)(0x40000C41))
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#define MCF_INTC0_ICR02 (*(vuint8 *)(0x40000C42))
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#define MCF_INTC0_ICR03 (*(vuint8 *)(0x40000C43))
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#define MCF_INTC0_ICR04 (*(vuint8 *)(0x40000C44))
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#define MCF_INTC0_ICR05 (*(vuint8 *)(0x40000C45))
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#define MCF_INTC0_ICR06 (*(vuint8 *)(0x40000C46))
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#define MCF_INTC0_ICR07 (*(vuint8 *)(0x40000C47))
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#define MCF_INTC0_ICR08 (*(vuint8 *)(0x40000C48))
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#define MCF_INTC0_ICR09 (*(vuint8 *)(0x40000C49))
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#define MCF_INTC0_ICR10 (*(vuint8 *)(0x40000C4A))
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#define MCF_INTC0_ICR11 (*(vuint8 *)(0x40000C4B))
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#define MCF_INTC0_ICR12 (*(vuint8 *)(0x40000C4C))
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#define MCF_INTC0_ICR13 (*(vuint8 *)(0x40000C4D))
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#define MCF_INTC0_ICR14 (*(vuint8 *)(0x40000C4E))
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#define MCF_INTC0_ICR15 (*(vuint8 *)(0x40000C4F))
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#define MCF_INTC0_ICR16 (*(vuint8 *)(0x40000C50))
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#define MCF_INTC0_ICR17 (*(vuint8 *)(0x40000C51))
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#define MCF_INTC0_ICR18 (*(vuint8 *)(0x40000C52))
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#define MCF_INTC0_ICR19 (*(vuint8 *)(0x40000C53))
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#define MCF_INTC0_ICR20 (*(vuint8 *)(0x40000C54))
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#define MCF_INTC0_ICR21 (*(vuint8 *)(0x40000C55))
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#define MCF_INTC0_ICR22 (*(vuint8 *)(0x40000C56))
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#define MCF_INTC0_ICR23 (*(vuint8 *)(0x40000C57))
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#define MCF_INTC0_ICR24 (*(vuint8 *)(0x40000C58))
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#define MCF_INTC0_ICR25 (*(vuint8 *)(0x40000C59))
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#define MCF_INTC0_ICR26 (*(vuint8 *)(0x40000C5A))
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#define MCF_INTC0_ICR27 (*(vuint8 *)(0x40000C5B))
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#define MCF_INTC0_ICR28 (*(vuint8 *)(0x40000C5C))
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#define MCF_INTC0_ICR29 (*(vuint8 *)(0x40000C5D))
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#define MCF_INTC0_ICR30 (*(vuint8 *)(0x40000C5E))
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#define MCF_INTC0_ICR31 (*(vuint8 *)(0x40000C5F))
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#define MCF_INTC0_ICR32 (*(vuint8 *)(0x40000C60))
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#define MCF_INTC0_ICR33 (*(vuint8 *)(0x40000C61))
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#define MCF_INTC0_ICR34 (*(vuint8 *)(0x40000C62))
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#define MCF_INTC0_ICR35 (*(vuint8 *)(0x40000C63))
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#define MCF_INTC0_ICR36 (*(vuint8 *)(0x40000C64))
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#define MCF_INTC0_ICR37 (*(vuint8 *)(0x40000C65))
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#define MCF_INTC0_ICR38 (*(vuint8 *)(0x40000C66))
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#define MCF_INTC0_ICR39 (*(vuint8 *)(0x40000C67))
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#define MCF_INTC0_ICR40 (*(vuint8 *)(0x40000C68))
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#define MCF_INTC0_ICR41 (*(vuint8 *)(0x40000C69))
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#define MCF_INTC0_ICR42 (*(vuint8 *)(0x40000C6A))
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#define MCF_INTC0_ICR43 (*(vuint8 *)(0x40000C6B))
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#define MCF_INTC0_ICR44 (*(vuint8 *)(0x40000C6C))
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#define MCF_INTC0_ICR45 (*(vuint8 *)(0x40000C6D))
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#define MCF_INTC0_ICR46 (*(vuint8 *)(0x40000C6E))
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#define MCF_INTC0_ICR47 (*(vuint8 *)(0x40000C6F))
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#define MCF_INTC0_ICR48 (*(vuint8 *)(0x40000C70))
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#define MCF_INTC0_ICR49 (*(vuint8 *)(0x40000C71))
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#define MCF_INTC0_ICR50 (*(vuint8 *)(0x40000C72))
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#define MCF_INTC0_ICR51 (*(vuint8 *)(0x40000C73))
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#define MCF_INTC0_ICR52 (*(vuint8 *)(0x40000C74))
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#define MCF_INTC0_ICR53 (*(vuint8 *)(0x40000C75))
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#define MCF_INTC0_ICR54 (*(vuint8 *)(0x40000C76))
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#define MCF_INTC0_ICR55 (*(vuint8 *)(0x40000C77))
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#define MCF_INTC0_ICR56 (*(vuint8 *)(0x40000C78))
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#define MCF_INTC0_ICR57 (*(vuint8 *)(0x40000C79))
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#define MCF_INTC0_ICR58 (*(vuint8 *)(0x40000C7A))
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#define MCF_INTC0_ICR59 (*(vuint8 *)(0x40000C7B))
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#define MCF_INTC0_ICR60 (*(vuint8 *)(0x40000C7C))
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#define MCF_INTC0_ICR61 (*(vuint8 *)(0x40000C7D))
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#define MCF_INTC0_ICR62 (*(vuint8 *)(0x40000C7E))
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#define MCF_INTC0_ICR63 (*(vuint8 *)(0x40000C7F))
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#define MCF_INTC0_SWIACK (*(vuint8 *)(0x40000CE0))
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#define MCF_INTC0_L1IACK (*(vuint8 *)(0x40000CE4))
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#define MCF_INTC0_L2IACK (*(vuint8 *)(0x40000CE8))
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#define MCF_INTC0_L3IACK (*(vuint8 *)(0x40000CEC))
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#define MCF_INTC0_L4IACK (*(vuint8 *)(0x40000CF0))
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#define MCF_INTC0_L5IACK (*(vuint8 *)(0x40000CF4))
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#define MCF_INTC0_L6IACK (*(vuint8 *)(0x40000CF8))
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#define MCF_INTC0_L7IACK (*(vuint8 *)(0x40000CFC))
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#define MCF_INTC0_ICR(x) (*(vuint8 *)(0x40000C41 + ((x-1)*0x1)))
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#define MCF_INTC0_LIACK(x) (*(vuint8 *)(0x40000CE4 + ((x-1)*0x4)))
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/* Bit definitions and macros for MCF_INTC_IPRH */
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#define MCF_INTC_IPRH_INT32 (0x1)
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#define MCF_INTC_IPRH_INT33 (0x2)
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#define MCF_INTC_IPRH_INT34 (0x4)
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#define MCF_INTC_IPRH_INT35 (0x8)
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#define MCF_INTC_IPRH_INT36 (0x10)
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#define MCF_INTC_IPRH_INT37 (0x20)
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#define MCF_INTC_IPRH_INT38 (0x40)
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#define MCF_INTC_IPRH_INT39 (0x80)
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#define MCF_INTC_IPRH_INT40 (0x100)
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#define MCF_INTC_IPRH_INT41 (0x200)
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#define MCF_INTC_IPRH_INT42 (0x400)
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#define MCF_INTC_IPRH_INT43 (0x800)
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#define MCF_INTC_IPRH_INT44 (0x1000)
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#define MCF_INTC_IPRH_INT45 (0x2000)
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#define MCF_INTC_IPRH_INT46 (0x4000)
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#define MCF_INTC_IPRH_INT47 (0x8000)
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#define MCF_INTC_IPRH_INT48 (0x10000)
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#define MCF_INTC_IPRH_INT49 (0x20000)
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#define MCF_INTC_IPRH_INT50 (0x40000)
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#define MCF_INTC_IPRH_INT51 (0x80000)
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#define MCF_INTC_IPRH_INT52 (0x100000)
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#define MCF_INTC_IPRH_INT53 (0x200000)
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#define MCF_INTC_IPRH_INT54 (0x400000)
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#define MCF_INTC_IPRH_INT55 (0x800000)
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#define MCF_INTC_IPRH_INT56 (0x1000000)
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#define MCF_INTC_IPRH_INT57 (0x2000000)
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#define MCF_INTC_IPRH_INT58 (0x4000000)
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#define MCF_INTC_IPRH_INT59 (0x8000000)
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#define MCF_INTC_IPRH_INT60 (0x10000000)
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#define MCF_INTC_IPRH_INT61 (0x20000000)
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#define MCF_INTC_IPRH_INT62 (0x40000000)
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#define MCF_INTC_IPRH_INT63 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_IPRL */
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#define MCF_INTC_IPRL_INT1 (0x2)
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#define MCF_INTC_IPRL_INT2 (0x4)
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#define MCF_INTC_IPRL_INT3 (0x8)
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#define MCF_INTC_IPRL_INT4 (0x10)
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#define MCF_INTC_IPRL_INT5 (0x20)
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#define MCF_INTC_IPRL_INT6 (0x40)
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#define MCF_INTC_IPRL_INT7 (0x80)
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#define MCF_INTC_IPRL_INT8 (0x100)
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#define MCF_INTC_IPRL_INT9 (0x200)
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#define MCF_INTC_IPRL_INT10 (0x400)
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#define MCF_INTC_IPRL_INT11 (0x800)
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#define MCF_INTC_IPRL_INT12 (0x1000)
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#define MCF_INTC_IPRL_INT13 (0x2000)
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#define MCF_INTC_IPRL_INT14 (0x4000)
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#define MCF_INTC_IPRL_INT15 (0x8000)
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#define MCF_INTC_IPRL_INT16 (0x10000)
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#define MCF_INTC_IPRL_INT17 (0x20000)
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#define MCF_INTC_IPRL_INT18 (0x40000)
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#define MCF_INTC_IPRL_INT19 (0x80000)
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#define MCF_INTC_IPRL_INT20 (0x100000)
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#define MCF_INTC_IPRL_INT21 (0x200000)
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#define MCF_INTC_IPRL_INT22 (0x400000)
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#define MCF_INTC_IPRL_INT23 (0x800000)
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#define MCF_INTC_IPRL_INT24 (0x1000000)
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#define MCF_INTC_IPRL_INT25 (0x2000000)
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#define MCF_INTC_IPRL_INT26 (0x4000000)
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#define MCF_INTC_IPRL_INT27 (0x8000000)
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#define MCF_INTC_IPRL_INT28 (0x10000000)
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#define MCF_INTC_IPRL_INT29 (0x20000000)
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#define MCF_INTC_IPRL_INT30 (0x40000000)
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#define MCF_INTC_IPRL_INT31 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_IMRH */
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#define MCF_INTC_IMRH_INT_MASK32 (0x1)
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#define MCF_INTC_IMRH_INT_MASK33 (0x2)
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#define MCF_INTC_IMRH_INT_MASK34 (0x4)
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#define MCF_INTC_IMRH_INT_MASK35 (0x8)
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#define MCF_INTC_IMRH_INT_MASK36 (0x10)
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#define MCF_INTC_IMRH_INT_MASK37 (0x20)
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#define MCF_INTC_IMRH_INT_MASK38 (0x40)
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#define MCF_INTC_IMRH_INT_MASK39 (0x80)
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#define MCF_INTC_IMRH_INT_MASK40 (0x100)
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#define MCF_INTC_IMRH_INT_MASK41 (0x200)
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#define MCF_INTC_IMRH_INT_MASK42 (0x400)
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#define MCF_INTC_IMRH_INT_MASK43 (0x800)
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#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
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#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
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#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
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#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
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#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
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#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
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#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
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#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
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#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
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#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
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#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
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#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
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#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
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#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
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#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
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#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
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#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
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#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
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#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
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#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_IMRL */
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#define MCF_INTC_IMRL_MASKALL (0x1)
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#define MCF_INTC_IMRL_INT_MASK1 (0x2)
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#define MCF_INTC_IMRL_INT_MASK2 (0x4)
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#define MCF_INTC_IMRL_INT_MASK3 (0x8)
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#define MCF_INTC_IMRL_INT_MASK4 (0x10)
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#define MCF_INTC_IMRL_INT_MASK5 (0x20)
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#define MCF_INTC_IMRL_INT_MASK6 (0x40)
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#define MCF_INTC_IMRL_INT_MASK7 (0x80)
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#define MCF_INTC_IMRL_INT_MASK8 (0x100)
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#define MCF_INTC_IMRL_INT_MASK9 (0x200)
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#define MCF_INTC_IMRL_INT_MASK10 (0x400)
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#define MCF_INTC_IMRL_INT_MASK11 (0x800)
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#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
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#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
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#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
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#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
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#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
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#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
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#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
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#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
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#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
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#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
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#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
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#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
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#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
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#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
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#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
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#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
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#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
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#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
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#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
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#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_INTFRCH */
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#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
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#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
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#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
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#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
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#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
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#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
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#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
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#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
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#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
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#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
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#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
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#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
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#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
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#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
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#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
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#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
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#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
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#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
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#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
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#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
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#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
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#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
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#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
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#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
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#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
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#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
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#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
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#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
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#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
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#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
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#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
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#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
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/* Bit definitions and macros for MCF_INTC_INTFRCL */
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#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
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#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
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#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
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#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
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#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
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#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
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#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
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#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
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#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
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#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
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291 |
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#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
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292 |
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#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
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#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
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#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
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#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
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296 |
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#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
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297 |
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#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
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298 |
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#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
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299 |
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#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
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300 |
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#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
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301 |
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#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
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#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
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#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
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#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
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#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
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#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
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307 |
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#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
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308 |
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#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
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309 |
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#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
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310 |
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#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
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311 |
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#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
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312 |
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313 |
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/* Bit definitions and macros for MCF_INTC_IRLR */
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314 |
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#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
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315 |
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316 |
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/* Bit definitions and macros for MCF_INTC_IACKLPR */
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317 |
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#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
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318 |
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#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
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319 |
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320 |
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/* Bit definitions and macros for MCF_INTC_ICR */
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321 |
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#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
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322 |
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#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
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323 |
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324 |
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/* Bit definitions and macros for MCF_INTC_SWIACK */
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325 |
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#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
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326 |
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327 |
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/* Bit definitions and macros for MCF_INTC_LIACK */
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328 |
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#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
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329 |
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330 |
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331 |
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#endif /* __MCF52221_INTC_H__ */
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