OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52221_CodeWarrior/] [headers/] [MCF52221_PIT.h] - Blame information for rev 582

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
2
 * Copyright Freescale Semiconductor Inc
3
 * All rights reserved.
4
 *
5
 * 2008/05/23 Revision: 0.95
6
 *
7
 * (c) Copyright UNIS, a.s. 1997-2008
8
 * UNIS, a.s.
9
 * Jundrovska 33
10
 * 624 00 Brno
11
 * Czech Republic
12
 * http      : www.processorexpert.com
13
 * mail      : info@processorexpert.com
14
 */
15
 
16
#ifndef __MCF52221_PIT_H__
17
#define __MCF52221_PIT_H__
18
 
19
 
20
/*********************************************************************
21
*
22
* Programmable Interrupt Timer (PIT)
23
*
24
*********************************************************************/
25
 
26
/* Register read/write macros */
27
#define MCF_PIT0_PCSR                        (*(vuint16*)(0x40150000))
28
#define MCF_PIT0_PMR                         (*(vuint16*)(0x40150002))
29
#define MCF_PIT0_PCNTR                       (*(vuint16*)(0x40150004))
30
 
31
#define MCF_PIT1_PCSR                        (*(vuint16*)(0x40160000))
32
#define MCF_PIT1_PMR                         (*(vuint16*)(0x40160002))
33
#define MCF_PIT1_PCNTR                       (*(vuint16*)(0x40160004))
34
 
35
#define MCF_PIT_PCSR(x)                      (*(vuint16*)(0x40150000 + ((x)*0x10000)))
36
#define MCF_PIT_PMR(x)                       (*(vuint16*)(0x40150002 + ((x)*0x10000)))
37
#define MCF_PIT_PCNTR(x)                     (*(vuint16*)(0x40150004 + ((x)*0x10000)))
38
 
39
 
40
/* Bit definitions and macros for MCF_PIT_PCSR */
41
#define MCF_PIT_PCSR_EN                      (0x1)
42
#define MCF_PIT_PCSR_RLD                     (0x2)
43
#define MCF_PIT_PCSR_PIF                     (0x4)
44
#define MCF_PIT_PCSR_PIE                     (0x8)
45
#define MCF_PIT_PCSR_OVW                     (0x10)
46
#define MCF_PIT_PCSR_DBG                     (0x20)
47
#define MCF_PIT_PCSR_DOZE                    (0x40)
48
#define MCF_PIT_PCSR_PRE(x)                  (((x)&0xF)<<0x8)
49
 
50
/* Bit definitions and macros for MCF_PIT_PMR */
51
#define MCF_PIT_PMR_PM(x)                    (((x)&0xFFFF)<<0)
52
 
53
/* Bit definitions and macros for MCF_PIT_PCNTR */
54
#define MCF_PIT_PCNTR_PC(x)                  (((x)&0xFFFF)<<0)
55
 
56
 
57
#endif /* __MCF52221_PIT_H__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.