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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52221_CodeWarrior/] [headers/] [MCF52221_SCM.h] - Blame information for rev 866

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Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
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 * Copyright Freescale Semiconductor Inc
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 * All rights reserved.
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 *
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 * 2008/05/23 Revision: 0.95
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 *
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 * (c) Copyright UNIS, a.s. 1997-2008
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 * UNIS, a.s.
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 * Jundrovska 33
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 * 624 00 Brno
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 * Czech Republic
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 * http      : www.processorexpert.com
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 * mail      : info@processorexpert.com
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 */
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#ifndef __MCF52221_SCM_H__
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#define __MCF52221_SCM_H__
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/*********************************************************************
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*
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* System Control Module (SCM)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_SCM_RAMBAR                       (*(vuint32*)(0x40000008))
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#define MCF_SCM_PPMRH                        (*(vuint32*)(0x4000000C))
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#define MCF_SCM_CRSR                         (*(vuint8 *)(0x40000010))
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#define MCF_SCM_CWCR                         (*(vuint8 *)(0x40000011))
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#define MCF_SCM_CWSR                         (*(vuint8 *)(0x40000013))
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#define MCF_SCM_DMAREQC                      (*(vuint32*)(0x40000014))
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#define MCF_SCM_PPMRL                        (*(vuint32*)(0x40000018))
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#define MCF_SCM_MPARK                        (*(vuint32*)(0x4000001C))
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#define MCF_SCM_MPR                          (*(vuint8 *)(0x40000020))
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#define MCF_SCM_PPMRS                        (*(vuint8 *)(0x40000021))
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#define MCF_SCM_PPMRC                        (*(vuint8 *)(0x40000022))
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#define MCF_SCM_IPSBMT                       (*(vuint8 *)(0x40000023))
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#define MCF_SCM_PACR0                        (*(vuint8 *)(0x40000024))
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#define MCF_SCM_PACR1                        (*(vuint8 *)(0x40000025))
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#define MCF_SCM_PACR2                        (*(vuint8 *)(0x40000026))
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#define MCF_SCM_PACR3                        (*(vuint8 *)(0x40000027))
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#define MCF_SCM_PACR4                        (*(vuint8 *)(0x40000028))
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#define MCF_SCM_PACR5                        (*(vuint8 *)(0x40000029))
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#define MCF_SCM_PACR6                        (*(vuint8 *)(0x4000002A))
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#define MCF_SCM_PACR7                        (*(vuint8 *)(0x4000002B))
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#define MCF_SCM_PACR8                        (*(vuint8 *)(0x4000002C))
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#define MCF_SCM_GPACR0                       (*(vuint8 *)(0x40000030))
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#define MCF_SCM_GPACR1                       (*(vuint8 *)(0x40000031))
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#define MCF_SCM_PACR(x)                      (*(vuint8 *)(0x40000024 + ((x)*0x1)))
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#define MCF_SCM_GPACR(x)                     (*(vuint8 *)(0x40000030 + ((x)*0x1)))
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/* Other macros */
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#define MCF_SCM_IPSBAR                       (*(vuint32*)(0x40000000))
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#define MCF_SCM_IPSBAR_V                     (0x1)
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#define MCF_SCM_IPSBAR_BA(x)                 ((x)&0xC0000000)
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/* Bit definitions and macros for MCF_SCM_RAMBAR */
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#define MCF_SCM_RAMBAR_BDE                   (0x200)
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#define MCF_SCM_RAMBAR_BA(x)                 ((x)&0xFFFF0000)
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/* Bit definitions and macros for MCF_SCM_PPMRH */
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#define MCF_SCM_PPMRH_CDPORTS                (0x1)
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#define MCF_SCM_PPMRH_CDEPORT                (0x2)
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#define MCF_SCM_PPMRH_CDPIT0                 (0x8)
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#define MCF_SCM_PPMRH_CDPIT1                 (0x10)
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#define MCF_SCM_PPMRH_CDADC                  (0x80)
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#define MCF_SCM_PPMRH_CDGPT                  (0x100)
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#define MCF_SCM_PPMRH_CDPWM                  (0x200)
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#define MCF_SCM_PPMRH_CDFCAN                 (0x400)
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#define MCF_SCM_PPMRH_CDCFM                  (0x800)
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/* Bit definitions and macros for MCF_SCM_CRSR */
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#define MCF_SCM_CRSR_EXT                     (0x80)
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/* Bit definitions and macros for MCF_SCM_CWCR */
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#define MCF_SCM_CWCR_CWTIF                   (0x1)
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#define MCF_SCM_CWCR_CWTAVAL                 (0x2)
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#define MCF_SCM_CWCR_CWTA                    (0x4)
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#define MCF_SCM_CWCR_CWT(x)                  (((x)&0x7)<<0x3)
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#define MCF_SCM_CWCR_CWT_2_9                 (0)
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#define MCF_SCM_CWCR_CWT_2_11                (0x8)
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#define MCF_SCM_CWCR_CWT_2_13                (0x10)
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#define MCF_SCM_CWCR_CWT_2_15                (0x18)
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#define MCF_SCM_CWCR_CWT_2_19                (0x20)
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#define MCF_SCM_CWCR_CWT_2_23                (0x28)
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#define MCF_SCM_CWCR_CWT_2_27                (0x30)
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#define MCF_SCM_CWCR_CWT_2_31                (0x38)
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#define MCF_SCM_CWCR_CWRI                    (0x40)
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#define MCF_SCM_CWCR_CWE                     (0x80)
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/* Bit definitions and macros for MCF_SCM_CWSR */
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#define MCF_SCM_CWSR_CWSR(x)                 (((x)&0xFF)<<0)
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/* Bit definitions and macros for MCF_SCM_DMAREQC */
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#define MCF_SCM_DMAREQC_DMAC0(x)             (((x)&0xF)<<0)
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#define MCF_SCM_DMAREQC_DMAC1(x)             (((x)&0xF)<<0x4)
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#define MCF_SCM_DMAREQC_DMAC2(x)             (((x)&0xF)<<0x8)
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#define MCF_SCM_DMAREQC_DMAC3(x)             (((x)&0xF)<<0xC)
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/* Bit definitions and macros for MCF_SCM_PPMRL */
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#define MCF_SCM_PPMRL_CDG                    (0x2)
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#define MCF_SCM_PPMRL_CDDMA                  (0x10)
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#define MCF_SCM_PPMRL_CDUART0                (0x20)
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#define MCF_SCM_PPMRL_CDUART1                (0x40)
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#define MCF_SCM_PPMRL_CDUART2                (0x80)
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#define MCF_SCM_PPMRL_CDI2C                  (0x200)
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#define MCF_SCM_PPMRL_CDQSPI                 (0x400)
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#define MCF_SCM_PPMRL_CDTMR0                 (0x2000)
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#define MCF_SCM_PPMRL_CDTMR1                 (0x4000)
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#define MCF_SCM_PPMRL_CDTMR2                 (0x8000)
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#define MCF_SCM_PPMRL_CDTMR3                 (0x10000)
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#define MCF_SCM_PPMRL_CDINTC0                (0x20000)
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/* Bit definitions and macros for MCF_SCM_MPARK */
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#define MCF_SCM_MPARK_LCKOUT_TIME(x)         (((x)&0xF)<<0x8)
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#define MCF_SCM_MPARK_PRKLAST                (0x1000)
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#define MCF_SCM_MPARK_TIMEOUT                (0x2000)
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#define MCF_SCM_MPARK_FIXED                  (0x4000)
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#define MCF_SCM_MPARK_M0_PRTY(x)             (((x)&0x3)<<0x12)
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#define MCF_SCM_MPARK_M2_PRTY(x)             (((x)&0x3)<<0x14)
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#define MCF_SCM_MPARK_BCR24BIT               (0x1000000)
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#define MCF_SCM_MPARK_M2_P_EN                (0x2000000)
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/* Bit definitions and macros for MCF_SCM_MPR */
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#define MCF_SCM_MPR_MPR(x)                   (((x)&0xF)<<0)
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/* Bit definitions and macros for MCF_SCM_PPMRS */
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#define MCF_SCM_PPMRS_PPMRS(x)               (((x)&0x7F)<<0)
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#define MCF_SCM_PPMRS_DISABLE_ALL            (0x40)
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#define MCF_SCM_PPMRS_DISABLE_CFM            (0x2B)
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#define MCF_SCM_PPMRS_DISABLE_CAN            (0x2A)
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#define MCF_SCM_PPMRS_DISABLE_PWM            (0x29)
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#define MCF_SCM_PPMRS_DISABLE_GPT            (0x28)
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#define MCF_SCM_PPMRS_DISABLE_ADC            (0x27)
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#define MCF_SCM_PPMRS_DISABLE_PIT1           (0x24)
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#define MCF_SCM_PPMRS_DISABLE_PIT0           (0x23)
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#define MCF_SCM_PPMRS_DISABLE_EPORT          (0x21)
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#define MCF_SCM_PPMRS_DISABLE_PORTS          (0x20)
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#define MCF_SCM_PPMRS_DISABLE_INTC           (0x11)
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#define MCF_SCM_PPMRS_DISABLE_DTIM3          (0x10)
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#define MCF_SCM_PPMRS_DISABLE_DTIM2          (0xF)
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#define MCF_SCM_PPMRS_DISABLE_DTIM1          (0xE)
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#define MCF_SCM_PPMRS_DISABLE_DTIM0          (0xD)
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#define MCF_SCM_PPMRS_DISABLE_QSPI           (0xA)
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#define MCF_SCM_PPMRS_DISABLE_I2C            (0x9)
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#define MCF_SCM_PPMRS_DISABLE_UART2          (0x7)
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#define MCF_SCM_PPMRS_DISABLE_UART1          (0x6)
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#define MCF_SCM_PPMRS_DISABLE_UART0          (0x5)
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#define MCF_SCM_PPMRS_DISABLE_DMA            (0x4)
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#define MCF_SCM_PPMRS_SET_CDG                (0x1)
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/* Bit definitions and macros for MCF_SCM_PPMRC */
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#define MCF_SCM_PPMRC_PPMRC(x)               (((x)&0x7F)<<0)
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#define MCF_SCM_PPMRC_ENABLE_ALL             (0x40)
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#define MCF_SCM_PPMRC_ENABLE_CFM             (0x2B)
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#define MCF_SCM_PPMRC_ENABLE_CAN             (0x2A)
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#define MCF_SCM_PPMRC_ENABLE_PWM             (0x29)
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#define MCF_SCM_PPMRC_ENABLE_GPT             (0x28)
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#define MCF_SCM_PPMRC_ENABLE_ADC             (0x27)
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#define MCF_SCM_PPMRC_ENABLE_PIT1            (0x24)
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#define MCF_SCM_PPMRC_ENABLE_PIT0            (0x23)
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#define MCF_SCM_PPMRC_ENABLE_EPORT           (0x21)
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#define MCF_SCM_PPMRC_ENABLE_PORTS           (0x20)
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#define MCF_SCM_PPMRC_ENABLE_INTC            (0x11)
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#define MCF_SCM_PPMRC_ENABLE_DTIM3           (0x10)
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#define MCF_SCM_PPMRC_ENABLE_DTIM2           (0xF)
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#define MCF_SCM_PPMRC_ENABLE_DTIM1           (0xE)
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#define MCF_SCM_PPMRC_ENABLE_DTIM0           (0xD)
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#define MCF_SCM_PPMRC_ENABLE_QSPI            (0xA)
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#define MCF_SCM_PPMRC_ENABLE_I2C             (0x9)
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#define MCF_SCM_PPMRC_ENABLE_UART2           (0x7)
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#define MCF_SCM_PPMRC_ENABLE_UART1           (0x6)
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#define MCF_SCM_PPMRC_ENABLE_UART0           (0x5)
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#define MCF_SCM_PPMRC_ENABLE_DMA             (0x4)
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#define MCF_SCM_PPMRC_CLEAR_CDG              (0x1)
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/* Bit definitions and macros for MCF_SCM_IPSBMT */
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#define MCF_SCM_IPSBMT_BMT(x)                (((x)&0x7)<<0)
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#define MCF_SCM_IPSBMT_BMT_CYCLES_1024       (0)
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#define MCF_SCM_IPSBMT_BMT_CYCLES_512        (0x1)
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#define MCF_SCM_IPSBMT_BMT_CYCLES_256        (0x2)
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#define MCF_SCM_IPSBMT_BMT_CYCLES_128        (0x3)
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#define MCF_SCM_IPSBMT_BMT_CYCLES_64         (0x4)
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#define MCF_SCM_IPSBMT_BMT_CYCLES_32         (0x5)
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#define MCF_SCM_IPSBMT_BMT_CYCLES_16         (0x6)
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#define MCF_SCM_IPSBMT_BMT_CYCLES_8          (0x7)
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#define MCF_SCM_IPSBMT_BME                   (0x8)
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/* Bit definitions and macros for MCF_SCM_PACR */
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#define MCF_SCM_PACR_ACCESS_CTRL0(x)         (((x)&0x7)<<0)
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#define MCF_SCM_PACR_LOCK0                   (0x8)
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#define MCF_SCM_PACR_ACCESS_CTRL1(x)         (((x)&0x7)<<0x4)
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#define MCF_SCM_PACR_LOCK1                   (0x80)
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/* Bit definitions and macros for MCF_SCM_GPACR */
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#define MCF_SCM_GPACR_ACCESS_CTRL(x)         (((x)&0xF)<<0)
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#define MCF_SCM_GPACR_LOCK                   (0x80)
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#endif /* __MCF52221_SCM_H__ */

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