OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52233_Eclipse/] [RTOSDemo/] [MCF5223x/] [MCF52235_EPHY.h] - Blame information for rev 578

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
2
 * Copyright Freescale Semiconductor Inc
3
 * All rights reserved.
4
 *
5
 * 2007/03/19 Revision: 0.91
6
 */
7
 
8
#ifndef __MCF52235_EPHY_H__
9
#define __MCF52235_EPHY_H__
10
 
11
 
12
/*********************************************************************
13
*
14
* Ethernet Physical Transceiver (EPHY)
15
*
16
*********************************************************************/
17
 
18
/* Register read/write macros */
19
#define MCF_EPHY_EPHYCTL0                    (*(vuint8 *)(&__IPSBAR[0x1E0000]))
20
#define MCF_EPHY_EPHYCTL1                    (*(vuint8 *)(&__IPSBAR[0x1E0001]))
21
#define MCF_EPHY_EPHYSR                      (*(vuint8 *)(&__IPSBAR[0x1E0002]))
22
 
23
 
24
/* Bit definitions and macros for MCF_EPHY_EPHYCTL0 */
25
#define MCF_EPHY_EPHYCTL0_EPHYIEN            (0x1)
26
#define MCF_EPHY_EPHYCTL0_EPHYWAI            (0x4)
27
#define MCF_EPHY_EPHYCTL0_LEDEN              (0x8)
28
#define MCF_EPHY_EPHYCTL0_DIS10              (0x10)
29
#define MCF_EPHY_EPHYCTL0_DIS100             (0x20)
30
#define MCF_EPHY_EPHYCTL0_ANDIS              (0x40)
31
#define MCF_EPHY_EPHYCTL0_EPHYEN             (0x80)
32
 
33
/* Bit definitions and macros for MCF_EPHY_EPHYCTL1 */
34
#define MCF_EPHY_EPHYCTL1_PHYADD(x)          (((x)&0x1F)<<0)
35
 
36
/* Bit definitions and macros for MCF_EPHY_EPHYSR */
37
#define MCF_EPHY_EPHYSR_EPHYIF               (0x1)
38
#define MCF_EPHY_EPHYSR_10DIS                (0x10)
39
#define MCF_EPHY_EPHYSR_100DIS               (0x20)
40
 
41
 
42
#endif /* __MCF52235_EPHY_H__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.