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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52233_Eclipse/] [RTOSDemo/] [MCF5223x/] [MCF52235_EPHY.h] - Blame information for rev 606

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Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
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 * Copyright Freescale Semiconductor Inc
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 * All rights reserved.
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 *
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 * 2007/03/19 Revision: 0.91
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 */
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#ifndef __MCF52235_EPHY_H__
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#define __MCF52235_EPHY_H__
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/*********************************************************************
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*
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* Ethernet Physical Transceiver (EPHY)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_EPHY_EPHYCTL0                    (*(vuint8 *)(&__IPSBAR[0x1E0000]))
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#define MCF_EPHY_EPHYCTL1                    (*(vuint8 *)(&__IPSBAR[0x1E0001]))
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#define MCF_EPHY_EPHYSR                      (*(vuint8 *)(&__IPSBAR[0x1E0002]))
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/* Bit definitions and macros for MCF_EPHY_EPHYCTL0 */
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#define MCF_EPHY_EPHYCTL0_EPHYIEN            (0x1)
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#define MCF_EPHY_EPHYCTL0_EPHYWAI            (0x4)
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#define MCF_EPHY_EPHYCTL0_LEDEN              (0x8)
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#define MCF_EPHY_EPHYCTL0_DIS10              (0x10)
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#define MCF_EPHY_EPHYCTL0_DIS100             (0x20)
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#define MCF_EPHY_EPHYCTL0_ANDIS              (0x40)
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#define MCF_EPHY_EPHYCTL0_EPHYEN             (0x80)
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/* Bit definitions and macros for MCF_EPHY_EPHYCTL1 */
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#define MCF_EPHY_EPHYCTL1_PHYADD(x)          (((x)&0x1F)<<0)
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/* Bit definitions and macros for MCF_EPHY_EPHYSR */
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#define MCF_EPHY_EPHYSR_EPHYIF               (0x1)
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#define MCF_EPHY_EPHYSR_10DIS                (0x10)
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#define MCF_EPHY_EPHYSR_100DIS               (0x20)
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#endif /* __MCF52235_EPHY_H__ */

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