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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52233_Eclipse/] [RTOSDemo/] [MCF5223x/] [MCF52235_GIACR.h] - Blame information for rev 675

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Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
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 * Copyright Freescale Semiconductor Inc
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 * All rights reserved.
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 *
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 * 2007/03/19 Revision: 0.91
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 */
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#ifndef __MCF52235_GIACR_H__
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#define __MCF52235_GIACR_H__
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/*********************************************************************
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*
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* Global Interrupt Acknowledge Control Registers Module (GIACR)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_GIACR_GSWIACK                    (*(vuint8 *)(&__IPSBAR[0xFE0]))
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#define MCF_GIACR_GL1IACK                    (*(vuint8 *)(&__IPSBAR[0xFE4]))
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#define MCF_GIACR_GL2IACK                    (*(vuint8 *)(&__IPSBAR[0xFE8]))
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#define MCF_GIACR_GL3IACK                    (*(vuint8 *)(&__IPSBAR[0xFEC]))
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#define MCF_GIACR_GL4IACK                    (*(vuint8 *)(&__IPSBAR[0xFF0]))
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#define MCF_GIACR_GL5IACK                    (*(vuint8 *)(&__IPSBAR[0xFF4]))
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#define MCF_GIACR_GL6IACK                    (*(vuint8 *)(&__IPSBAR[0xFF8]))
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#define MCF_GIACR_GL7IACK                    (*(vuint8 *)(&__IPSBAR[0xFFC]))
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#define MCF_GIACR_GLIACK(x)                  (*(vuint8 *)(&__IPSBAR[0xFE4 + ((x-1)*0x4)]))
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/* Bit definitions and macros for MCF_GIACR_GSWIACK */
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#define MCF_GIACR_GSWIACK_VECTOR(x)          (((x)&0xFF)<<0)
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/* Bit definitions and macros for MCF_GIACR_GLIACK */
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#define MCF_GIACR_GLIACK_VECTOR(x)           (((x)&0xFF)<<0)
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#endif /* __MCF52235_GIACR_H__ */

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