1 |
578 |
jeremybenn |
/* Coldfire C Header File
|
2 |
|
|
* Copyright Freescale Semiconductor Inc
|
3 |
|
|
* All rights reserved.
|
4 |
|
|
*
|
5 |
|
|
* 2007/03/19 Revision: 0.91
|
6 |
|
|
*/
|
7 |
|
|
|
8 |
|
|
#ifndef __MCF52235_UART_H__
|
9 |
|
|
#define __MCF52235_UART_H__
|
10 |
|
|
|
11 |
|
|
|
12 |
|
|
/*********************************************************************
|
13 |
|
|
*
|
14 |
|
|
* Universal Asynchronous Receiver Transmitter (UART)
|
15 |
|
|
*
|
16 |
|
|
*********************************************************************/
|
17 |
|
|
|
18 |
|
|
/* Register read/write macros */
|
19 |
|
|
#define MCF_UART0_UMR1 (*(vuint8 *)(&__IPSBAR[0x200]))
|
20 |
|
|
#define MCF_UART0_UMR2 (*(vuint8 *)(&__IPSBAR[0x200]))
|
21 |
|
|
#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x204]))
|
22 |
|
|
#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x204]))
|
23 |
|
|
#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x208]))
|
24 |
|
|
#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x20C]))
|
25 |
|
|
#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x20C]))
|
26 |
|
|
#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x210]))
|
27 |
|
|
#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x210]))
|
28 |
|
|
#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x214]))
|
29 |
|
|
#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x214]))
|
30 |
|
|
#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x218]))
|
31 |
|
|
#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x21C]))
|
32 |
|
|
#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x234]))
|
33 |
|
|
#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x238]))
|
34 |
|
|
#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x23C]))
|
35 |
|
|
|
36 |
|
|
#define MCF_UART1_UMR1 (*(vuint8 *)(&__IPSBAR[0x240]))
|
37 |
|
|
#define MCF_UART1_UMR2 (*(vuint8 *)(&__IPSBAR[0x240]))
|
38 |
|
|
#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x244]))
|
39 |
|
|
#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x244]))
|
40 |
|
|
#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x248]))
|
41 |
|
|
#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x24C]))
|
42 |
|
|
#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x24C]))
|
43 |
|
|
#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x250]))
|
44 |
|
|
#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x250]))
|
45 |
|
|
#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x254]))
|
46 |
|
|
#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x254]))
|
47 |
|
|
#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x258]))
|
48 |
|
|
#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x25C]))
|
49 |
|
|
#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x274]))
|
50 |
|
|
#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x278]))
|
51 |
|
|
#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x27C]))
|
52 |
|
|
|
53 |
|
|
#define MCF_UART2_UMR1 (*(vuint8 *)(&__IPSBAR[0x280]))
|
54 |
|
|
#define MCF_UART2_UMR2 (*(vuint8 *)(&__IPSBAR[0x280]))
|
55 |
|
|
#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x284]))
|
56 |
|
|
#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x284]))
|
57 |
|
|
#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x288]))
|
58 |
|
|
#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x28C]))
|
59 |
|
|
#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x28C]))
|
60 |
|
|
#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x290]))
|
61 |
|
|
#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x290]))
|
62 |
|
|
#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x294]))
|
63 |
|
|
#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x294]))
|
64 |
|
|
#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x298]))
|
65 |
|
|
#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x29C]))
|
66 |
|
|
#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x2B4]))
|
67 |
|
|
#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x2B8]))
|
68 |
|
|
#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x2BC]))
|
69 |
|
|
|
70 |
|
|
#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x200 + ((x)*0x40)]))
|
71 |
|
|
#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x204 + ((x)*0x40)]))
|
72 |
|
|
#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x204 + ((x)*0x40)]))
|
73 |
|
|
#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x208 + ((x)*0x40)]))
|
74 |
|
|
#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x20C + ((x)*0x40)]))
|
75 |
|
|
#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x20C + ((x)*0x40)]))
|
76 |
|
|
#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x210 + ((x)*0x40)]))
|
77 |
|
|
#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x210 + ((x)*0x40)]))
|
78 |
|
|
#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x214 + ((x)*0x40)]))
|
79 |
|
|
#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x214 + ((x)*0x40)]))
|
80 |
|
|
#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x218 + ((x)*0x40)]))
|
81 |
|
|
#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x21C + ((x)*0x40)]))
|
82 |
|
|
#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x234 + ((x)*0x40)]))
|
83 |
|
|
#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x238 + ((x)*0x40)]))
|
84 |
|
|
#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x23C + ((x)*0x40)]))
|
85 |
|
|
|
86 |
|
|
/* Bit definitions and macros for MCF_UART_UMR */
|
87 |
|
|
#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0)
|
88 |
|
|
#define MCF_UART_UMR_BC_5 (0)
|
89 |
|
|
#define MCF_UART_UMR_BC_6 (0x1)
|
90 |
|
|
#define MCF_UART_UMR_BC_7 (0x2)
|
91 |
|
|
#define MCF_UART_UMR_BC_8 (0x3)
|
92 |
|
|
#define MCF_UART_UMR_PT (0x4)
|
93 |
|
|
#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3)
|
94 |
|
|
#define MCF_UART_UMR_ERR (0x20)
|
95 |
|
|
#define MCF_UART_UMR_RXIRQ (0x40)
|
96 |
|
|
#define MCF_UART_UMR_RXRTS (0x80)
|
97 |
|
|
#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
|
98 |
|
|
#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
|
99 |
|
|
#define MCF_UART_UMR_PM_NONE (0x10)
|
100 |
|
|
#define MCF_UART_UMR_PM_FORCE_HI (0xC)
|
101 |
|
|
#define MCF_UART_UMR_PM_FORCE_LO (0x8)
|
102 |
|
|
#define MCF_UART_UMR_PM_ODD (0x4)
|
103 |
|
|
#define MCF_UART_UMR_PM_EVEN (0)
|
104 |
|
|
#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0)
|
105 |
|
|
#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7)
|
106 |
|
|
#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8)
|
107 |
|
|
#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF)
|
108 |
|
|
#define MCF_UART_UMR_TXCTS (0x10)
|
109 |
|
|
#define MCF_UART_UMR_TXRTS (0x20)
|
110 |
|
|
#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6)
|
111 |
|
|
#define MCF_UART_UMR_CM_NORMAL (0)
|
112 |
|
|
#define MCF_UART_UMR_CM_ECHO (0x40)
|
113 |
|
|
#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
|
114 |
|
|
#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
|
115 |
|
|
|
116 |
|
|
/* Bit definitions and macros for MCF_UART_USR */
|
117 |
|
|
#define MCF_UART_USR_RXRDY (0x1)
|
118 |
|
|
#define MCF_UART_USR_FFULL (0x2)
|
119 |
|
|
#define MCF_UART_USR_TXRDY (0x4)
|
120 |
|
|
#define MCF_UART_USR_TXEMP (0x8)
|
121 |
|
|
#define MCF_UART_USR_OE (0x10)
|
122 |
|
|
#define MCF_UART_USR_PE (0x20)
|
123 |
|
|
#define MCF_UART_USR_FE (0x40)
|
124 |
|
|
#define MCF_UART_USR_RB (0x80)
|
125 |
|
|
|
126 |
|
|
/* Bit definitions and macros for MCF_UART_UCSR */
|
127 |
|
|
#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0)
|
128 |
|
|
#define MCF_UART_UCSR_TCS_SYS_CLK (0xD)
|
129 |
|
|
#define MCF_UART_UCSR_TCS_CTM16 (0xE)
|
130 |
|
|
#define MCF_UART_UCSR_TCS_CTM (0xF)
|
131 |
|
|
#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4)
|
132 |
|
|
#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
|
133 |
|
|
#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
|
134 |
|
|
#define MCF_UART_UCSR_RCS_CTM (0xF0)
|
135 |
|
|
|
136 |
|
|
/* Bit definitions and macros for MCF_UART_UCR */
|
137 |
|
|
#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0)
|
138 |
|
|
#define MCF_UART_UCR_RX_ENABLED (0x1)
|
139 |
|
|
#define MCF_UART_UCR_RX_DISABLED (0x2)
|
140 |
|
|
#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2)
|
141 |
|
|
#define MCF_UART_UCR_TX_ENABLED (0x4)
|
142 |
|
|
#define MCF_UART_UCR_TX_DISABLED (0x8)
|
143 |
|
|
#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4)
|
144 |
|
|
#define MCF_UART_UCR_NONE (0)
|
145 |
|
|
#define MCF_UART_UCR_RESET_MR (0x10)
|
146 |
|
|
#define MCF_UART_UCR_RESET_RX (0x20)
|
147 |
|
|
#define MCF_UART_UCR_RESET_TX (0x30)
|
148 |
|
|
#define MCF_UART_UCR_RESET_ERROR (0x40)
|
149 |
|
|
#define MCF_UART_UCR_RESET_BKCHGINT (0x50)
|
150 |
|
|
#define MCF_UART_UCR_START_BREAK (0x60)
|
151 |
|
|
#define MCF_UART_UCR_STOP_BREAK (0x70)
|
152 |
|
|
|
153 |
|
|
/* Bit definitions and macros for MCF_UART_URB */
|
154 |
|
|
#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0)
|
155 |
|
|
|
156 |
|
|
/* Bit definitions and macros for MCF_UART_UTB */
|
157 |
|
|
#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0)
|
158 |
|
|
|
159 |
|
|
/* Bit definitions and macros for MCF_UART_UIPCR */
|
160 |
|
|
#define MCF_UART_UIPCR_CTS (0x1)
|
161 |
|
|
#define MCF_UART_UIPCR_COS (0x10)
|
162 |
|
|
|
163 |
|
|
/* Bit definitions and macros for MCF_UART_UACR */
|
164 |
|
|
#define MCF_UART_UACR_IEC (0x1)
|
165 |
|
|
|
166 |
|
|
/* Bit definitions and macros for MCF_UART_UIMR */
|
167 |
|
|
#define MCF_UART_UIMR_TXRDY (0x1)
|
168 |
|
|
#define MCF_UART_UIMR_FFULL_RXRDY (0x2)
|
169 |
|
|
#define MCF_UART_UIMR_DB (0x4)
|
170 |
|
|
#define MCF_UART_UIMR_COS (0x80)
|
171 |
|
|
|
172 |
|
|
/* Bit definitions and macros for MCF_UART_UISR */
|
173 |
|
|
#define MCF_UART_UISR_TXRDY (0x1)
|
174 |
|
|
#define MCF_UART_UISR_FFULL_RXRDY (0x2)
|
175 |
|
|
#define MCF_UART_UISR_DB (0x4)
|
176 |
|
|
#define MCF_UART_UISR_COS (0x80)
|
177 |
|
|
|
178 |
|
|
/* Bit definitions and macros for MCF_UART_UBG1 */
|
179 |
|
|
#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0)
|
180 |
|
|
|
181 |
|
|
/* Bit definitions and macros for MCF_UART_UBG2 */
|
182 |
|
|
#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0)
|
183 |
|
|
|
184 |
|
|
/* Bit definitions and macros for MCF_UART_UIP */
|
185 |
|
|
#define MCF_UART_UIP_CTS (0x1)
|
186 |
|
|
|
187 |
|
|
/* Bit definitions and macros for MCF_UART_UOP1 */
|
188 |
|
|
#define MCF_UART_UOP1_RTS (0x1)
|
189 |
|
|
|
190 |
|
|
/* Bit definitions and macros for MCF_UART_UOP0 */
|
191 |
|
|
#define MCF_UART_UOP0_RTS (0x1)
|
192 |
|
|
|
193 |
|
|
|
194 |
|
|
#endif /* __MCF52235_UART_H__ */
|