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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ColdFire_MCF52259_CodeWarrior/] [Freescale_Headers/] [MCF52259_BWT.h] - Blame information for rev 597

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Line No. Rev Author Line
1 578 jeremybenn
/* Coldfire C Header File
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 * Copyright Freescale Semiconductor Inc
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 * All rights reserved.
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 *
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 * 2008/04/17 Revision: 0.2
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 *
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 * (c) Copyright UNIS, spol. s r.o. 1997-2008
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 * UNIS, spol. s r.o.
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 * Jundrovska 33
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 * 624 00 Brno
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 * Czech Republic
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 * http      : www.processorexpert.com
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 * mail      : info@processorexpert.com
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 */
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#ifndef __MCF52259_BWT_H__
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#define __MCF52259_BWT_H__
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/*********************************************************************
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*
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* Backup Watchdog Timer Module (BWT)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_BWT_WCR                          (*(vuint16*)(0x40140000))
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#define MCF_BWT_WMR                          (*(vuint16*)(0x40140002))
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#define MCF_BWT_WCNTR                        (*(vuint16*)(0x40140004))
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#define MCF_BWT_WSR                          (*(vuint16*)(0x40140006))
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/* Bit definitions and macros for MCF_BWT_WCR */
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#define MCF_BWT_WCR_EN                       (0x1)
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#define MCF_BWT_WCR_DBG                      (0x2)
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#define MCF_BWT_WCR_DOZE                     (0x4)
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#define MCF_BWT_WCR_WAIT                     (0x8)
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#define MCF_BWT_WCR_STOP                     (0x10)
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/* Bit definitions and macros for MCF_BWT_WMR */
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#define MCF_BWT_WMR_WM(x)                    (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_BWT_WCNTR */
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#define MCF_BWT_WCNTR_WC(x)                  (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_BWT_WSR */
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#define MCF_BWT_WSR_WS(x)                    (((x)&0xFFFF)<<0)
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#endif /* __MCF52259_BWT_H__ */

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