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jeremybenn |
/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2008/04/17 Revision: 0.2
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*
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* (c) Copyright UNIS, spol. s r.o. 1997-2008
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* UNIS, spol. s r.o.
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* Jundrovska 33
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* 624 00 Brno
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* Czech Republic
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* http : www.processorexpert.com
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* mail : info@processorexpert.com
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*/
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#ifndef __MCF52259_FBCS_H__
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#define __MCF52259_FBCS_H__
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/*********************************************************************
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*
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* Mini-FlexBus Chip Select Module (FBCS)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_FBCS0_CSAR (*(vuint32*)(0x40000080))
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#define MCF_FBCS0_CSMR (*(vuint32*)(0x40000084))
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#define MCF_FBCS0_CSCR (*(vuint32*)(0x40000088))
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#define MCF_FBCS1_CSAR (*(vuint32*)(0x4000008C))
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#define MCF_FBCS1_CSMR (*(vuint32*)(0x40000090))
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#define MCF_FBCS1_CSCR (*(vuint32*)(0x40000094))
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#define MCF_FBCS_CSAR(x) (*(vuint32*)(0x40000080 + ((x)*0xC)))
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#define MCF_FBCS_CSMR(x) (*(vuint32*)(0x40000084 + ((x)*0xC)))
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#define MCF_FBCS_CSCR(x) (*(vuint32*)(0x40000088 + ((x)*0xC)))
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/* Bit definitions and macros for MCF_FBCS_CSAR */
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#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
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/* Bit definitions and macros for MCF_FBCS_CSMR */
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#define MCF_FBCS_CSMR_V (0x1)
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#define MCF_FBCS_CSMR_WP (0x100)
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#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
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#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
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#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
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#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
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#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
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#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
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#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)
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#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)
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#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)
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#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)
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#define MCF_FBCS_CSMR_BAM_16M (0xFF0000)
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#define MCF_FBCS_CSMR_BAM_8M (0x7F0000)
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#define MCF_FBCS_CSMR_BAM_4M (0x3F0000)
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#define MCF_FBCS_CSMR_BAM_2M (0x1F0000)
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#define MCF_FBCS_CSMR_BAM_1M (0xF0000)
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#define MCF_FBCS_CSMR_BAM_1024K (0xF0000)
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#define MCF_FBCS_CSMR_BAM_512K (0x70000)
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#define MCF_FBCS_CSMR_BAM_256K (0x30000)
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#define MCF_FBCS_CSMR_BAM_128K (0x10000)
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#define MCF_FBCS_CSMR_BAM_64K (0)
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/* Bit definitions and macros for MCF_FBCS_CSCR */
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#define MCF_FBCS_CSCR_BSTW (0x8)
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#define MCF_FBCS_CSCR_BSTR (0x10)
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#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)
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#define MCF_FBCS_CSCR_PS_8 (0x40)
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#define MCF_FBCS_CSCR_PS_16 (0x80)
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#define MCF_FBCS_CSCR_AA (0x100)
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#define MCF_FBCS_CSCR_MUX (0x200)
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#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)
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#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)
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#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)
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#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)
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#define MCF_FBCS_CSCR_SWSEN (0x800000)
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#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)
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#endif /* __MCF52259_FBCS_H__ */
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